ARM’s verified the SOI SPICE models accuracy in its physical IP, helping designers to simulate their chips prior to tape-out as well as helping the foundries to tune their SOI SPICE models.
SPICE models are used for checking the integrity of circuit designs and predicting circuit behavior prior to commiting a design to silicon. Each SPICE model is based on critical electrical response information that is specific to the fab that will produce the chips. SPICE models that predict actual results with the greatest accuracy enable designers to fully exploit design trade-offs in terms of power, performance and area (PPA).
ARM has recently developed new methodology(1) to validate the timing verification for SOI-based chips, and is currently working with foundry clients to tune their SPICE models accordingly.
To maximize accuracy, partially-depleted (PD) SOI timing verification must take into account the “history effect”, wherein the body voltage of a transistor is a function of its recent on/off history. While early SOI adopters had to deal with this on their own, for today’s designers the history effect is just another “corner” accounted for in the physical IP libraries, making it essentially transparent in the design flow.
We have done the work behind the scenes to ensure that both the foundries and fabless designers have models in which they can be completely confident.
For standard cell libraries, ARM characterizes and incorporates timing verification in the library (.lib) files. SOI design requires two libraries per process-voltage-temperature (PVT) corner (whereas bulk silicon design uses one library per corner). For each function, a Max-SOI is characterized for the slowest operation possible, while a Min-SOI library is characterized for the fastest possible operation due to the history effect. The timing analysis tool uses these libraries.
However, it’s important for the designers to have real and accurate timing data in order to avoid too much pessimism during the timing closure phase of circuit design. ARM’s new measurement process correctly characterizes the history effect. This enables designers to reach the highest possible frequencies with a high confidence level.
ARM has developed and proven this reliable timing verification methodology on a 45nm SOI standard cell library. This methodology, which can be applied to any cell, also enables our foundry customers to fine tune their SPICE models, dissociating NMOS from PMOS (rise/fall transition). The same methodology is applied to the 32 and 22nm nodes.
The methodology uses both floating-body (FB) and body-contacted (BC) cells (which should not have any history effect at all). It extracts the history effect delay chain timing measurements. Three types of delay chains (FB/FB, BC/BC and FB/BC) are implemented, measured, simulated and compared with a foundry’s actual silicon results.
Essentially, we measure the chain delay of the rise and fall transistions, for the two first switches corresponding to DC0 and DC1 conditions known to deliver the worst case history effect in most cases. We also measure the delays when the steady-state is reached after the signal has been toggling for a long time (typically a few ms).
The measurements are then compared to SPICE simulation results.
Taking one foundry’s BC/BC delay chain as an example, cumulated measurements indicated that 95% of the measurements had a better than 2% accuracy and that the BC chain was exempt of history effect as expected. The silicon measurements were found to be close to the simulation results using the typical process corner. They indicated that the temperature inversion point was close to 0.8V.
A good correlation was obtained between the FB/FB and the FB/BC extracted history effect. However, the simulated history effect spread more than the measured one, which indicated that the SPICE models needed to be retuned to be more accurate in the history effect prediction and then avoid too much pessimism.
ARM helped the foundry retune the SPICE models for greater accuracy. The same methodology has now been used for modeling at the 32nm and 22nm nodes, and for fast and slow process corners.
 JL Pelloie et al. Timing Verification of a 45nm SOI Standard-Cell Library. IEEE SOI Conference 2010.