The recent LetiDays FD-SOI workshop in Grenoble was the biggest show of force to date for the burgeoning FD-SOI ecosystem. In addition to a raft of excellent presentations, we learned two very big pieces of news. First, GlobalFoundries provided more insights into their upcoming FD-SOI offering. And second, designers opting for Samsung’s 28nm FD-SOI offering can get all their IP (with Samsung numbering) directly from (and supported by) Synopsys.
In fact the workshop marked the first time that the entire ecosystem took to the same stage. It was great. Here’s a recap.
Although not “officially” announced yet, GlobalFoundries was there to talk about their FD-SOI offering. In his presentation on Design/Technology Opimizations for FD-SOI, Gerde Teepe, Design Enablement Director at GF in Dresden, said theirs would be 22nm FD-SOI. That translates to a 14nm front-end with two double-patterning layers, and 28nm upper interconnect layers in the back-end. Currently working on body-biasing generators, they’re on target to be completely ready for business by the end of the year (see slide below).
The decision to go with a 14nm front-end was customer driven, said Dr. Teepe. They wanted a shrink, but they didn’t want to drive up the cost, hence the 28nm back-end.
The conference made clear that there’s no more “chicken-egg” IP problem for FD-SOI. IP is ready, and everyone wants to talk about it.
Kelvin Low, Senior Director of Foundry Marketing at Samsung said they’re driving 28nm FD-SOI to get “massive support” for the ecosystem. It’s positioned as cost-effective, low-power solution for a long-lived node, he said, and yes, they’re getting new customers. Wafer level reliability tests were successfully completed last September, and product level reliability tests finished up in March.
This set the stage for the big IP news from Synopsys. Senior Director Mike McAweeney said that Synopsys is supplying both ST’s IP plus their own Synopsys IP to Samsung customers, with Samsung part numbers and Synopsys support.
IP is hot at Cadence, too, said Amir Bar-Niv, Senior Group Director for Design IP Marketing. Since February they’ve doubled the number of available IP to meet customer demand.
Proof of rising demand also came from CMP, which organizes multi-project wafer runs for 28nm FD-SOI. Over 191 customers in 32 countries have requested the PDK. (Click here to learn more about the service.)
New approaches to body biasing were mentioned in a number of presentations, including talks by ST, GF and Leti. GF’s working on their body-biasing generator for 22nm. ST’s got a new-generation compact body bias generator especially for IoT. And ST and Leti are working on a new generation of “adaptive” body biasing, adding another 30% in power savings.
In a very interesting keynote, Professor Boris Thurmann of Stanford looked at mixed-signal IC design. We’re about to fuse the physical and virtual worlds, he said, in a third paradigm: IoT. He cited lots of advantages of FD-SOI in meeting the ultra-low-power and RF challenges faced by analog designers.
FD-SOI attacks variability with tighter process corners and less random mismatch than competing processes. It enables “…a simpler design process, shorter design cycles, improved yield or improved performance at given yield”. You get outstanding switch performance (see slide) and better ways of dealing with junction capacitance.
FD-SOI renders a shift in RF to translational circuits (no inductors) more practical. It also enables smaller but higher performance digital blocks in apps for things like object recognition – and the list goes on.
Naim Ben-Hmida, Senior Manager of Mixed-Signal Design & Test at Ciena (they used to be Nortel), talked about optical transceivers in 28nm FD-SOI. We’re heading towards terabyte modems connecting cities, he said, putting enormous pressure on short-reach optical networks. Their 100Gb/s metro-regional transceiver integrates what was two ASICs and an FPGA into a single 28nm FD-SOI transceiver ASIC. In addition to power and performance, FD-SOI was the right solution for both time-to-market and cost, he said.
In closing, let’s swing back to the conference opening keynote by Thomas Skotnicki, ST’s FD-SOI godfather (you can also read his 2011 ASN piece on FD-SOI here). The key to the FD-SOI success story, he reminded us, is the thin buried oxide. That’s been the essence of his work for the last 26 years.
“You must believe in what you’re doing,” he said. Proof of his perseverence: his breakthrough paper was twice rejected by the IEEE in 1999 – but once they accepted it in 2000, they named it best paper of the year.
He gave a big thank you to Soitec for breakthroughs in SOI wafer manufacturing – the ultra-thin silicon and ultra-thin insulating BoX combination were the enabling tour-de-force.
Skotnicki added that for 14nm Soitec has taken the wafers to new heights. “At 14nm, we are very robust,” he concluded, noting that the Leti/ST VLSI Symposium 2015 (O. Faynot et al) paper showed 14nm FD-SOI matching or beating 14nm FinFET performance at low voltages. The future is wide open. FD-SOI, he says can go down to 5nm (compared to 3nm for FinFET).
And clearly, he’s a man who knows the future.