If you’re going to Semicon West this year, be sure to attend the SOI Consortium’s workshop on how IoT is driving the SOI supply chain. There’s a great line-up of speakers – see the program below.
IoT means many things to many people but everyone agrees it’s here and growing quickly. IoT, including machine learning and movement to the edge, is fueling innovation as the high compute and ultra-low energy requirements are pushing technology to deliver on these needs. The well-known characteristics defining IoT of “Sense”, “Compute”, and “Act” put additional burden on technology to full these requirements across a variety of use cases and environments without sacrificing reliability or quality.
All the various forms of SOI technology from FD-SOI to High-Voltage to RF-SOI, are uniquely situated to deliver on the promise of today’s as well as tomorrow’s IoT roadmap. The supply chain for all forms of SOI technology is in place. This workshop will discuss the current and future solutions from a supply chain perspective.
Speakers include experts from SOI Consortium members Applied Materials, NXP, GlobalFoundries and Soitec.
Entitled The Internet of Things, Driver of the SOI Supply Chain, the workshop will take place at the Moscone Center South, Wednesday July 10th in Room 301. It will run from 1 pm until 4:30 pm. Anyone and everyone who is registered for Semicon West is welcome. Here is the sign-up page.
It’s a great program:
1:00pm – Welcome by Semi
1:10pm – IoT/AI/Edge Market – Using SOI Through-out, Jon Cheek, Senior Director, NXP
1:35pm – The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials
2:00pm – The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, GlobalFoundries
2:25pm – Engineered Substrates – Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec
2:50pm – Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG
3:15pm – Panel: The Internet of Things, Driver of the SOI Supply Chain, Moderator: Carlos Mazure, Chairman, SOI Industry Consortium. Panelists include:
4:05pm – Closing remarks, Carlos Mazure, Chairman, SOI Industry Consortium
4:20pm – End
This is a great chance to learn more about SOI and the SOI Consortium. Don’t miss it!
And while you’re at West, you should also check out a related event. SOI Consortium member Leti will be teaming up with Fraunhofer for a workshop entitled New Paradigms in Microelectronics–Providing R&D for the 21st Century. That happens at the nearby W Hotel in San Francisco on Tuesday, July 9th at 5:00pm. Click here for more information on that.
Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.
Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design & the SOI Consortium’s IP/EDA roundup.
If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung & more) here and part 2 here (Synaptics, GlobalFoundries & more). Almost all of the presentations are now freely available under “events” on the consortium website – or just click here to get them.
The presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).
He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge & Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.
First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.
Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI.
What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.
Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.
How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.
Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R&D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision & smart sensing, embedded processing & fusion, new computing paradigms and deep learning, ultra-low power computing nodes & framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.
SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.
While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day.
The last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith.
Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license.
So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.
From the audience, NXP VP & longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary,” he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm.
And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”
During the half day workshop current and future solutions from a supply chain perspective have been discussed.
IoT/AI/Edge Market – Using SOI through-out, Jon Cheek, Senior Director, NXP
The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials
The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, Globalfoundries
>Engineered Substrates – Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec
Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG
Panel: The Internet of Things, Driver of the SOI Supply Chain
Moderator: Carlos Mazure, Chairman, SOI Industry Consortium
Jon Cheek, Sr. Director, NXP
Manish Hemkar, Director, AMAT
Yoshio Kitahara, President & Managing Director, Kokusai Europe
Jon Kretzschmar, Manager of Product Sales & Marketing, TEL America
Thomas Piliszczuk, EVP Strategy, Soitec
Thomas Uhrmann, Head of Business Development, EVG
Leah Schuth Director Technical Marketing, Arm
Jerome Ramel, Analyst, Exane-Paribas
FD-SOI has hit Q1 with terrific momentum, both in terms of visibility into products and in press coverage. In case you missed them, here are three articles you should definitely read:
But, if you don’t have time to read them all right away, here are some highlights to tide you over til you do.
Ed Sperling at SemiEngineering sees FD-SOI adoption “… gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs.”
After recounting the advantages (with which ASN readers are well familiar), he notes that two things have changed in our industry. First, fewer and fewer companies can afford to design in the most advanced FinFET nodes. And second: there are enough emerging markets where power is critical, but there won’t necessarily be the billions of units per chip needed to amortize exorbitant design costs.
In particular, for FD-SOI adoption he cites, “…the inferencing stage of machine learning [note: that happens in “edge” devices], base-stations, IoT and IIoT, bitcoin mining, 5G, radar, and a variety of automotive applications.” (GF’s Jamie Schaeffer makes the technical case in the article for NB-IoT and automotive if you want more info.)
ST’s Giorgio Cesana makes an interesting point about body biasing (that I hadn’t hear before) re: uni-direction vs. bi-directional. Currently, he explains, body biasing is uni-directional – although you can use it now in such a way that is effectively bi-directional. However, after the 22nm node, it will become truly bi-directional, which will enable wider swings for power savings. (For those concerned about pre-mature chip aging, see the full article for explanations by experts from Soitec who explain why that’s not a problem after all.)
Cesana also points out that the kind of chips leveraging FD-SOI are not the kind of chips that will need to move to a new node every year. They’re looking for power savings, not shrink. Sperling goes on to make an interesting observation about Intel/MobileEye and power savings vs. shrink – by all means read what he has to say about that….
In conclusion, Sperling asserts that we are now witnessing a shift in the semi supply chain essentially dovetailing with the expansion of FD-SOI adoption and its ecosystem, wherein “…as new markets open up, chipmakers are finding themselves much closer to the application than in the past.”
All in all a great read – don’t miss it.
David Lammers (who you probably know from SST) wrote about products on FD-SOI for GF’s Foundry Files in 22FDX Shows IoT Traction at MWC 2018. A number of start-ups will be showing products on GF’s 22FDX (FD-SOI) technology at Mobile World Congress.
For example, Nanotel Technology is using 22FDX to “…reduce power consumption for its mixed-signal NB-IoT modem.” Lammers interviewed the company’s CTO, Anup Savla, who explained, “We have a digital engine, a processor, designed around IoT applications, where the emphasis is on low power and low leakage. With 22FDX there are knobs that are available to turn down the power and leakage. The opportunities to do that are unparalleled, and you just don’t get that kind of opportunity from bulk CMOS.” A significant part to this design is analog – which of course really benefits from FD-SOI.
Riot Micro on the other hand, has designed an all-digital cellular modem for LTE Cat-M and NB-IOT. There’s no DSP, and big parts of the chip can be shut down as needed to save power for long-term battery operation in the field (get more details in the full GF blog). Several major cellular carriers are on track to certify it this year, and a Middle Eastern customer plans to incorporate it into an emergency-alert system. The company’s CEO, Peter Wong told Lammers, “With 22FDX, the value proposition for us is potential power and area savings.” They also leveraged the growing 22FDX IP ecosystem to accelerate TTM.
Dream Chip Technologies, which as Lammers reminds us, showed their multi-core vision processor at MWC last year, says that now “…the design is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives.”
Verisilicon, an SOI Consortium member and a major FD-SOI champion in China will be teaming up with GF show their dual-mode connectivity solutions (which we first heard about last year). GF and VeriSilicon have a suite of IP so that customers can create single-chip, low-power wide-area (LPWA) solutions that support either LTE-M (for the US) or NB-IoT (for Asia & Europe). The IP covers integrated baseband, power management, RF radio and front-end components.
Lammers also cited Anubhav Gupta, GF’s director of strategic marketing and business development for IoT, AI & Machine Learning. He said they’ve got customers taking older multi-chip designs and re-creating them as single-chip solutions in 22FDX for better performance and savings in area, power and cost. Gupta noted that with body biasing in digital designs, they can operate down to 0.4V with standby leakage currents of less than one picoamp per micron. And when embedded MRAM is used in tandem with on-chip SRAM, off-chip flash can be completely eliminated.
In a wide-ranging interview (see part 7, which focuses on FD-SOI), GF CTO Gary Patton told Anandtech’s Ian Cutress that, “FinFET is a great technology for [performance at any cost], but if you’re looking for something that is more in the consumer space, you need to balance performance with power and cost, you know FD-SOI is a clear winner.”
Patton told Cutress that they have working 12FDX devices in NY that are already close to reaching performance targets. They’ll be in risk production in early 2019.
Meanwhile in 22FDX, Patton talked about the different flavors, including RF, ULP, UL leakage and mmWave, and how well suited they are for target applications especially in automotive and IoT. Elsewhere in the interview he mentioned that potential customers in the cryptocurrency mining businesses are looking at 22FDX, and that ST will be using it to do some “incredible products”.
All in all – products and press – it’s a really fine Q1.
Over the last few weeks there’s been another burst of activity in the FD-SOI arena. A new round of articles, videos and conferences are making FD-SOI the centerpieces. Here’s a quick round-up of things you won’t want to miss.
Info on GlobalFoundries 22nm FD-SOI offering just keeps on coming. Following the ASN roundup of info from the summer and fall (missed it? read it here), they’ve posted yet another excellent FD-SOI video:
How to optimize power and performance with 22FDX™ Platform body-biasing – Dr. Jamie Schaeffer gives a quick (under 3 minute) guide to the basics of front and reverse body-biasing, and the GF approach to a dynamic trade-off between power and performance . He explains how forward body bias (FBB) boosts performance at both high and low voltages, and how reverse body bias (RBB) cuts leakage for the lowest standby power. He also touches on FBB techniques for analog/RF designs.
They’re back! Though they’ve been pretty quiet recently, this latest Samsung video on their 28nm FD-SOI foundry offering hits right at the heart of IoT. Entitled The IoT Revolution and Samsung Foundry’s 28nm FD-SOI, the fun two-minute spot features two runners talking shop during a break. She asks: Is there a lot of design ecosystem support for FD-SOI? He answers: Absolutely. And he goes on to talk about the EDA/IP ecosystem they’re building. It ends on this tantalizing note: He: So you’re done? She: Not! Race you to the next station! He: Oh, it’s on!
With reader interest high and higher, FD-SOI continues to get great coverage in SemiWiki.com. Here are some recent good reads:
IP-SoC Rebound in 2015 ! – IP expert Eric Esteve covers FD-SOI highlights from the upcoming IP-SOC 2015 conference in Grenoble, France (2-3 December 2015), including these presentations (full program here):
28nm FD-SOI: A Unique Sweet Spot Poised to Grow – Pawan Fangaria explains why “…today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on.”
Globalfoundries 22FDX Technology Shows Advantages in PPA over 28nm Node – Tom Simon was at ARM Techcon, where he attended a talk sponsored by Cadence on the topic of using GlobalFoundries 22nm FD-SOI process to implement a quad core ARM Cortex-A17. He shares a number of the key slides in this informative blog.
SemiEngineering Editor-in-Chief Ed Sperling continues his great line-up of incisive interviews. In Increasing Challenges At Advanced Nodes, he gets some spot-on FD-SOI quotes from GlobalFoundries CTO Gary Patton, including:
A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.
After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.
When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:
GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.
Here are some of the resources posted on the website as of this writing:
Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides
FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).
Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI Technology – NEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.
Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.
Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.
Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.
You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”
Which is great news for the SOI ecosystem and the entire industry.
It’s happening! GlobalFoundries is having an FD-SOI technical webinar on the 24th of June 2015. Don’t wait – sign up now – click here to get the registration document.
Here’s the information we know so far.
Title: Extending Moore’s Law with FD-SOI Technology
When: June 24, 2015, 10:00 am Pacific Time
Speaker: Jamie Schaeffer, Ph.D., FDSOI Product Line Manager, GLOBALFOUNDRIES
Where: a computer or mobile device near you!
Jamie Shaeffer’s been on the front lines of FD-SOI in recent days. In case you missed ASN’s recap of EDPS coverage (you can still read it here), he was on the panel discussion, agreeing that FinFET and FD-SOI can and will co-exist. His comment (as noted by Richard Goering of Cadence) really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
Also noted by Richard, Jamie was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
So while we’re waiting for “The Big GF FD-SOI Announcement”, we have a growing body of reports from industry events. In a SemiWiki blog (read it here), for example, Scotten Jones reported that GF’s Thomas Caulfield said that they are “…developing a 22nm process in Malta for manufacturing in Dresden. The goal is 14nm FinFET performance at 28nm costs.”
At DAC 52, GF’s Tim Dry gave what was reported to be a very well-attended presentation at the Synopsys booth. You don’t see the GF logo on the slides yet – but the source looks pretty clear….
His presentation was entitled Driving Innovation to Enable IoT Growth. Here’s a few snapshots of slides he showed.
Consider a ubiquitous security camera – a prime IoT sort of app. Here’s what FD-SOI does for it:
And then there’s the Smart Watch. 28nm FD-SOI with Forward Body Bias gives you great performance and over a week more of battery life than FinFET. Yes, please!
Next he looks at various applications, and the process technology needed to meet their power and performance requirements. As seen below, 55/40/28ULP and 28SLP each cover a limited segment of the range:
To cover the full range of requirements from low static power with RF to high performance active power, as seen below, you need 28FDSOI:
Recapping the presentation title, we see FD-SOI is the IoT growth enabler, as shown below:
Clearly GF’s rolling with this. So will you be at their FDSOI webinar on June 24? Of course you will. See you there!
Is FD-SOI a better choice than FinFETs for my chip? In some high-profile forums, designers are now asking that question. And the result is coming back: almost certainly.
Is there a place for FinFETs? Of course there is. If it’s a really big digital chip – no significant analog integration, where leakage not your biggest concern because what you’re really after is the ultimate in performance, when you’ve got a mega-budget and you’re going to run in extremely high volume, absolutely, you can make a strong business case for bulk FinFETs.
But is that really where most designs are?
If you need high-performance but you have to consider leakage (think battery life), if you’ve got to integrate the real world (aka analog – think IoT), if your chip is not a monster in size and will run in high volume but you don’t have an unlimited budget, you should be looking hard at FD-SOI. That’s what the experts at the recent EDPS conference in Monterey, CA said, that’s what they’re starting to tell the press, and that’s what they’re saying here on ASN.
Combined with the pretty dazzling results of the first 28nm FD-SOI silicon from cryptocurrency chipmaker SFARDS (read about it here) and the promise of very-high volume FD-SOI chips hitting the shelves in 2016, it’s a whole new ballgame.
Richard Goering over at the Cadence and Herb Reiter writing for 3DInCites wrote excellent blogs covering the EDPS conference in Monterey, CA a few weeks ago. EDPS – for Electronic Design Process Symposium – is a small but influential conference for the EDA community. Session 1 was entitled “FinFET vs. FD-SOI – which is the Right One for Your Design?”, and it lasted the entire morning.
The session kicked off with a presentation by Tom Dillinger, CAD Technology Manager at Oracle. Richard covered this in-depth in Part 1 of his two-part write-up (read the whole thing here). Tom gave an overview of the two technologies, putting a big emphasis on the importance or working closely with your foundry whichever way you go.
And then came the panel discussion with questions from the audience, which Herb in his write-up (read it here) described as “heated”. Acknowledging that FinFET has the stronger eco-system, Herb noted that, “…when using FinFETs, designers complain about the modeling- and design complexities of fins, the need for double pattering (coloring), the higher mask cost and added variability the extra masking step introduces. If 10nm FinFETs will demand triple or even quadruple patterning, they may face a significant disadvantage, compared to the 14nm FD-SOI technology, currently in development.”
In Part 2 of his coverage (read it here), Richard highlighted some of the big questions put to the panelists:
The two foundry guys were very much of the opinion that FinFET and FD-SOI can and will co-exist. Jamie Schaeffer’s comment, as noted by Richard, really sums it up nicely: “For some applications that have a large die with a large amount of digital integration, and require the ultimate in performance, FinFET is absolutely the right solution. For other applications that are in more cost-sensitive markets, and that have a smaller die and more analog integration, FD-SOI is the right solution.”
There you have it!
Shaeffer was also very bullish on next-gen FD-SOI, noting that performance will climb by 40% with half as many immersion lithography layers as FinFETs. He also said that next-gen FD-SOI is 30% faster than 20nm HK/MG.
Marco Brambilla noted that for Synapse, the FD-SOI choice was all about leakage, especially in IoT products where you need a burst of activity and then absolute quiet in sleep mode. (They’re working on a 28nm FD-SOI chip that will go into very high-volume production in early 2016, Synapse Design recently told ASN – read about that here).
Boris Murmann said that extrinsic capacitance in FinFETS is “a mess”, which is “a nightmare” for the analog guys. “ It’s a beautiful transistor [FinFET] but I can’t use it.” Yes, Richard reported, that’s what the man said.
So indeed, there is a choice. And with FD-SOI, the experts are seeing that it’s a real one.
Name a top Silicon Valley company, and you’ll probably find it on the attendance list of the upcoming FD-SOI & RF-SOI Forum in San Francisco. At the time of this posting, people from over 65 companies are among the hundreds who’ve signed up for this free, all-day event.
If you haven’t yet, you can still sign up at the SOI Consortium Website – just click here to go there. This event’s being sponsored by ARM, GlobalFoundries, ST, Synopsys, SunEdison, SEH and Soitec. Cadence, Ciena, GlobalFoundries, IBM, IMEC, Samsung, STMicroelectronics, Synopsys and VeriSilicon will present compelling solutions about FD-SOI and RF-SOI technologies, including competitive comparisons and product results.
Here’s a preview of the day. The morning’s devoted to FD-SOI, and the afternoon’s all about RF-SOI. Plus, there’s a (yes, free!) lunch, and a chance to network during the coffee breaks and over wine & cheese at the end of the day.
FD-SOI foundry offer
FD-SOI IP offer
FD-SOI design experience
Advantages and opportunities when designing with FD-SOI — Moderator: Dan Nenni, SemiWiki
If you’re in San Francisco for ISSCC (22-26 February), the FD-SOI/RF-SOI is a seven-minute walk up the street the next day. But if you can’t get to SF, don’t worry – you’ll get summaries of all the talks here at ASN. Access to the complete presentations will be freely available on the SOI Consortium website a few days later.
This workshop is part of a continuing series organized by the SOI Consortium. If you missed the recent ASN coverage of the event in Shanghai this fall, you can read about the FD-SOI part here, and the RF-SOI part here. For coverage of the Tokyo event in December, click here to read about the big Sony FD-SOI presentation and EDA/IP presentations and more here, and the Samsung, ST and other presentations here. You can also download most any of the presentations from all of the workshops that have been held over the last five years here.
For the SF event – here’s the key information:
FD-SOI and RF-SOI Forum