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Download the presentations of the October 21, 2009 conference.

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#14 - Winter 2009/10

The SOI Design Experience

• Special supplement: SOI Industry Consortium

• ARM11, Cadence, Freescale, Voldman/ESD and more

• Toshiba's Cell Regza TV

» read the full edition

Ritsumeikan University STMicroelectronics Berkeley, University of California Chartered Semiconductor Manufacturing Varian Infotech Freescale Semiconductor Applied Materials IMEC Cadence Design Systems

ARM Université Catholique de Louvain CEA-Leti Samsung Stanford University IBM Mentor Graphics Lam Research Synopsys Soitec

Semico KLA-Tencor Corporation Shin-Etsu Handotai GLOBALFOUNDRIES UMC AMD Kanazawa Institute of technology NVIDIA Magma Design Automation Tyndall National Institute

Innovative Silicon Synopsys Tyndall National Institute Berkeley, University of California NVIDIA Applied Materials UMC AMD IBM Varian

3D integration

Jan. 18, 2010Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout Circuits
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-μm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
[Lincoln Laboratory, Massachusetts Institute of Technology]

Jan. 18, 2010A 4-Side Tileable Back Illuminated 3D-Integrated Mpixel CMOS Image Sensor
[MIT Lincoln Laboratory, Irvine Sensors, Forza Silicon]