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NVIDIA MIT Lincoln Laboratory GLOBALFOUNDRIES CEA-Leti Tyndall National Institute University of Southern California Soitec STMicroelectronics Varian Semico

Mentor Graphics Berkeley, University of California Freescale Semiconductor IBM Samsung Universitι Catholique de Louvain BroadPak Ritsumeikan University Cadence Design Systems IMEC

Infotech UMC KLA-Tencor Corporation Synopsys ARM Kanazawa Institute of technology MEMC Shin-Etsu Handotai Stanford University BroadPak

3D integration

May. 31, 2010Fraunhofer IZM-ASSID selects EV Group Temporary Bonding and Debonding Equipment for Devoloping Processes for High-Volume Manufacturing of 3D ICS
EVG Systems Selected for Platform Flexibility, Functionality and Industry-Proven Reliability
[EV Group (EVG)]

Jan. 18, 2010A 4-Side Tileable Back Illuminated 3D-Integrated Mpixel CMOS Image Sensor
[MIT Lincoln Laboratory, Irvine Sensors, Forza Silicon]

Jan. 18, 2010Wafer-Scale 3D Integration of InGaAs Image Sensors with Si Readout Circuits
In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 x 1024 diode array with 8-μm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.
[Lincoln Laboratory, Massachusetts Institute of Technology]