Category Archive Industry Buzz

ByAdele Hars

SOI Consortium & Ecosystem Shines at SOI Academy (Shanghai) & WCS (Nanjing)

The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai.

Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums.

Presenting at WCS ’19 in Nanjing (clockwise from top left): Wayne Dai, CEO/Founder, VeriSilicon; Carlos Mazure, Executive Director, SOI Consortium; Giorgio Cesana, Director, STMicroelectronics; Christophe Tretz, Design Expert, SOI Consortium.
(Photos courtesy: WCS)

The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website — click here to get them.

Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.

Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes.

Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.

Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips.

SOI Academy, Shanghai, 2019, FD-SOI Training Day attendees.
(Photo credit: SIMIT)

The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF.

All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.

ByAdele Hars

SOI Consortium at Key China Events in May: World Semiconductor Congress (Nanjing) and SOI Academy/FD-SOI Training (Shanghai)

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)

QR code for WCS, Nanjing ’19

At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.

Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.

QR code for SOI Academy and FD-SOI Training, Shanghaid 2019

The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.

We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.

ByAdele Hars

SOI Consortium & Members at Samsung Foundry Forum (14 May, Santa Clara, CA)

For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you’ll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem.

There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners.

SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.

Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.

ByAdele Hars

PCM/MRAM Workshop by Leti and Applied Materials During 2019 IEEE Intl. Memory Workshop

Two of the big, recent breakthroughs in memory technology – eMRAM and ePCM – have gotten their start in volume manufacturing on 28nm FD-SOI. In conjunction with the 2019 IEEE International Memory Workshop, SOI Consortium members Leti and Applied Materials have teamed up to give a technical program to explore short-term and long-term memory solutions. While the workshop is not specific to SOI, given the recent foundry announcements about ePCM and eMRAM for FD-SOI, the organizers predict it will be of particular interest to those following the greater SOI ecosystem. The event takes place at the end of the Sunday IMW tutorial day, starting at 5:30pm at the Hyatt Regency in Monterey, CA. Please see this page for the program and registration information.

Here is the program:

  • Emerging Non-Volatile Memory Promises Toward New Energy-Efficient Design and Applications – Michael Tchagaspanian, VP Business Development, CEA-Leti
  • Technologies That Enable MRAM and PCRAM in Volume Manufacturing – Kevin Moraes, Vice President, Metal Deposition Products, Applied Materials
  • Technology Improvements Directions of Emerging Non-Volatile Memory for New Applications Solutions – Etienne Nowak, Head of Memory Laboratory, CEA-Leti
  • Integration Schemes and Challenges for New Memories in a New Artificial Intelligence Era –Michel Frei, Director, Advanced Product & Technology Development, Applied Materials

Jean-Eric Michallet, Head of Leti’s Microelectronics Components Department, Silicon Component Division is one of the organizers. Here is his overview:

FD-SOI is expected to be a long-lived technology. It enables planar CMOS scaling and accommodates a great deal of More-than-Moore developments where its ability for low power and great analog performance can make a difference for IoT, Automotive, Machine Learning or 5G applications. But to do this it requires a high-performance and cost-effective non-volatile embedded memory option. The incumbent Flash cell is reaching the end of its roadmap due to the difficulty of shrinking the bitcell and manufacturing, as well as the finished wafer cost increase. Back-end integrated Random Access Memory in advanced CMOS process has been explored for many years now as a competitive solution for fast-write and low-voltage non-volatile embedded memories. Foundry availability of embedded Magnetic RAM and Phase Change RAM for FDSOI 28nm platforms has been announced recently, showing that these technologies have now reached industrial maturity. CEA-Leti and Applied Materials invite you to attend a technical program to explore short-term and long-term memory solutions, from early research to industrialization.

Registration is open, free, and available to all IMW attendees, and others. However, as seating is limited and as we have already several participants pre-registered, registration is by invitation only and early registration is recommended. If you are interested, please email Jean-Eric Michallet.

The event is presented in conjunction with the 2019 IEEE International Memory Workshop, to be held on Sunday, May 12th, 2019, Hyatt Regency, Monterey CA, starting at 5:30 pm.

ByAdele Hars

FD-SOI for RF & mmWave: Free Workshop, 4 April ’19, Grenoble

FD-SOI for RF and mmWave communications is a hot topic. In high-data rate communications like RF and millimeter-wave devices in particular, FD-SOI delivers high-performance with numerous unique advantages, making it most likely the fastest RF-CMOS technology on the market.

If you’d like to take a deep dive and learn more about it, Soitec and Incize are sponsoring a free, full-day workshop in Grenoble on April 4th, 2019. Click here for registration information. The workshop follows the day after the IEEE/EDS EuroSOI-ULIS conference there (you can read about the full conference in a previous ASN post).

This technical workshop will cover the FD-SOI technology platform with a focus on its compatibility with RF & mmWave communications. Attendees will hear from notable FD-SOI leaders and experts from leading industry and research institutions presenting updates on key developments and building blocks across the semiconductor value chain. Topics will include circuit design, device fundamentals, simulation and characterization of RF devices, test, CMOS technology and substrate technologies enabling FD-SOI. In addition, the workshop will include an overview about how FD-SOI technology is benefiting current and future end user applications.

Here’s the agenda:

FD-SOI technology platform: new standards for emerging consumer electronics [Click to enlarge.]

 

ByAdele Hars

GF-Dolphin 22FDX Turnkey Adaptive Body Bias Solutions Offer Big Energy Savings, Faster TTM. Design Kits Q2/19.

GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019.

As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone.

The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs.

“We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.”

“In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.”

As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of.

~ ~ ~

*A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago:

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering’s Ann Steffora Mutschler from a couple years ago.

ByAdele Hars

World 1st and It’s on 28nm FD-SOI: ST Sampling ePCM (eNVM) for Automotive MCUs

STMicroelectronics is now sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on ePCM to alpha customers. Field trials meeting the requirements of automotive applications and full technology qualification are expected in 2020. These MCUs—the world’s first to use ePCM, which stands for embedded Phase-Change Memory—will target powertrain systems, advanced and secure gateways, safety/ADAS applications, and Vehicle Electrification. (Read the full press release here.)

A cross section of the embedded-PCM bitcell integrated in the 28nm FD-SOI technology shows the heater that quickly flips storage cells between crystalline and amorphous states. (Courtesy: STMicroelectronics)

“Having applied ST’s process, design, technology, and application expertise to ePCM, we’ve developed an innovative recipe that makes ST the very first to combine this non-volatile memory with 28nm FD-SOI for high-performance, low-power automotive microcontrollers,” said Marco Monti, President Automotive and Discrete Group, STMicroelectronics. “With samples already in some lead-customers’ hands, we’re confirming the outstanding temperature performance of ePCM and its ability to meet all automotive standards, further assuring our confidence in its market adoption and success.”

ePCM presents a solution to chip- and system-level challenges, meeting automotive MCU requirements for AEC-Q100 Grade 0, operating at temperature up to +165°C. In addition, ST says its technology assures firmware/data retention through high-temperature soldering reflow processes and immunity to radiation, for additional data safety.

Architecture and performance benchmark updates were presented the most recent IEDM (December 2018 in San Francisco) in a paper entitled Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory (F. Arnaud et al). As of this writing, the IEDM 2018 papers are not yet posted on the IEEE Xplore Digital Library site. However, the ppt that ST presented at the conference is available here.

For more in-depth information on ePCM, see the ST PCM page. To learn more about how it compares with competing technologies such as eMRAM, read Embedded Phase-Change Memory Emerges by Mark Lapedus of SemiEngineering. Papers describing other eNVM solutions on FD-SOI were also presented at IEDM 2018. Samsung’s is entitled Demonstration of Highly Manufacturable STT-MRAM Embedded in 28nm Logic (Y. J. Song et al). GlobalFoundries’ is entitled 22-nm FD-SOI Embedded MRAM Technology for Low-Power Automotive-Grade-1 MCU Applications (K. Lee et al).

ByAdele Hars

India & Industry 1st Next Gen TV SoCs on Samsung 28nm FD-SOI (Demo at CES ’19)

Going to CES? Check out the demo by Saankhya Labs. They just announced the launch of their latest next-gen digital terrestrial TV demodulator chipsets, SL3000 and SL4000. As reported by The Times of India and many other media outlets, the chipset is part of the Pruthvi-3 series, and it’s being manufactured on Samsung Foundry’s 28nm FD-SOI technology. Saankhya Labs says they’ll be sampling in the 1st Quarter of 2019.

[UPDATE 9 January 2019: Per a press release issued at CES, the chipset was launched by ONE Media 3.0, LLC, a subsidiary of Sinclair Broadcast Group,  and Saankhya Labs in collaboration with VeriSilicon and Samsung Foundry.  This announcement follows Sinclair Broadcast Group’s recent commitment to a nationwide roll-out of ATSC 3.0 (“Next Gen TV“) service and its past announcement to fund millions of chipsets giveaways for wireless operators. Sinclair is a major TV station operator in the US.

The PR goes on to say that the demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option.] 

(Courtesy: @SaankhyaLabs)

The Pruthvi-3 is an upgrade of Saankyha’s Software Defined Radio (SDR) chipsets for Direct to Mobile (DTM) applications, which address video bandwidth congestion and other challenges, including internet access for the vast populations of rural users found in India and worldwide. (DYK half the world still lacks access!?)

The company says the SL300x will be the industry’s first SDR-based DTV Demodulator that supports all the leading broadcast terrestrial, cable and satellite TV standards including the ATSC 3.0. The SOC is designed to deliver high performance and high throughput in static and multipath environments. A power-efficient, small footprint device, it targets DTV receiver applications such as digital televisions, set top boxes, home theatres and automotive entertainment systems. The SL400x – for mobile phones and tablets – is designed to be the most technologically advanced and highly-integrated single chip Mobile DTV Receiver in the industry. The full featured front-end SOC integrates UHF RF tuner, baseband DTV demodulator, FEC decoder, de-interleaver memory and Analog to Digital Converter (ADC) in a single chip.

Here is a brief YouTube video of the company’s CEO at the launch event, explaining why they see this chipset as a game changer.

India Times reports that there are already 5 million of the chipsets in pre-order to companies in the US and China.

ByAdele Hars

EuroSOI-ULIS (April 2019, Grenoble) + Free FD-SOI RF Technology Workshop for 5G

If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.

The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.

One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.

This year, papers in the following areas have been solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.

Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.

EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.

And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).

Grenoble the first week of April 2019 is clearly the place to be.

ByAdele Hars

New Bluetooth 5 RF IP from VeriSilicon Targets Wearables, IoT on GF’s 22FDX

Since about a third of all IoT devices are expected to be connected by Bluetooth, chip designers need IP solutions that will help reduce system cost and greatly improve battery life. And that’s just what VeriSilicon has announced for GlobalFoundries’ 22FDX® (FD-SOI) process.

“By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs,” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. 22FDX enables efficient single-chip integration of RF, transceiver, baseband, processor, and power management components. GF and VeriSilicon are working on an SoC using VeriSilicon’s BLE 5.0 RF IP in GF’s 22FDX process.

The latest iteration of Bluetooth is 5, which (like its predecessor 4) has a Low Energy (LE) RF option – but with big improvements. According to the Bluetooth website, “With 4x range, 2x speed and 8x broadcasting message capacity, the enhancements of Bluetooth 5 focus on increasing the functionality of Bluetooth for the IoT.” BLE 5.0 was designed for very low power operation and is optimized for the sorts of short burst data transmissions you’ll get with IoT.

On the strength of VeriSilicon’s innovative RF architecture and by leveraging GF’s 22FDX technology, VeriSilicon says the new IP product achieves significant improvements in power, area, and cost compared to current offerings, so it will better serve the emerging and increasing wearable devices and IoT applications space.

“VeriSilicon’s BLE IP complements GF’s 22FDX FD-SOI capabilities and is well positioned to support the explosive growth of low-power IoT and connected devices,” said Mark Ireland, vice president of ecosystem partnerships at GF. “Together, we broaden our IP and services to further enable our mutual clients to provide power and cost efficient solutions.”

VeriSilicon BLE 5.0 RF IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management.

You can read the full press release in Chinese here and in English here.