Category Archive ASN #14

Digital implementation with SOI: go with the float

Off-the-shelf solutions eliminate SOI design-time overhead.

Since the drive began to make SOI a more mainstream manufacturing process there has been concern over the cost. These considerations have overshadowed the benefits that the floating body of the SOI process brings, which includes better chip performance per watt, smaller die size, and better scalability at smaller geometries.

The concerns raised were not only regarding the cost of the manufacturing process itself — because any advance comes at a price — but also with the cost of actually implementing cell-based digital designs. The biggest concern: it would take many more man-hours of engineering time to make it through the digital design process as compared to bulk CMOS. Read More

Multicore’s perfect balance

Freescale’s highly successful QorIQ™ line of communications processors leverages 45nm SOI for power & performance at the right price.

Last year, Freescale launched a new line of communications platforms on 45nm SOI under the QorIQ™ (pronounced “Core IQ”) brand name. As the industry leader, Freescale has shipped 250 million communications processors over the years. With QorIQ, Freescale is carrying forward proven IP from its industry-leading PowerQUICC family, as well as building new innovations into the QorIQ platforms.

Read More

Implementing the 45nm SOI ARM11

The mobile app chip’s 40% power saving was achieved without any major rework in design methodology.

At the IEEE SOI Conference, ARM announced the results from a 45nm SOI test chip. The test chip was based on an ARM 1176™ processor and enables a direct comparison between SOI and bulk microprocessor implementations.

The goal was to demonstrate the power savings in a real silicon implementation with a well-known, industry-standard core, in an apples-to-apples comparison of 45nm SOI high-performance technology with bulk CMOS 45nm low-power (LP) technology. Read More

Green success

The SOI: Simply Greener campaign launched this past summer was great success, generating a high level of interest.

The press gave it extensive coverage, with follow-up articles and interviews, including two video interviews that are available on the consortium website.

This effort accomplished two important objectives. First, it drove home the message that SOI delivers lower power. Secondly, it was a timely, socially responsible message on behalf of our industry. This message continues to gained traction. The SOI: Simply Greener logo is freely available on the website. Members and supporters are encouraged to download it for continued use in their own presentations.

Design clinic

The SOI Consortium recently sponsored another very successful SOI Design Clinic. Co-located with ARM’s October TechCon3 developer conference in San Jose, this clinic followed ARM’s announcement of achieving 40% power savings by porting the ARM 1176 core to SOI (see ARM’s article in this edition of ASN). The full day of talks included:

Horacio Mendez, Executive Director of the SOI Industry Consortium, gave the opening talk.

  • SOI Fundamentals by Bob Ulicki, SOI Industry Consortium,
  • Designing Low Power Circuits on SOI by Olivier Thomas, CEA-Leti,
  • Designing High Performance Microprocessors on SOI by Nghia Phan, IBM,
  • Design Tools, Flows and Methodologies for SOI: Digital, Mixed-Signal SoC and RF by Jim McMahon, Trisha Kristof and Michael Jacobs, Cadence. Read More

IMEC hosts FD-SOI for low power workshop

There was an excellent turnout at an all-day workshop on FD SOI for low-power applications, co-sponsored by IMEC and the SOI Industry Consortium. Held at the IMEC campus in Leuven, Belgium this past October, “FD SOI architecture, technology platform for low power applications for 22nm and beyond” featured speakers from IMEC, IBM, Hitachi, Soitec, UC Berkeley, ISi, CEA-Leti, ARM, Cadence, Synopsys and the SOI Industry Consortium. Read More

FD-SOI & low power workshop after the IEDM conference

The SOI Industry Consortium, CEA-Leti and Soitec are organizing an evening workshop entitled FD-SOI Readiness at the Hilton Baltimore on Wednesday the 9th of December 2009. The workshop is by invitation, particularly targeting IC makers, foundries, TCAD companies and IP houses. Complementing the technical papers and short courses presented during the IEDM conference, the workshop will be devoted to SRAM scaling, design porting from bulk to FD-SOI, BSIM models, the results of porting an ARM core to SOI, and TCAD with an outlook towards the specificities for FD-SOI. It provides a comprehensive review of the current state of technology presented by renowned experts in the field, and includes plenty of time for discussion and exchanges.

See the Consortium website for details

Reports & Papers

Floating Body Effects: Just the Facts

For designers who’ve never worked in SOI, rumors surrounding the “floating body effect” might make SOI  seem like too much of a challenge. A paper freely available on the SOI Industry Consortium website entitled “De-myth-tifying” the SOI Floating Body Effect by Bob Ulicki and Herb Reiter puts an end to any lingering misconceptions. Read More


  • Modeling and direct extraction of band offset induced by stress engineering in silicon-on-insulator metal-oxide-semiconductor field effect transistors: Implications for device reliability
    X. Garros, et al.  (Leti, Soitec) J. Appl. Phys. 105, 114508 (2009).
  • Elastic relaxation in patterned and implanted strained silicon on insulator
    S. Baudot, et al.  (CEA-CNRS, Leti) J. Appl. Phys. 105, 114302 (2009)
  • Development of analytical model for strained silicon relaxation on (100) fully relaxed Si0.8Ge0.2 pseudo-substrates
    C. Figuet and O. Kononchuk. (Soitec) Thin Solid Films. 13 October 2009.

Frontiers in Optics (FiO)

11-15 October 2009 – San Jose, CA, USA

  • Low Insertion Loss SOI Microring Resonator Integrated with Nano-Taper Couplers
    M.Pu, et al. (TU Denmark, Koheras A/S)