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2019 Greetings for the Start of an Exciting Year in SOI

Welcome to our first post for 2019 here at the SOI Consortium’s Advanced Substrate News. First and foremost, may we wish you and yours a safe, happy, healthy and prosperous year.

It should be a good year across the SOI ecosystem, with new products, players, IP, technologies and tools — and high volumes.

What’s new? Let’s start with the people, as the Consortium welcomes new team members. Jon Cheek of NXP will join Carlos Mazure as Executive Co-Director. He’ll be replacing ST’s Giorgio Cesana in that role – and goodness knows those are some big shoes to fill. Giorgio has given of his time and expertise so tirelessly over many years. He’ll of course still be a key resource for the SOI ecosystem, and though we’ll miss him here at the Consortium, we know he’ll be doing great things in SOI at ST. So a heartfelt thanks to Giorgio Cesana from all of us.

Jon Cheek has a long history in engineering management at companies that have been leading users of SOI: AMD, Freescale and now NXP. As such, he understands what companies need to design great products, and how the Consortium can help further build, promote, connect and support the ecosystem. The Consortium team also welcomes Jean-Eric Michallet of Leti, who’ll bring deep bizdev expertise and a keen sense of what it takes to reach further into the ecosystem. (Astute long-time ASN readers might remember his post from five years ago about 3D monolithic integration – now dubbed “Cool Cube” by Leti.) And finally, look to hear more from and about the Consortium, as our team is rounded out with the addition of the comm & marketing savvy of Erin Berard of Soitec.

In addition to new team members, the Consortium is very pleased to welcome new member Applied Materials. Though new to the Consortium, AMAT has a long history in the heart of SOI ecosystem – in fact they’ve been working with SOI wafer-leader Soitec for over 25 years. AMAT ion implanters are a key enabler to what became and is Soitec’s industry-leading Smart CutTM SOI wafer manufacturing process. And of course AMAT equipment is used to make virtually every chip in the world, so their breadth of vision as a consortium member is clearly a fabulous addition.

2019 will also be marked by the expansion of the highly successful SOI Academy series, the first of which was held this past fall in Shanghai. We’ll keep you posted as these and other Consortium events are announced throughout the year. In fact, 2019 marks a decade of (excellent!) SOI Consortium events events around the world: our first symposium was held back in 2009. Kicking off this year, save April 9th on your calendar for our Annual SOI Silicon Valley Symposium. Then watch this page for more events across the globe.

What will the year bring? On the product side, RF-SOI for 5G is of course super hot. Last summer, a SemiconductorEngineering headline proclaimed RF-SOI Wars Begin. And what we heard at the International RF-SOI Workshop last fall in Shanghai (presentations here) certainly confirmed that in the coming year the race will continue unabated.

Part 3 in SemiconductorEngineering’s “Experts at the Table” series on FD-SOI featured James Lamb of Brewer Science, Giorgio Cesana of ST, Olivier Vatel of Screen, and Carlos Mazure of Soitec. (Image courtesy: SemiconductorEngineering.com)

And for FD-SOI, you might want to read the SE series published over the last six months. The latest, published a couple of weeks ago looks at FD-SOI at the Edge. There are some great insights from SOI Consortium members there. In terms of products, too, there’s lots of activity.

Last summer, Samsung indicated they’d taped out over 60 products since they first began offering 28FDS three years ago. It’s a trend they see accelerating.  Full production of 18FDS is slated for this fall.

And also last summer GlobalFoundries indicated they had over 50 client designs on 22FDX. “We’re only just beginning,” said GF CEO Tom Caulfield at the time. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. ”

For its part, ST, as we learned at the last SOI Consortium Japan Workshop, has been doing FD-SOI for five years now. And while we don’t have number, we learned that some of those products are now in their second and third generations, and that some big FD-SOI chips coming out this year with embedded memory and RF, with especially good traction in mmWave, automotive and IoT.

So while the outlook for the overall industry is anyone’s guess for the coming year, the outlook for chips built on SOI technologies is very good indeed.

India & Industry 1st Next Gen TV SoCs on Samsung 28nm FD-SOI (Demo at CES ’19)

Going to CES? Check out the demo by Saankhya Labs. They just announced the launch of their latest next-gen digital terrestrial TV demodulator chipsets, SL3000 and SL4000. As reported by The Times of India and many other media outlets, the chipset is part of the Pruthvi-3 series, and it’s being manufactured on Samsung Foundry’s 28nm FD-SOI technology. Saankhya Labs says they’ll be sampling in the 1st Quarter of 2019.

[UPDATE 9 January 2019: Per a press release issued at CES, the chipset was launched by ONE Media 3.0, LLC, a subsidiary of Sinclair Broadcast Group,  and Saankhya Labs in collaboration with VeriSilicon and Samsung Foundry.  This announcement follows Sinclair Broadcast Group’s recent commitment to a nationwide roll-out of ATSC 3.0 (“Next Gen TV“) service and its past announcement to fund millions of chipsets giveaways for wireless operators. Sinclair is a major TV station operator in the US.

The PR goes on to say that the demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option.] 

(Courtesy: @SaankhyaLabs)

The Pruthvi-3 is an upgrade of Saankyha’s Software Defined Radio (SDR) chipsets for Direct to Mobile (DTM) applications, which address video bandwidth congestion and other challenges, including internet access for the vast populations of rural users found in India and worldwide. (DYK half the world still lacks access!?)

The company says the SL300x will be the industry’s first SDR-based DTV Demodulator that supports all the leading broadcast terrestrial, cable and satellite TV standards including the ATSC 3.0. The SOC is designed to deliver high performance and high throughput in static and multipath environments. A power-efficient, small footprint device, it targets DTV receiver applications such as digital televisions, set top boxes, home theatres and automotive entertainment systems. The SL400x – for mobile phones and tablets – is designed to be the most technologically advanced and highly-integrated single chip Mobile DTV Receiver in the industry. The full featured front-end SOC integrates UHF RF tuner, baseband DTV demodulator, FEC decoder, de-interleaver memory and Analog to Digital Converter (ADC) in a single chip.

Here is a brief YouTube video of the company’s CEO at the launch event, explaining why they see this chipset as a game changer.

India Times reports that there are already 5 million of the chipsets in pre-order to companies in the US and China.

FD-SOI Training: Over 220 Attend 1st SOI Academy in Shanghai

There were over 220 participants at the recent SOI Academy FD-SOI Training event organized in Shanghai. The event extended over two days, with the first day covering a basic introduction to the technology as well as the ecosystem worldwide and in China. The second day was hands-on professional training. Attendees got a comprehensive understanding of how to leverage the benefits and flexibility of FD-SOI design techniques for low-power chips including logic, mixed-signal/RF and analog blocks.

They had a great line-up of experts from whom to learn – check out the agenda here. There was also a follow-up press release (in Chinese) from SITRI here. There will be more of these SOI Academy events in cities across China in the year to come – we’ll keep you posted (and of course, keep checking back for news on the Consortium’s Events page).

SOI Academy ’18 keynotes by: Dr. Mark Ding, CEO, SITRI; Dr. Carlos Mazure, EVP Soitec and Chairman/Executive Director SOI Consortium. Dr. Julien Arcamone, EVP Leti. (Images courtesy: SITRI). Lower right: the hands-on FD-SOI training.

The two-day seminar and hands-on FD-SOI design training was (superbly!) co-organized by SITRI and Leti, with the support of the SOI Industry Consortium at the Jiading SIMIT campus outside of Shanghai.

Just to put this in perspective, SIMIT and SITRI are absolutely key players in China’s chip ecosystem. SIMIT is the Shanghai Institute of Microsystem and Information Technology, one of the most venerable institutes in the Chinese Academy of Science (CAS) and one of the world’s earliest pioneers in SOI. SITRI is the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating innovation and commercialization of More-than-Moore for IoT. Both institutions are under the aegis of Dr. Xi Wang, Chairman of SITRI, Director General of SIMIT, Academician of CAS, and champion of all things SOI in China.

At this Shanghai event, the participants came from industry (including big companies, SMEs and startups) and technical institutions. In fact as well as attendees from Shanghai people voyaged from other cities such as Shenzhen and Chengdu.

The designers participating to the FD-SOI training day were all experienced in design and highly motivated in learning FD-SOI design, notes Carlos Mazure, Chairman & Executive Director of the SOI Industry Consortium, and Executive VP of Soitec. “This made it possible to dive into the specificities of FD-SOI,” he said, adding that, “The focus on RF was very timely.”

Day 1: Intro to FD-SOI

The first afternoon opening keynotes were made by SITRI CEO Dr. Mark Ding and Leti EVP Dr. Julien Arcamone. These were followed by overview talks by execs from Soitec, Verisilicon and GlobalFoundries.

After a lively networking break, three talks delved into FD-SOI technology. The first was by Professor Sorin Cristoloveanu, Laureate of the IEEE Andrew Grove Award and Director at the CNRS (the French National Center for Scientific Research – the largest governmental research organization in France and the largest fundamental science agency in Europe). He covered device physics and characterization techniques. This was followed by talks on the technology by Soitec Fellow Bich-Yen Nguygen, and by Dr. Christophe Tretz, IBM Sr. Engineer on product design methodology.

The day ended with a dinner, where Professor Cristoloveanu says enthusiastic technical discussions continued unabated (and continued even further in follow-up emails), lots of business cards were exchanged, and opportunities for further education were explored.

Day 2: Hands-on Training

The second day, designers got hands-on training from Leti experts using FD-SOI PDKs, first in the morning on digital, then in the afternoon on RF. Everyone loved the lively discussion and in-depth exchanges between the experts and the designers. They agreed that FD-SOI has important applications and differentiated competitive advantages for IoT, 5G, automotive, AI and other fields. At the end of the training, Leti and SITRI jointly issued SOI Academy certificates of completion to the designers.

Feedback from participants was very good. Some asked for further education and for hands-on testimonials from companies that are already designing and manufacturing products on FD-SOI.

“The participants were focused, motivated, involved, with good knowledge, which helped make the three hours of Digital training effective,” said Dr. Alexandre Valentian, Leti Sr. Expert, Digital Design. “The IT team was very helpful in setting up the training, the students accounts and the hardware infrastructure.”

“The training on Basics of FD-SOI RF circuit was a great success thanks to the efficiency of our Chinese partners and also thanks to the enthusiasm and the good level of our trainees. As senior Expert of CEA Leti I was really impressed by the professionalism of the organization team. For all these reasons, I’m very glad to have had the opportunity to contribute to the 2018 SOI Academy,” said Dr. Baudouin Martineau, Leti Sr. Expert, RFIC Design & Technologies.

“The professionalism, efficiency and enthusiasm of our Chinese partners and the level and technical relevance of all trainees made the training on Basics of FD-SOI RF circuit a great success and fruitful experience,” added Frédéric Hameau, Sr. RF Research Engineer, Leti Project Leader, Architecture, IC Design & Embedded Software Division, RF Architectures and ICs Laboratory. “It was a pleasure to get the opportunity to be part of this first edition of SOI academy 2018.”

The organizers would like to thank the sponsors, including: the SOI Consortium and its members Soitec, VeriSilicon, GlobalFoundries, Simgui and Cadence, as well as Mentor, ProPlus and other companies and institutions in China and worldwide. Dr. Mazure notes that special recognition must go to Dr. Julien Arcamone, EVP, Leti-CEA and to Qing Wang-Bousquet, SITRI representative, for the perfect and smooth organization, and to the Leti instructors, who are international experts and highly committed.

“As one of the main initiators and organizers of the 2018 SOI Academy, I wanted to personally thank all of you for your respective contribution to this first edition of the SOI Academy,” concludes Dr. Arcamone. “Undoubtedly, it was a great success, very well organized and fluid and we can be proud of that.”

EuroSOI-ULIS (April 2019, Grenoble) + Free FD-SOI RF Technology Workshop for 5G

If you’ve never been, you should put it on your list. EuroSOI is one of those seminal conferences where you get a front-row seat to emerging technologies. It provides an interactive forum for scientists and engineers working in the field of new materials and advanced nanoscale devices. In fact, some of the leading technologies enabled by SOI that are now in the mainstream got their start at this conference. Within a few years of being presented here, the best work continues to evolve and star in the “big” conferences like IEDM and VLSI.

The list of luminaries on the steering and technical committees is a veritable who’s who of the SOI research ecosystem, including two winners of the IEEE Andrew Grove Award: Technical Chair Jean-Pierre Colinge and Sorin Cristoloveanu. So, if you want to get in on the ground floor of next-gen SOI, or just get a look at the early stages of the pipeline, this is a great place to do it.

One of the key objectives is to promote collaboration and partnership between players in academia, research and industry. As such it provides opportunities for cross-fertilization across materials, devices and design. The networking is excellent, and the gala dinner is always an affair to remember.

This year, papers in the following areas have been solicited:

  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
  • Emerging memory devices.

Accepted papers appear in the conference proceedings in the IEEE Xplore® digital library. The authors of the best papers are invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SiNANO institute.

EuroSOI-ULIS kicks off a full week of activities in Grenoble. The day after the conference, Incize and Soitec are sponsoring an excellent, free workshop on FD-SOI RF technologies for 5G: materials, devices, circuits and performance. The’ve got a terrific line-up of presentations planned.

And towards the end of the week, there are other important satellite events. The 1st open IRDS International Roadmap for Devices and Systems European Conference (April 4th, 2019) is jointly organized by the USA, Japan and EU, and sponsored by the IEEE and SiNANO Institute. Then the week finishes out with the IEEE ICRC International Conference on Rebooting Computing (April 5th, 2019).

Grenoble the first week of April 2019 is clearly the place to be.

Now, We Ramp! Panelists at Japan Workshop See Good Opps for FD-SOI, RF-SOI

Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here).

The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS & sensors), and the SOI manufacturing ecosystem.

The 1st day panel discussion was so interesting we’ll give it a post of its own, then follow up with round-ups of the presentations from both days.

And now to ramp!

The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF’s CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019.

Panel on FD-SOI and RF-SOI end-user deployment, SOI Workshop Japan, 2018. Giorgio Cesana, SOI Consortium Executive Director, Moderator; John Carey, ST Director; Adam Lee, Samsung Director; Subramani Kengeri, GF CTO; Wayne Dai, VeriSilicon CEO; Mostafa Emam, Incize CEO. (Courtesy: SOI Consortium)

VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI.

ST Director John Carey noted that ST’s been using FD-SOI since 2014. They’ve fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they’ve got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT.

The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it’s in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded.

Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung’s Lee said they’ve already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST’s Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained.

With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing.

5G – What’s First?

The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung’s seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons.

Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that’s what tier-one players want.

Carey brought it back to RF-SOI (noting that ST’s introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won’t be the bottleneck he said, so what’s the FD-SOI/mmWave roadmap? Kengeri responded that GF’s ready. Lee said Samsung is also ready, and you’d see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it’s qualified. Carey said ST sees it first in consumer premises equipment that’s connected by satellite.

The right enabler

Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn’t give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it’s very important.

In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.

New Bluetooth 5 RF IP from VeriSilicon Targets Wearables, IoT on GF’s 22FDX

Since about a third of all IoT devices are expected to be connected by Bluetooth, chip designers need IP solutions that will help reduce system cost and greatly improve battery life. And that’s just what VeriSilicon has announced for GlobalFoundries’ 22FDX® (FD-SOI) process.

“By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs,” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. 22FDX enables efficient single-chip integration of RF, transceiver, baseband, processor, and power management components. GF and VeriSilicon are working on an SoC using VeriSilicon’s BLE 5.0 RF IP in GF’s 22FDX process.

The latest iteration of Bluetooth is 5, which (like its predecessor 4) has a Low Energy (LE) RF option – but with big improvements. According to the Bluetooth website, “With 4x range, 2x speed and 8x broadcasting message capacity, the enhancements of Bluetooth 5 focus on increasing the functionality of Bluetooth for the IoT.” BLE 5.0 was designed for very low power operation and is optimized for the sorts of short burst data transmissions you’ll get with IoT.

On the strength of VeriSilicon’s innovative RF architecture and by leveraging GF’s 22FDX technology, VeriSilicon says the new IP product achieves significant improvements in power, area, and cost compared to current offerings, so it will better serve the emerging and increasing wearable devices and IoT applications space.

“VeriSilicon’s BLE IP complements GF’s 22FDX FD-SOI capabilities and is well positioned to support the explosive growth of low-power IoT and connected devices,” said Mark Ireland, vice president of ecosystem partnerships at GF. “Together, we broaden our IP and services to further enable our mutual clients to provide power and cost efficient solutions.”

VeriSilicon BLE 5.0 RF IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management.

You can read the full press release in Chinese here and in English here.

QuickLogic ultra-low power eFPGA on GF’s 22FDX FD-SOI and in PULP/RISC-V SoC

(Courtesy: PRNewsfoto/QuickLogic Corporation)

Some great pieces of FD-SOI news from QuickLogic. The company recently demonstrated its ultra-low power ArcticPro™ embedded FPGA (eFPGA) solutions at the GlobalFoundries Technology Conferences in Santa Clara, California, Munich and Shanghai. The technology is available now.

ArcticPro is the industry’s first eFPGA offering for GF’s 22FDX® process (btw they’ve been shipping it in volume for GF’s 65nm and 40nm bulk processes for years). The company says its ultra-low power eFPGA architecture and mature software offer semiconductor and system companies the ability to integrate programmable hardware accelerators to lower power consumption and the flexibility to reconfigure a device’s functionality in the field.

(Image courtesy: QuickLogic)

QuickLogic has also announced that the technical university ETH Zurich  will integrate QuickLogic’s ArcticPro technology onto the university’s PULP platform. PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. ETH will become the first licensee of eFPGA technology from QuickLogic on GF’s 22FDX process node. They will develop an SoC integrating ETHZ’s open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption.

“The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications,” said QuickLogic CTO Dr. Timothy Saxe. “QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we’ve learned along with our eFPGA technology to this groundbreaking initiative in low power computing.”

ETH’s PULP platform with the fully integrated eFPGA is expected to be available Q1′ 2019.

QuickLogic is part of GF’s fast-growing FDXcelerator™ partner ecosystem, offering customers ultra-low power (eFPGA) Intellectual Property, complete software tools and a compiler.

1st Highlights from Shanghai FD-SOI/RF-SOI Events – Amazon/Blink, Intellifusion, Foundries, China Mobile, Nokia, Qorvo and More

Excellent news and exciting applications made headlines at the recent FD-SOI and RF-SOI events in Shanghai. During the FD-SOI day, Amazon/Blink and Intellifusion shared news about their new chips, and we got updates from GF and Samsung. The RF-SOI day featured a great talk with details about China Mobile’s 5G plans, and peeks at Nokia’s groundbreaking approach and Qorvo’s outlook.

(Photo courtesy: Verisilicon)

The hall was absolutely full – with over 300 people attending each day. The FD-SOI event was by invitation only, and there were far more people wanting to attend than there was room for, even given the big room in which the events were held.

The events got excellent coverage in the China tech press. For example, EEWorld started with an overview article and added five supporting pieces zooming in on key presentations and companies: one on GlobalFoundries, one on Samsung, one on Verisilicon, and two on Soitec (CEO and top exec interviews). These pieces are in Chinese, but just open the links through your favorite translation site. Many of the key slides are captured in these articles, so if you can’t wait for the ppts to be posted on the SOI Consortium website, you can get some quick previews now.

The Verisilicon PR folks also wrote up highlights of the FD-SOI event in real time with lots of great pictures – you can read that here. Many thanks to that team, too, for flagging the coverage in the China press and posting it on their WeChat account. On the RF-SOI side, the Simgui folks wrote that up – you can read it here. They also sponsored a gala dinner with awards given to Qorvo and SmarterMicro – you can read about that here.

Most of the presentations will be posted on the SOI Consortium website over the next few weeks, at which point we’ll cover them in-depth here at ASN. But for now, here’s a quick round-up of some of the highlights.

FD-SOI Highlights

(Courtesy: Blink, Verisilicon)

Boston-area based Blink, which makes very popular home security systems, was recently bought by Amazon (see their current product page here). They just taped out a new chip on Samsung’s 28FDS FD-SOI technology, and they’re really happy about it. “I believe for battery powered devices at home, FD-SOI is the way to go,” said Yantoa Jia, Head of ASIC & China Ops at Blink.

Their goal in the move from 55nm bulk to 28nm FD-SOI was to double battery life, add features and control costs: and they did it. Even adding two more CPU cores and lots more features, “The power drop is fantastic,” he said. Design was no problem, he continued, and there was plenty of IP. Once the new generation is officially announced, he promised to sit down with ASN and give us more details.

Attendees also heard about a new chipset from Intellifusion, which is putting its face recognition technology onto GlobalFoundries’ 22FDX FD-SOI with design house Verisilicon. CEO Nin Chen gave an impromptu talk about how their technology is used to find missing people and property. The new chip, which is especially designed for use in cities, is network-to-cloud leveraging AI.

For his part Thomas Morgenstern, GlobalFoundries SVP and GM of the Dresden Fab 1, said they’re seeing high yields and increasing capacity for 22FDX. The marketing and manufacturing ecosystem has been built around the fab in Europe. Now, he said, the key is to build an FD-SOI ecosystem in China. The market needs of China largely parallel those of Europe, he noted, for performance and efficiency at the right cost point. The ecosystem enables fast time-to-market and 1st-time-right.

(Photo courtesy: Cadence)

Samsung SVP Gitae Jeong sees their FD-SOI technology as the right solution for the 4th Revolution, which includes everything from energy harvesting to self-driving cars. They’ve just taped out their first 5G mmWave cellular chip on 28FDS, he revealed. eMRAM is looking very good, only requiring three additional masks and getting stable yields from -40o to 105oC. 18FDS is on schedule, with PDK 0.5 now being released, and 1.0 on track for release in March 2019. They expect a very fast ramp, and are looking at a 35% area reduction, power cut in half and performance up 22% compared to 28FDS.

 

RF-SOI Highlights

China Mobile, Project Manager Danni Song (Photo courtesy: Simgui)

When China Mobile talks, the world listens. Project Manager Danni Song presented again this year (she gave a great talk last year, too). China has a very ambitious 5G project underway, and under two years in which to roll it out. The biggest challenges are power consumption and cost (a problem made worse by the additional power amplifiers needed for MIMO). Can RF-SOI help solve these challenges, she asked? One thing she did clarify during the panel discussion was with respect to the mmWave part of the 5G puzzle. Their initial 2020 rollout will only focus on sub-6GHz, with mmWave following a year or two later.

Michael Reiha, Head of RFIC R&D at Nokia Mobile Networks clarified the worldwide 5G rollout during the panel discussion. Different locations on the planet have different histories and needs, so will rollout 5G in different ways. For historical reasons (and a lack of choice), the US will lead with mmWave, he said. Europe, meanwhile, will focus on 24GHz to meet the needs of automotive radar.

In his presentation, Reiha described Nokia’s approach to power amplifiers (PA), which is very different from what others are doing. With RF-SOI, he said, you can add sensors and logic for a level of preventative care, so you can gauge and protect your equipment using AI. He believes this disruptive approach will put them two years ahead of the industry, enabling massive MIMO to be deployed in dense urban areas with 60% lower power consumption and 50% savings in material costs. Go read about their Reefshark tech, he urged, which he says will beat GaAs. “The future is very bright with RF-SOI,” he concluded. “I can state that with confidence.”

Julio Costa, Director of Technology Development, Qorvo (Photo courtesy: Simgui)

Julio Costa, Director of Technology Development at Qorvo sees it differently. Traditionally a GaAs house, all their RF-SOI work is fabless. While RF front end modules (FEMs) are loaded with RF-SOI, he said, and are a big winner for antenna tuning, Qorvo still sees GaAs for high-efficiency amplifiers and envelope tracking. But, he said, it will be a battle. GaAs wins in terms of area and power consumption he contends, but adds that SOI wins in terms of cost. Power levels, he predicts, will be the determining factor.

So that’s the quick overview – we’ll drill down into the presentations as they’re posted, so stay tuned!

4G/5G Opps for SOI Supply Chain – Workshop Presentations Now Posted

The presentations from the SOI Consortium sponsored workshop held during Semicon West are now posted and freely available on the website – click here to see the full agenda with links to the presentations. The workshop, entitled 4G/5G Connectivity: Opportunities for the SOI Supply Chain, was well-attended and generated excellent discussions.

If you don’t have time to look at all of the ppts, here are quick overviews.

Market Overview and FD SOI Opportunities, by Handel Jones, CEO, IBS.

Handel Jones is an industry veteran, China expert and longtime follower of the SOI ecosystem. High performance with low power consumption are the key requirements for the continued growth in the semiconductor industry, he said, making FD-SOI the right choice for a wide range of products. Here’s how he sees it:

(Courtesy: IBS and SOI Consortium)

He estimates the yearly TAM (total available market) for FD-SOI based products in the range of $46 billion over the next 10 years, largely driven by needs for ultra-low power and RF integration. He goes on to break out volumes by applications (including ISPs – image signal processors; and CIS – CMOS image sensors), foundry markets by feature dimension and to map out technology trends.

Mobile Radio Transformation in the Age of 5G: A Perspective on Opportunities for SOI, Peter Rabbeni, Vice President, Globalfoundries.

Peter Rabbeni is an RF expert par excellence, having overseen the shipping of over 35 billion RF-SOI products to date. In his presentation, he details how 5G NR (New Radio) sub-6GHz frequency band specifications significantly increase frequency range and channel bandwidth, and how new band support and MIMO complexity and die size per handset are driving complexity in RF FEMs. Furthermore, 5G/mmWave phased arrays are driving a paradigm shift in the approaches that can be taken, he explains, so greater integration is needed. Here’s a great slide showing where GF’s two main SOI technologies come into play:

(Courtesy: GlobalFoundries and SOI Consortium)

Empowerment of 5G with SOI-Based Technologies, Emmanuel Sabonnadière, CEO, Leti-CEA.

(Courtesy: Leti and SOI Consortium)

Working in partnership with industry leaders around the world, Leti has been the research powerhouse behind all things SOI since the early 1980s. In fact Reuters ranks them #2 in their most recent list of the World’s Most Innovative Research Institutions. This presentation reviews the key technical benefits of FD-SOI for IoT and IMT (that’s international mobile communications, btw).

Engineered Substrates – at the Foundation of 5G, Thomas Piliszczuk, Executive Vice President, Soitec.

This presentation really puts the context around engineered substrates. Here are two excellent and useful slides here that identify which engineered substrates go where in the 5G world, and the engineered substrates that Soitec provides. Check these out:

(Courtesy: Soitec and SOI Consortium)

(Courtesy: Soitec and SOI Consortium)

Ultra-thin Double Layer Metrology with High Lateral Resolution, Bernd Srocka, Vice President, Unity GmbH.

(Courtesy: Unity and SOI Consortium)

In case you’re not familiar with them, Unity provides a wide range of solutions in metrology and inspection. Both the top silicon layer and BOX layer of wafers for FD-SOI applications have draconian requirements that have required new approaches in metrology to ensure the thickness and homegeneity control of these very thin layers.

China 5G Plan and SOI Ecosystem, Jeffrey Wang, CEO, Simgui.

Shanghai-based Simgui partners with Soitec, using SmartCut™ technology for the production of RF-SOI wafers. It is doubling its capacity to reach 400K over the next year, and expanding into 300mm. China is aggressively working on 5G and plans to deploy 5G commercialization in 2020. Jeff Wang’s is a terrific presentation detailing the rollout. (BTW, in addition to the massive funding effort underway, the government created the National Silicon Industry Group (NSIG) to support the semiconductor material ecosystem in China. You’ll want to keep up with what’s going on here). Here’s the slide that summarizes the SOI ecosystem in China – the presentation then goes on to detail who does what.

(Courtesy: Simgui and SOI Consortium)

Inspection and Metrology Relevance in SOI Manufacturing, Jijen Vazhaeparambil, Vice President & General Manager, KLA-Tencor.

(Courtesy: KLA-Tencor and SOI Consortium)

K-T has played a strategic role in the SOI story going back for decades (and in fact they wrote a piece for the third edition of ASN back in 2005!), ensuring metrology innovations for things that hadn’t previously need detection and measurement. With each new set of requirements, they rose to the occasion with wafer metrology solutions that helped increase quality and decrease costs. This presentation recaps some of them.

 

pSemi: World’s First Monolithic SOI Wi-Fi FEM

pSemi (formerly Peregrine, now a Murata company) has staked its claim for having the world’s first monolithic SOI Wi-Fi front-end module (FEM)—the PE561221. This 2.4 GHz Wi-Fi FEM is the first to integrate a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T) on a single SOI CMOS die. pSemi says it’s ideal for Wi-Fi home gateways, routers and set-top boxes (read the full press release here).

Driving this is the new WiFi standard, IEEE 802.11ax, which launches next year. While it’s largely meant to tackle issues with WiFi in crowded places, it’s also going to be welcome in high-demand home situations. (There’s a good piece on the NetworkWorld site on what 802.11ax will do compared to the current 802.11ac – you can read it here).

The PE561221 uses a smart bias circuit to deliver a high linearity signal and excellent long-packet EVM performance. (Courtesy: pSemi)

With new standards come new challenges. pSemi explains their PE561221 uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance.

“Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance,” says Colin Hunt, vice president of worldwide sales at pSemi.

The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules. It is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration, notes pSemi—the unique design ability to integrate RF, digital and analog components on a single die.

Volume-production parts and samples of the PE561221 are now available from pSemi. And this is just the beginning: while the PE561221 is the first product in the pSemi Wi-Fi FEM portfolio, the product roadmap includes 5 GHz Wi-Fi FEM solutions.

The folks at pSemi have been doing RF-SOI for 30 years now, and recently shipped their 4 billionth chip. For the last five years, they’ve partnered with GlobalFoundries.