NEW Filter our 213 articles by market or company:
• IBM, STM, Hitachi, Leti, Soitec on FD-SOI
• Special supplement: SOI Industry Consortium
• Medical apps: KEK, Hitachi, UCL, Nanosens
• IEEE fellows, Industry Buzz and more

May. 6, 2010 BroadPak joins SOI Industry Consortium
SOI Industry Consortium confirms new board members
Mar. 23, 2010 Major semiconductor companies join forces to launch design chain solution for silicon-on-insulator technology

SOI ‐
The
next
five
years: The
critical
role
that
SOI
will
play
in
the
semiconductor
market
Euro
SOI
2010
- Grenoble,
France
[Horacio Mendez, Executive Director, SOI Industry Consortium]
Presentation: Silicon results of ARM core 1176 in SOI – A 40% power reduction
[by Remy Pottier, Jonathan Tong, Chris Hawkins, Roma Kundu and Jean-Luc Pelloie, ARM]

Jun. 23, 2010 SOI Scalability
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]
Jun. 9, 2010 Cadence Announces Comprehensive SOI Design Hub
[Cadence]
May. 24, 2010 Cadence, IBM team for 32-nm SOI IP
[EDN]
Apr. 7, 2010 Getting IP, Tools, And People “Ready For SOI”
[Cadence]
Apr. 6, 2010 The Time is Right for SOI Technology Adoption
[ChipEstimate.com]

Jul. 1, 2010 EDA Consolidation Continues
It too is expanding its product portfolio and launched a comprehensive silicon-on-insulator (SoI) Design Hub, a new Web portal that will help lower barriers to adoption of SoI technology by reducing initial start-up costs, reducing time ... [Sramana Mitra on Strategy]
Jul. 1, 2010 Ellison Makes Pressure Transducers Using Silicon on Sapphire
[SA Instrumentation & Control]
Jun. 23, 2010 AMD's Opteron 4100s march into x64 price war
Both chips are implemented in a 45 nanometer silicon on insulator process and manufactured by GlobalFoundries, the chip foundry that AMD spun out last year. [The Register]

The Truth About Power and Process Technology
[Horacio Mendez, Executive Director, SOI Industry Consortium]
Low-Power Design with Material Impact on Silicon-on-Insulator Technology
[Horacio Mendez, Executive Director, SOI Industry Consortium]
SOI – Integrated Technology, IP and Design Flow for Customer Success
[Gordon Starkey, IBM Systems & Technology Group; David Desharnais, Group Marketing Director, Cadence Design Systems; Tom Lantzch, VP Marketing, ARM]
• White paper on Silicon On Insulator (SOI) implementation [Infotech Enterprises Ltd.]
• Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic [UC Louvain]
texte [Chipestimate.tv]
[by Harry Gries, ASIC Methodology and EDA Technology Consultant]