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Download the presentations of the October 21, 2009 conference.

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The SOI Design Experience

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Varian Chartered Semiconductor Manufacturing Stanford University Magma Design Automation Ritsumeikan University STMicroelectronics KLA-Tencor Corporation Université Catholique de Louvain Shin-Etsu Handotai Freescale Semiconductor

ARM GLOBALFOUNDRIES AMD IBM UMC Tyndall National Institute Synopsys Soitec Innovative Silicon IMEC

Mentor Graphics Kanazawa Institute of technology Cadence Design Systems Infotech Berkeley, University of California Applied Materials Semico Samsung NVIDIA Lam Research

CEA-Leti GLOBALFOUNDRIES IBM IMEC Stanford University Ritsumeikan University Cadence Design Systems AMD ARM Infotech

Past events

Workshop on Fully depleted SOI readiness
Organized by The SOI Industry Consortium, CEA-Leti and Soitec

When: Wednesday, December 9, 2009 - From 6pm to 9:15pm, starting with networking reception
Where: Hilton Baltimore, Holiday conference rooms 4 and 5

Complementing the technical papers and short courses presented during the IEDM conference, the workshop will be devoted to SRAM scaling, design porting from bulk to FDSOI, BSIM models, the results of porting an ARM core to SOI and TCAD with an outlook towards the specificities for FDSOI.

The workshop will provide a comprehensive review of the current state of technology presented by renowned experts in the field: IBM, LETI, UC Berkeley and ARM.

» Detailed program

SOI Industry Consortium Design Clinic at ARMtechon3
October 21, 2009
Santa Clara Convention Center
Santa Clara, California, USA

FD SOI architecture, technology platform for Low Power applications for 22nm and beyond
We have the honour to invite you on an ad-hoc workshop “FD SOI architecture, technology platform for Low Power applications for 22nm and beyond”. This workshop will be held on October 16, 2009 in IMEC.

The development of fully depleted SOI has gained strong momentum in recent years. Although initially FinFETs appeared to be a preferred FDSOI architecture, recent major advances in planar FDSOI devices are strongly positioning this technology towards an interception of the 22/20nm node for Low Power applications. From a design perspective, planar FDSOI is an evolutionary approach that is easier to implement than FinFETs. FDSOI CMOS has proved to reduce the Vt variability by 50-60%, makes possible the smallest SRAM cell operated at Vdd=0.5V with an excellent SNM, reduces Ioff by orders of magnitude and preserves a target performance at a cost per die that is comparable or lower than the equivalent bulk.

This workshop on SOI technology, sponsored by the SOI Consortium and IMEC, for the first time addresses in one day the entire ecosystem that will be necessary to bring the FDSOI technology to industrial maturity and widespread adoption. In the morning session, the technology options for FDSOI CMOS architecture will be discussed, and the afternoon will be devoted to SRAM scaling, the porting of an ARM core to PDSOI and TCAD with an outlook towards the specificities for FDSOI. The workshop provides a comprehensive review of the current state of technology presented by renowned experts in the field.

Click here to see the detailed program. In order to provide time for networking and discussions with the speakers there will be ample time between sessions; we are also happy to invite you to a reception after the workshop…

We strongly encourage you to participate in the workshop and contribute to the advancement of FDSOI technology.

Registration for this FDSOI workshop is mandatory, and can be done by sending an email to corepartner_meetings@imec.be.

We are looking forward to seeing you at the FDSOI Workshop on October 16th.

Horacio Mendez
Director, SOI Consortium

Malgorzata Jurczak
Manager, IMEC

2009 IEEE International SOI Conference
October 5-8, 2009
Crowne Plaza Hotel
Foster City, California, USA

46th Design Automation Conference
July 26-31, 2009
Moscone Center
San Francisco, California, USA