Tag Archive 10nm

GF’s 12nm FD-SOI With Back Bias Beats 10nm FinFET Performance (EETimes)

With back bias,12nm FD-SOI beats 10nm FinFET on performance. This excellent news comes in by way of Peter Clarke of EETimes Europe (read the whole article here). Rutger Wijburg, GM of GloFo’s Dresden fab told him, “If you look at performance with back-bias 22FDX is the same or better than 16/14nm FinFET process. With 12FDX with back bias you get better than 10nm FinFET processes.”

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

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Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:

S3S15lineup

The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.

IEEE SOI-3D-Substhreshold (S3S) Conference Issues Call for Papers

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers.

Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and invited talks on three main topics: SOI technology, subthreshold architectures with associated designs and 3D integration. With its 40-year history, the SOI segment continues as world’s premier conference to present and discuss state of the art SOI technical papers.

The 2014 edition was a great success (click here to read about it).  The deadline for submissions for the 2015 conference is April 15, 2015 (click here for complete submission information).

SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.

We learned all this and much more during the very successful 2014 IEEE S3S Conference.

The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.

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Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.

(Photo credit: Justin Lloyd)

S3S Conference Poster & reception session. (Photo credit: Justin Lloyd)

 The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.

 The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.

 

Sub-Threshold Microelectronics

The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.

3D Integration

The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).

Key Fully-Depleted SOI Technical results

Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.

STMicroelectronics and CEA-Leti gave us a wealth of information on:

  • From "Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology" in the S3S '14 "Energy Efficiency" short course by P. Flatresse (Source: STMicroelectronics)

    From “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the S3S ’14 “Energy Efficiency” short course by P. Flatresse (Source: STMicroelectronics)

    How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).

  •  How to use FMAX tracking to maintain optimal Vdd, VBB values during operation. This shows how you can take advantage of both Vdd and VBB dynamic modulation to maintain your circuit’s best performance when external conditions (e.g. temperature, supply voltage…) vary. (E. Beigné, “FDSOI Circuit Design for a Better Energy Efficiency”).

The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).

In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.

More than An Order of Magnitude Energy Improvement of

From S3S 2014 Best Paper, “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains” (AIST)

The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.

On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

FinFET_SOI_IBM_S3S14_Mobility_1

Join the conference in 2015!

Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.

The organizing committee is looking forward to seeing you there!

~~~

 

Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory.  He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT.  Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices.  Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.

Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors.  He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999.  As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials.  As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes.  He has authored or co-authored over 50 papers and holds over 10 patents.

 

 

*RO = ring oscillator

 

 

Welcome to IEEE S3S – the World’s Leading Conference for SOI, 3DI and Sub Vt (SF, 6-9 Oct)

S3Sheader

(For best rates, register by September 18th.)

The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.

Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.

This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.

 

Short courses: Monolithic 3D & Power-Efficient Chip Tech

On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.

The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.

The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.

 

Conference program

The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.

Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.

Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.

We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.

Our technical content is detailed on our program webpage.

 

Panel discussions, cookout & more

Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.

SFstreetsignOur conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.

The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.

Please take a moment to learn more about our conference by browsing our website or downloading our advance program.

To take full advantage of this outstanding event, register before September 18!

Special hotel rates are also available from the dedicated hotel registration page.

The committee and I look forward to seeing you in San Fransisco.

– Bruce Doris, S3S General Chair

 Photo Credit: Catherine Allibert

Photo Credit: Catherine Allibert

Good FD-SOI Summer Reading & Viewing

 

Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher.

But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up.

In mid-June, Samsung posted a video of their DAC presentation, Samsung 28nm technology for the next big thing on YouTube.  Presented by JW Hwang, Principal Engineer for Samsung Electronics, it runs almost 14 minutes long, with the entire second half devoted to 28nm FD-SOI.  Here are some key points made therein:

  • The smartphone market is saturating, except in China.
  • Internet of Things (IoT) is The Next Big Thing – and it’s a far bigger market (heading towards $9 trillion per IDC) than smartphones. It’s about affordability & connectivity, with a lot of sensors and generating a lot of data (which will need low-power processing).
  • 28nm is the sweet spot, and FD-SOI simplifies processing, lowering costs – and it gets better performance.
  • Designers shouldn’t be afraid of FD-SOI, as the design flow is the same as bulk planar, and there’s a lot to be gained by body biasing.
  • Most of the IP is already product-proven, and the PDK is currently available.
  • The technology transfer from ST to Samsung is underway, and Samsung expects to have it fully qualified for high volume by March 2015.
  • A second generation with additional IP that will further decrease chip size is also in the works.
 Samsung2814FD  Samsung228FDready

Samsung DAC ’14 video – process complexity vs. performance/power.

Samsung DAC ’14 video – 28nm FD-SOI is  product-proven

Here at ASN, of course, there was the terrific piece by industry expert Handel Jones (IBS) entitled FD-SOI: The Best Enabler for Mobile Growth and Innovation.  IBS concludes the benefits of FD-SOI are overwhelming for mobile through Q4/2017. Jones also looks for it to have a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs.

Also in ASN, we covered the SOI Papers at the 2014 VLSI Symposia.   Three top SOI-based papers included one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs, and the two on 10nm SOI FinFETS. (In Part 2, we covered the rest of the SOI papers.)

Elsewhere, we saw high-profile, open debate, which is excellent and necessary.  Semiwiki has been a great platform for discussion, with a steady flow of FD-SOI articles – many of which generate ferociously active discussions in the comments section. Here’s a round-up of what went on this summer:

  • Is SOI Really Less Expensive? by Scotten Jones (24 June ’14) generated a whopping 56 comments.  Jones’ company, IC Knowledge, used its IC cost modeling on bulk planar, FD-SOI, bulk FinFETs and SOI FinFETs. Jones concluded that at 14nm, costs were fairly comparable, which was hotly debated by readers (with FD-SOI supporters fortifying their claim that it comes in significantly cheaper). However, no one quibbled with Jones’ final conclusion: “Decisions on which process to pursue are therefore expected to be driven by factors other than cost.”
  • Keywords: FD-SOI, Cost, FinFET by Eric Esteve (15 July ’14) followed up on Jones’ piece, generating another super-heated round of comments: 41 in all. Esteve dove into the different approaches to multiple threshold voltages (Vt) between FD-SOI and FinFET, and looked at the advantages of biasing in FD-SOI, concluding that FD-SOI should do 10% better on cost than Jones projected. Heavy hitters from all sides chimed in, many with very insightful and sometimes deeply technical information and explanations.
  • Setting the Record Straight on FD-SOI Costs by Scotten Jones (21 July 14) pushed back on the Esteve “keyword” piece, as well as on an ASN blog, “Is FD-SOI Cheaper? Why yes!”, (27 June ’14).  However, in the end, he reminded readers that costs won’t be the deciding factor.
  • FD-SOI: 20nm Performance at 28nm Cost by Paul McLellan (28 July ’14) covered a presentation given by Samsung’s Kelvin Lo about their foundry strategy at the CSPA (Chinese Semiconductor Professionals Association) meeting. Low reiterated that 28nm FD-SOI is the sweet spot for low-power, high performance. McLellan then briefly covered the Cadence quarterly conference call, which indicated interest in FD-SOI is up.
  • FD-SOI Target Applications Are… by Eric Esteve (1 Aug. ’14) looked at the big picture. He had listened to the July ST analyst call, where they said they had 18 FD-SOI ASIC design wins.
  • FD-SOI at 14nm by Paul McLellan (17 Aug. ’14) looks at an ST presentation given at SemiconWest in 2013 – a good overview with some pertinent technical detail.

Next, check out this interesting post in SemiconductorEngineering by Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys.  She gives a very informative perspective on “Power Reduction Techniques” (7 Aug. ’14) in bulk planar, FD-SOI and FinFETs. She talks about how biasing in FD-SOI is highly effective, then goes on to summarize various power-reduction techniques by process node. There’s an excellent summary in her graphic (her Figure 2):

synopsys_FDSOI_FF_poweropt

There’s also a terrific chart in the same article based on the annual Synopsys’ Global User Survey (GUS), indicating which power techniques are used most in which applications (mobile, automotive, networking, etc.).

If talk on LinkedIn is any indication, the design community in India is very interested in FD-SOI.  EE Herald published a much-shared interview with ST’s CAD/design solutions director in India (18 July ’14), entitled  FDSOI; The only semiconductor tech to continue Moore’s Law down to 10nm. It gives an excellent overview of the technology, answering some of the basic questions designers are asking.

Finally, the folks at the silicon prototyping brokerage CMP pointed us at a bit of humor – and as they say, a picture’s worth a thousand words….

FFvFDSOIcomic16e7be0

 

 

FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.

 

FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.

 

FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

 

The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.

 

Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.

 

FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.

The SOI Papers at VLSI ’14 (Part 2):

Last week we posted Part 1 of our round-up of SOI papers at the VLSI Symposia – which included the paper showing that 14nm FD-SOI should match the performance of 14nm bulk FinFETs. (If you missed Part 1, covering the three big 14nm FD-SOI and 10nm FinFET papers, click here to read it now.)

This post here gives you the abstracts of all the other papers we couldn’t fit into Part 1.  (Note that as of this posting date, the papers are not yet available on the IEEE Xplore site – but they should be shortly.)

There are in fact two symposia under the VLSI umbrella: one on technology and one on circuits. We’ll cover both here. Read on!

 

(More!) SOI Highlights from the Symposium on VLSI Technology

4.2: III-V Single Structure CMOS by Using Ultrathin Body InAs/GaSb-OI Channels on Si, M. Yokoyama et al. (U. Tokyo, NTT)

The authors propose and demonstrate the operation of single structure III-V CMOS transistors by using metal S/D ultrathin body (UTB) InAs/GaSb-on-insulator (-OI) channels on Si wafers. It is found that the CMOS operation of the InAs/GaSb-OI channel is realized by using ultrathin InAs layers, because of the quantum confinement of the InAs channel and the tight gate control. The quantum well (QW) InAs/GaSb-OI on Si structures are fabricated by using direct wafer bonding (DWB). They experimentally demonstrate both n-and p-MOSFET operation for an identical InAs/GaSb-OI transistor by choosing the appropriate thickness of InAs and GaSb channel layers. The channel mobilities of both InAs n- and GaSb p-MOSFET are found to exceed those of Si MOSFETs.

 

4.4:  High Performance InGaAs-On-Insulator MOSFETs on Si by Novel Direct Wafer Bonding Technology Applicable to Large Wafer Size Si, S. Kim et al. (U. Tokyo, IntelliEPI)

The authors present the first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by a direct wafer bonding (DWB) process using InGaAs channels grown on Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs have exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement factor of 3× against Si MOSFETs.

 

6.1: Simple Gate Metal Anneal (SIGMA) Stack for FinFET Replacement Metal Gate Toward 14nm and Beyond, T. Ando et al. (IBM)

The authors demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate technology with a 14nm design rule. The SIGMA stack uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100x PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (Lg) scaling compared to the conventional stack with matched gate resistance due to absence of high resistivity WF-setting metal and more room for W in the gate trench. This gate stack solution opens up pathways for aggressive Lg scaling toward the 14nm node and beyond.

 

8.1: First Demonstration of Strained SiGe Nanowires TFETs with ION Beyond 700μA/μm, A. Villalon et al. (CEA-LETI, U.Udine, IMEP-LAHC, Soitec)

The authors presented for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si1-xGex (x=0, 0.2, 0.25) nanowires, Si0.7Ge0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. They analyzed the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices were also investigated, showing a 1/W3 dependence of ON current ION per wire. The fabricated devices exhibit higher Ion than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

8.2: Band-to-Band Tunneling Current Enhancement Utilizing Isoelectronic Trap and its Application to TFETs, T. Mori et al. (AIST)

The authors proposed a new ON current boosting technology for TFETs utilizing an isoelectronic trap (IET), which is formed by introducing electrically inactive impurities. They  demonstrated tunneling current enhancement by 735 times in Si-based diodes and 11 times enhancement in SOI-TFETs owing to non-thermal tunneling component by the Al-N isoelectronic impurity complex. The IET technology would be a breakthrough for ON current enhancement by a few orders in magnitude in indirect-transition semiconductors such as Si and SiGe.

 

9.1: Ge CMOS: Breakthroughs of nFETs (I max=714 mA/mm, gmax=590 mS/mm) by Recessed Channel and S/D, H. Wu et al. (Purdue U.)

The authors report on a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). Both junctionless (JL) nFETs and pFETs are integrated on a common GeOI substrate. The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current (Imax) of 714 mA/mm and trans-conductance (gmax) of 590 mS/mm, high Ion/Ioff ratio of 1×105 are archived at channel length (Lch) of 60 nm on the nFETs. Scalability studies on Ge nFETs are conducted sub-100 nm region down to 25 nm for the first time. Considering the Fermi level pining near the valence band edge of Ge, a novel hybrid CMOS structure with the inversion-mode (IM) Ge pFET and the accumulation-mode (JAM) Ge nFET is proposed.

 

13.4: Lowest Variability SOI FinFETs Having Multiple Vt by Back-Biasing, T. Matsukawa et al. (AIST)

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (Vt) necessary for multiple Vt solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain cur-rent (Ion) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of Vt (AVt=1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (Gm). Back-biasing through the SOTB provides excellent Vt controllability keeping the low Vt variability in contrast to Vt tuning by fin channel doping.

 

13.6: Demonstration of Ultimate CMOS based on 3D Stacked InGaAs-OI/SGOI Wire Channel MOSFETs with Independent Back Gate (Late News), T. Irisawa et al. (GNC-AIST)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

 

17.3: Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era (Invited), S. Kamohara et al. (Low-power Electronics Association & Project, U. Electro-Communications, Keio U, Shibaura IT, Kyoto IT, U.Tokyo)

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, the authors describe their recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other lcircuits. Their 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

 

18.1: Direct Measurement of the Dynamic Variability of 0.120μm2 SRAM Cells in 28nm FD-SOI Technology, J. El Husseini et al. (CEA-Leti, STMicroelectronics)

The authors presented a new characterization technique successfully used to measure the dynamic variability of SRAMs at the bitcell level. This effective method easily replaces heavy simulations based on measures at transistors level. (It’s worth noting that this could save characterization/modeling costs and improve the accuracy of modeling.)  Moreover, an analytical model was proposed to explain the SRAM cell variability results. Using this model, the read failure probability after 10 years of working at operating conditions is estimated and is shown to be barely impacted by this BTI-induced variability in this FD-SOI technology.

 

18.2: Ultra-Low Voltage (0.1V) Operation of Vth Self-Adjusting MOSFET and SRAM Cell, A. Ueda et al. (U. Tokyo)

A Vth self-adjusting MOSFET consisting of floating gate is proposed and the ultra-low voltage operation of the Vth self-adjustment and SRAM cell at as low as 0.1V is successfully demonstrated.  In this device, Vth automatically decreases at on-state and increases at off-state, resulting in high Ion/Ioff ratio as well as stable SRAM operation at low Vdd. The minimum operation voltage at 0.1V is experimentally demonstrated in 6T SRAM cell with Vth self-adjusting nFETs and pFETs.

 

18.3: Systematic Study of RTN in Nanowire Transistor and Enhanced RTN by Hot Carrier Injection and Negative Bias Temperature Instability, K. Ota et al. (Toshiba)

The authors experimentally study the random telegraph noise (RTN) in nanowire transistor (NW Tr.) with various NW widths (W), lengths (L), and heights (H). Time components of RTN such as time to capture and emission are independent of NW size, while threshold voltage fluctuation by RTN was inversely proportional to the one-half power of circumference corresponding to the conventional carrier number fluctuations regardless of the side surface orientation. Hot carrier injection (HCI) and negative bias temperature instability (NBTI) induced additional carrier traps leading to the increase in the number of observed RTN. Moreover, threshold voltage fluctuation is enhanced by HCI and NBTI and increase of threshold voltage fluctuation becomes severer in narrower W.

 

SOI Highlights from the Symposium on VLSI Circuits

C19.4: A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. E. Olieman et al. (U.Twente)

The authors presented an innovative nine-bit interleaved DAC (digital-to-analog converter) implemented in a 28nm FD-SOI technology. It uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. In addition, its clock timing can be tuned by back gate bias voltage. The DAC features an 11 GS/s sampling rate while occupying only 0.04mm2 and consuming only 110mW at a 1.0V supply voltage.

 

UTwenteC194VLSI14lowres

(Courtesy: VLSI Symposia)

A nine-bit interleaved digital-to-analog converter (DAC) from the University of Twente uses two-time interleaving to suppress the effects of the main error mechanism of current-steering DACs. The low-power device features an 11 GS/s sampling rate and occupies only 0.04mm2. From A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist, E. Olieman et al. (University of Twente)

 

 

C6.4: A Monolithically-Integrated Optical Transmitter and Receiver in a Zero-Change 45nm SOI Process, M. Georgas et al . (MIT, U.Colorado/Boulder)

An optical transmitter and receiver with monolithically-integrated photonic devices and circuits are demonstrated together for the first time in a commercial 45nm SOI process, without any process changes. The transmitter features an interleaved-junction carrier-depletion ring modulator and operates at 3.5Gb/s with an 8dB extinction ratio and combined circuit and device energy cost of 70fJ/bit. The optical receiver connects to an integrated SiGe detector designed for 1180nm wavelength and performs at 2.5Gb/s with 15μA sensitivity and energy cost of 220fJ/bit.

The SOI Papers at VLSI ’14 (Part 1): Breakthroughs in 14nm FD-SOI, 10nm SOI-FinFETs

The VLSI Symposia – one on technology and one on circuits – are among the most influential in the semiconductor industry. Three hugely important papers were presented – one on 14nm FD-SOI and two on 10nm SOI FinFETs – at the most recent symposia in Honolulu (9-13 June 2014). In fact, three out of four papers in the Highlights Sessions covered SOI devices for the 10 and 14nm nodes.

There were so many great SOI-based papers that we’re going to cover this conference in two posts.  This post covers the three big 14nm FD-SOI and 10nm FinFET papers. Summaries and abstracts of all the others will be covered in Part 2 (click here to read Part 2).  Please note that as of this posting date, the papers are not yet available from the IEEE Xplore site – but they should be shortly.

Read on!

Top SOI Highlights from the Symposium on VLSI Technology

2.3: 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications. O. Weber et al. (STMicroelectronics, CEA-LETI, IBM)

This is the big paper we’ve been waiting for – the one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs. We still don’t have a side-by-side FD-SOI v. bulk FinFET comparison, as there is scant data at comparable leakage on bulk FinFETs at 14nm publicly available with which to compare. But based on what they’ve been seeing and some extrapolation, the FD-SOI  technology developers see the figures presented in this paper as a big win.  We’ve already seen hints of this in a recent ASN piece (click here to see that one) showing 14nm FD-SOI matching 14nm bulk for performance and coming in at a much lower cost.  Now in terms of performance, here’s the VLSI paper detailing the FD-SOI side of the story.

The authors confirm a scaling path for FD-SOI technology down to 14nm, using strain-engineered FD-SOI transistors. Compared to 28-nm FDSOI, this work provides an 0.55x area reduction from scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back-bias, an additional 40% dynamic power reduction for ring oscillators is experimentally demonstrated. Moreover, a full single-port SRAM is described, including a 0.081 μm2 high-density bitcell and two 0.090 μm2 bitcell designs used to address high-performance and low-leakage/low Vmin requirements.

Paper-T2.3-14nm-FDSOI-Technology-for-High-Speed-and-Energy-Efficient-Applications

(Courtesy: VLSI Symposia)

 

TEM of an FD-SOI nMOS transistor, showing gate-to-drain capacitance components and experimental values. From 14-nm FDSOI Platform Technology for High-Speed and Energy-Efficient Applications (O. Weber et al., STMicroelectronics, CEA-LETI & IBM)

 

 

 

 

 

2.2: A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI.  K.-I. Seo et al.  (Samsung, IBM, ST, GF, UMC)

This paper covers the first-ever demonstration of FinFET technology suitable for 10-nm CMOS manufacturing. Targeting low-power and high-performance, it offers the tightest contacted poly pitch (64 nm) and metallization pitch (48 nm) ever reported on both bulk and SOI substrates. A 0.053 μm2 SRAM bit-cell – and this part was on SOI –  was reported with a low corresponding static noise margin of 140 mV at 0.75 V.  The team developed intensive multi-patterning technology and various self-aligned processes with 193i lithography to overcome optical patterning limits. A multi-workfunction gate stack provides Vt tunability without the variability degradation channel dopants induce.

Paper-T2.2-A-10nm-Platform-Technology-for-Low-Power-and-High-Performance-Applications-Featuring-FINFET-Devices-with-Multi-Workfunction-Gate-Stack-on-Bulk-and-SOI

(Courtesy: VLSI Symposia)

 

Projected scaling trend, featuring the tightest contacted poly pitch (CPP=64 nm) and metallization pitch (Mx=48 nm) ever reported, on both bulk and SOI substrates. From A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI, by K.-I. Seo et al.  (Samsung, IBM, ST GF, UMC)

 

 

 

 

2.4: Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

The authors demonstrated high performance (HP) s-SiGe pMOS pMOSsfinFETs with Ion/Ieff of ~1.05/0.52mA/μm and ~1.3/0.71mA/μm at Ioff=100nA/μm at VDD=0.8 and 1V, extremely high intrinsic performance and source injection velocity. Compared to earlier work, an optimized process flow and a novel interface passivation scheme, result in ~30% mobility enhancement and dramatic sub-threshold-swing reduction to 65mV/dec. They also demonstrate the most aggressively scaled s-SiGe finFET reported to date, with WFIN~8nm and L G~15nm, while maintaining high current drive and low leakage. With their very low GIDL-limited ID, min and more manufacturing-friendly process compared to high-Ge content SiGe devices, as well as impressive Ion~0.42mA/μm at Ioff =100nA/μm and gm, int as high as 2.4mS/μm at VDD=0.5V, s-SiGe FinFETs are strong candidates for future HP and low-power applications.

VLSI_2.4

(Courtesy: VLSI Symposia)

 

TEM images of the most aggressively scaled SiGe FinFET reported to date with a fin width of ~8nm and gate length of ~15nm. From Strained Si1-xGex-on-Insulator PMOS FinFETs with Excellent Sub-Threshold Leakage, Extremely-High Short-Channel Performance and Source Injection Velocity for 10nm Node and Beyond, P. Hashemi et al. (IBM, GlobalFoundries, MIT)

 

 

 

Rump Sessions

There were also two rump sessions held during the conference, which were co-chaired by Soitec CTO Carlos Mazure. The SOI ecosystem was well-represented, the rooms were packed and the debate lively.

Rump Session 1: Who gives up on scaling first: device and process technology engineers, circuit designers, or company executives?  Which scaling ends first – memory, or logic? Panelists: M. Bohr, Intel; M. Cao, TSMC; J. Chen, Nvidia; S-H Lee, Hynix; T-J King Liu, UC Berkeley; K. Nii, Renesas: R. Shrivastava, Sandisk; H. Jaouen, STMicroelectronics; E. Terzioglu, Qualcomm

The take-away here is that the majority of panelists and attendees see company executives giving up on scaling in the face of rising costs.

Rump Session 2: 450 mm, EUV, III-V, 3D; All in 7nm? Are you serious?!  Panelists:  W. Arnold, ASML;
 R. Gottscho, Lam Research; K. Hasserjian, AMAT; S. Iyer, IBM;
 C. Maleville, Soitec; A. Steegen, IMEC

The general consensus was that 3D integration is needed and will be adopted at the 7nm node due to delays and the high cost of the EUV and III-V, and the lack of 450mm wafer supply and support.

14nm FD-SOI Presentation by ST Posted on WeSRCH

ST14FDweSRCHA ppt presentation by STMicroelectronics entitled Features and Benefits of 14nm UTBB* FD-SOI Technology is now posted on WeSRCH (click here to view it). It is fairly technical, covering process boosters, modules and innovations, mask sequences, performance and scalability.