It’s a bright green light from the world leaders in SOI wafer capacity. Soitec, the world leader in SOI wafer production, and long-time partner Shin-Etsu Handatai (SEH), the world’s biggest producer of silicon wafers, have extended their licensing agreement and expanded their technology cooperation.
SEH is a $12.7 billion company, supplying over 20% of the world’s bulk silicon wafers. SEH’s relationship with Soitec goes way back: they were one of the original corporate investors back in 1997, and the first to license Soitec’s Smart CutTM technology for manufacturing SOI wafers.
With its 300mm SOI wafer production fabs in France and Singapore, Soitec has an expandable installed industrial base of two million wafers per year.
As Horacio Mendez, Executive Direct of the SOI Consortium told ASN, “This is a very significant announcement. The substrate supply chain is fully engaged: we have multiple independent suppliers that can clearly meet the market demands for all key sectors, including mobile devices. As the advanced technology nodes ramp, the wafer production is in place; and very importantly, the capacity is expandable to provide maximum flexibility to customers.”
SEH has been manufacturing standard SOI wafers using Smart Cut technology for years. And last year, the company said it had completed development of its ultra-thin BOX (aka UTB — the wafers used for planar FD-SOI) substrates. Nobuo Katsuoka, director of the SOI program at SEH, recently told Semiconductor Manufacturing & Design, “SEH is delighted to deliver the products on request.”
Wafers for FD-SOI (a “planar” “2D” technology) have Angstrom-level uniformity in their ultra-thin layers – so it’s excellent news that the the industry’s two leaders are both supply sources.
SOI wafers for FinFETs (a “vertical” or “3D” technology, for which the top silicon and insulating BOX layer don’t have to be ultra-ultra-thin) have also long been available from Soitec, SEH and other sources.
With respect to this announcement, SEH’s Katsuoka said, “We are very excited about the business opportunities for SOI products, and we look forward to working with Soitec to extend the global supply chain for new products, such as FD-SOI and SOI for FinFETs, which are showing potential benefits in mobile and embedded applications. Our relationship with Soitec has been a very positive and fruitful one, and we are excited to extend that collaboration. The unique features of Smart Cut will enable our two companies to jointly improve global output for existing and new SOI products.”
As Steve Longoria, SVP of WW Business Development at Soitec, told ASN, “The wafer is the front end of the manufacturing process. This announcement is a proof point of new energy for robust, multi-source supply for impending high-volume demand.”
The newly announced Soitec-SEH agreement also extends the companies’ commitment to wafers for a broad-range of areas. For example, there are major market opportunities in SOI for RF devices, power, MEMS/sensors, photonics and more.
The agreement also extends to R&D for technologies of the next wave. We might think of Smart Cut as an SOI technology, but in fact it’s really a manufacturing technology that can be applied to a huge range of wafer materials. As a result of the extended agreement, SEH will continue to use Soitec’s industry-defining Smart Cut technology to manufacture SOI wafers, and now will be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), which will allow SEH to further expand its scope of applications.
So with an abundance of opportunities, a robust multi-source supply chain for the front end of the chip manufacturing process, top-quality wafers that enable savings and efficiencies – in short, better end-user value – it’s all systems go for high-volume demand.
Want to learn first-hand what’s going on in the world of FD-SOI? (aka Fully-Depleted Silicon-On-Insulator)
The SOI Industry Consortium, CEA-Leti and Soitec are organizing the 6th edition of the Fully Depleted Workshop. Presentations will be given by experts from ST, ARM, IBM, Leti, UCBerkeley, Soitec, Accelicon & the SOI Consortium.
It’s a full-day event at the Marriott Marquis Hotel in San Francisco, California, on February 24th following the ISSCC conference (which runs February 19-23). Registration for this free event is now open – click here.
The workshop is designed to give chip designers and manufacturers the latest information and insights on using FD-SOI technology to produce more power-efficient ICs at the right performance levels.
Planar FD-SOI and SOI-based FinFETs are serious, cost-effective contenders for the next generations of low-power, high-performance CMOS devices. They are disruptive technologies providing critical solutions for the fast-growing mobile and consumer electronics markets. However, SOI-based fully-depleted technologies also represent a clear, evolutionary path from existing bulk technologies.
The Consortium’s been giving these workshops all over the world following major conferences for a few years now, and they’ve been a terrific success. (You can download papers from the previous workshops from the Consortium website.)
This workshop is co-organized by Dr. H. Mendez from the SOI Industry Consortium, Dr. O. Faynot from CEA-Leti and Dr. C. Mazure from Soitec.
Feedback from previous workshops has been excellent. This edition is addressing product, design and technology, and provides an excellent window onto the fast-growing the fully depleted (FD) ecosystem.
The workshop will provide breakfast, coffee break and lunch to allow time for informal discussions. Lively discussions with the speakers always follow.
Here’s a preview of program – you won’t want to miss it.
|7:30am||Badge pick up & On-site registration|
|8:30am||Introduction by Carlos Mazure (Soitec)|
|8:40am||Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Design by Philippe Flatresse (ST Microelectronics)|
|9:10am||Planar Fully Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond: Technology by Michel Haond (ST Microelectronics)|
|9:40am||Recent Advances in FDSOI by Bruce Doris (IBM)|
|10:30am||Library and Physical IP Porting for FDSOI by Jean-Luc Pelloie (ARM)|
|11:00am||20nm FDSOI Models by Brian Chen (Accelicon & SOI Consortium)|
|11:30am||FinFET on SOI by Terrence Hook (IBM)|
|1:00pm||Enabling Substrate Technology for a Large Volume Fully Depleted Standard by Christophe Maleville (Soitec)|
|1:30pm||Strain Options for FDSOI by Olivier Faynot (CEA – Leti)|
|2:00pm||Advanced FDSOI Design by Bora Nikolic (UC Berkeley)|
|2:20pm||Closing Remarks by Horacio Mendez (SOI Consortium)|
|2:30pm||Networking and coffee buffet|
A new study compares processes for the 20/22nm generation at a typical foundry.
Silicon On Insulator (SOI) has been in use for state-of-the-art integrated circuit (IC) manufacturing since IBM first championed the technology in the mid-nineties. SOI offers process technologists the option of reducing power or improving performance for a given process node.
As process technology has continued to advance it has become practical to manufacture SOI wafers with silicon layers that are thin enough for Fully Depleted SOI (FDSOI). Also referred to as Extremely Thin SOI (ETSOI), FDSOI processes offer process technologists the opportunity to significantly simplify the process of manufacturing an IC.
IC Knowledge, the world leader in IC cost and economics was retained by Soitec, the world leader in SOI wafer manufacturing, to compare the cost of a FDSOI process versus a Bulk process for 22nm/20nm foundry logic processes.
One of the challenges of state-of-the-art foundry processes is providing the multiple threshold voltages required for power management and performance. At a minimum an additional threshold voltage requires two threshold adjust masks and associated implants.
As process geometries have shrunk additional threshold voltages may also require tailoring of source/drain (S/D) extension and halo implants and even S/D contact implants (both extension/halo and contacts each require multiple implants to fabricate).
The result is a single threshold voltage can require up to five masks and fifteen implants.
FDSOI on the other hand can provide multiple threshold voltages by alternative means (including the option to shift the threshold voltage by actively controlling the biasing of the back gate), eliminating the need for threshold adjust masks and implants entirely.
An FDSOI foundry process with eight metal levels and three threshold voltages can be fabricated with up to fifteen less masking steps and forty-eight fewer implants than a similar bulk process. The resulting process simplification was found to more than offset the higher cost of the starting SOI substrate and result in a cost competitive process versus bulk with better performance.
As processes scale down to 22nm/20nm and beyond standard bulk process transistors can no longer be scaled down without exhibiting unacceptable leakage properties. Techniques such as FDSOI offer better control of the transistor channel and far lower leakage making them a viable technical solution to leakage problems. As has been shown in this study FDSOI also offers an economically viable solution.
In conclusion FDSOI processes offer sufficient process simplification to offset the additional cost of the starting SOI substrate and be cost competitive with bulk processes.
Note: the full FD-SOI cost report is available as a free download from IC Knowledge.
What are you going to do with your SOCs at 20/22nm? The options seem to boil down to just staying on bulk CMOS, or changing to FinFETs or planar, fully-depleted (FD) SOI-based CMOS.
Though some may find comfort in staying on bulk CMOS, it’s getting very complicated – and complicated get expensive fast. The FinFET option (which can be on bulk or SOI) is exciting for the longer term,but in the short term still raises significant design and manufacturing challenges. That leaves FD-SOI — which in terms of cost, performance, power and complexity is turning out to be an extremely attractive option.
You’ve probably heard that FD-SOI promises major savings in power (40%) and/or a big boost in performance (25 to 80% – depending on the Vdd and design type – over low-power bulk technology). And a recent study found that FD-SOI will be cheaper to fab than bulk because it’s less complicated.
Perhaps also you’ve heard that designing for FD-SOI is pretty much the same as designing for planar bulk CMOS. But what would it mean from a design perspective to actually port your existing bulk SOCs to FD-SOI? What would the impact be? What would you have to do?
Member companies of the SOI Consortium – including ARM, Leti, UCL, IBM, GlobalFoundries and Soitec – have tackled these questions. The Consortium just posted a major technical white paper called, “Considerations for Bulk CMOS to FD-SOI Design Porting”.
It’s a must-read for anyone working on the leading edge.
Over the next few months, here at ASN we’ll be publishing excerpts and summaries. But to give you an idea of the magnitude of this paper, here is an overview.
The scope of the study is to examine the efforts required to port existing bulk CMOS designs to FD-SOI at the same node – so we’re comparing apples to apples, as it were. It considers both bulk-to-FD-SOI IP Porting and full chip design porting.
With respect to the full chip design porting, it considers two potential paths:
There’s a section on the FD-SOI design specificities that need to be taken into account. It sorts out in significant detail devices and electrical characteristics that are addressed at the technology level, looks at any impacts at the designer level, and indicates what is foundry-dependent.
The meat of the document is in a section called “Impact Per Design Domain”. Here it goes into the impact of an FD-SOI port on logic library cells, memory compilers, I/Os and ESD protections, analog & mixed-signal IP, and the choice of porting approach (fastest vs. most optimized) right down to sign-off considerations.
Those considering the “most optimized” approach will want to look at the appendices that go into great detail on back-biasing for VT shifting or tuning (more efficient than, although similar to the body-biasing used in some bulk designs), as well as “native” multi-VT.
Finally, the References section is a treasure trove, listing the most important FD-SOI papers presented at the top conferences over the past few years – including VLSI, IEDM, ISSCC, the SOI Conference and more.
Overall, the approach is technical but approachable. Let us know what you think.
A comprehensive cost analysis study by research firm IC Knowledge concludes that FD-SOI wafers offer the most cost effective solution compared to bulk silicon for the 22 nm node and beyond. The study uses a Strategic Cost Model to evaluate how process flows would perform in a Taiwanese wafer fab producing 30,000 wafers per month in the 2012 timeframe. Strictly based on costs, it does not consider FD-SOI’s potential performance improvements in leakage and speed. The study is freely available for downloading.
For those new to FD-SOI, here’s a short description of the basic principles.
FD SOI transistors are constructed on an ultrathin Silicon layer (< 10nm) set on the top of an ultra-thin BOX (thickness <20nm). This architecture represents a fundamental difference from previous generations of SOI and offers a distinct improvement in power, performance and processed wafer cost over Bulk transistor.
The major obstacles in scaling both the voltage and the transistor geometry are driven by manufacturing fluctuations. Fully Depleted SOI controls transistor fluctuations by nearly eliminating the variability due to channel-dopant distribution.
The objective of producing wafers with a thin Buried Oxide (BOX) is to enable back-bias. The back-bias is applied through a Well contact, etched through the BOX .With back-bias, the transistor Vt can be readily controlled by appliying voltage to the Well under the gate (fig1).
The advantage of impletmenting back-bias in FD SOI as opposed to Bulk is that the BOX acts as an isolation barrier for p-n juction leakage. The back bias can be controlled independently for the P and N transistors to optimize leakage and performance.
Publications by Hitachi’s Yamaoka et al, show that “by using a forward back-gate bias, Ion can be increased by about + 20%. While using a reverse back-gate bias, Ioff can be reduced by about up to 90%. Even if we apply some voltages to the back gate, the substrate current does not increase”. These measurements were made at 65nm. The advantages become even more acute at 20nm and below (see Figure 2).
These transistor advantages in FD SOI, provide significant advantages for mobile SoC’s.
|Target Markets||Mobile computing of all kinds: Games, smart phones, tablets, etc.|
|Power||Provides low power at handset class performance|
|Performance||Power/performance improves at lower voltage|
|Leakag||Lower leakage by design|
|Complexity||Simpler and cost-efficient manufacturing. This is particularly true when compared to 3-D transistors such as FinFETs|
|Design Compatibility||Fully compatible with bulk, no floating body effects to worry about|
For more in-depth information, see the white paper on the SOI Consortium website.
One of the key projects currently underway within the SOI Consortium is to understand and provide guidance on the advantages and obstacles of porting SoC designs from Bulk to FD-SOI. This project represents a strategic opportunity to help drive the profile of FD SOI and participate in the emergence of this important technology.
Objective: Analyze details of a design migration from 20LPM to 20ET
Current participants: IBM, Qualcomm (limited), Soitec, ARM, GlobalFoundries
Deliverables: Provide a comprehensive and credible answer to the question, “What will it take to port a SoC design from Bulk to FD-SOI CMOS in the most straight-forward way?” The output will be a short manual or white paper describing the design porting steps.
Key Focus areas:
Timescale (tentative): Final release is currently slated to be ready in time for the DAC conference (June 5th).
One of the world’s leading experts, Professor Fossum explains why SOI represents a pragmatic approach to future transistor generations.
Based on our recent studies of multi-gate MOSFETs (“MuGFETs”) for CMOS applications, which are mainly modeling- and simulation-based with experimental support from Freescale Semiconductor, we have suggested that nanoscale FinFETs can and should be designed pragmatically, with:
• double gates (DG),
• a near-midgap metal (for both nMOS and pMOS),
• an undoped ultra-thin fin-body (UTB),
• a relatively thick nitrided oxide (no high-k dielectric needed),
• and an optimal gate-source/drain underlap. Read More