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Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

(Image courtesy: SEMI)

 

For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.

And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.

So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.

Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.

For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.

In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.

 

FD-SOI at the Semicon Europa Low Power Conference

The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conferencewhich features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.

Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.

Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.

Other talks include imec on FinFETs, Imagination Technology on MIPS, Qualcomm on the “Landscape for More Moore”, and Leti on FD-SOI and 3D stacking for multicore embedded systems.

Renesas will detail their flavor of FD-SOI, which they’ve been working on for a long time (especially with innovations from Hitachi). They call it Silicon-on-Thin-Buried Oxide, aka SOTB.

David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)

Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.

Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)

The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).

ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.

 

Power and 3DI

A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.

Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.

Hope to see you in Grenoble!

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FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.

 

FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.

 

FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

 

The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.

 

Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.

 

FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.

By

Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets

By Handel Jones

IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry.  The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within the next 24 to 60 months, covering the 28nm, 20nm and 14/16nm nodes.

We conclude that:

  • at 28nm and 20nm, the lower power consumption and higher performance of FD-SOI compared to planar bulk CMOS gives major competitive advantages to FD-SOI in high volume portable applications.
  • the lower cost of FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI for high volume applications at this technology node.

Here is a brief summary of our findings.

 

Overview

High volume applications need lower cost per transistor in order to use the new generation of process technologies. It is, consequently, appropriate to evaluate the options for continuing the pattern of lower cost per gate, with the analysis of different technology options.

After the 28nm node, the decreasing cost-per-gate trend with reduction in feature dimensions for bulk CMOS is reversed: at 20nm, cost-per-gate starts to increase rather than decrease.

Cost Per Gate Reduction Trends

(Source: IBS)

IBS14_costpergate

The impact of not reducing cost per gate is one of the most serious challenges that the semiconductor industry has faced within the last 20 to 30 years. It is, consequently, appropriate to evaluate whether other options are available that can allow scaling to 20nm and smaller feature dimensions to be effective in cost and power consumption because of the large financial impact on the semiconductor industry of not continuing with Moore’s Law.

 

Wafer Cost Analysis

 Our analysis considers depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.

 Already at 28nm, the wafer cost is lower for FD-SOI than for bulk HKMG CMOS, although with a relatively small difference. The key reason for the lower cost of FD-SOI is the smaller number of mask and processing steps.

 The cost analysis is based on eight-layer metal and 3Vt levels. The following graph is built from the more detailed analysis in our report.

IBS14_FDSOI_FinFET_wafercost

Furthermore, while the difference in total yielded wafer cost at 28nm and 20nm is not very large, it is very important to remember that the FD-SOI technology has the added advantage of providing significantly lower leakage and higher performance than the bulk CMOS.

The reality is that performance of 28nm FD-SOI is 15% better than 20nm bulk CMOS and extends the lifetime of the 28nm technology node. Lower cost, lower power consumption, higher performance, the conclusions are clear.

The situation is even more compelling at 14/16nm.

The wafer cost for 14nm FD-SOI is 18.4% lower than 16nm FinFET.  A key factor contributing to the high cost of FinFET wafers is that of the extensive inspection steps required to ensure high yield and high reliability. A number of wafer processing steps need to be tightly controlled and monitored with the processing of FinFET structures. The result is that depreciation cost per wafer for FinFET structures is significantly higher than for FD-SOI.

Note: the generation we call 20nm FD-SOI in our report is called “14FD” by ST Microelectronics, as they also position it as a competitor to 14/16nm FinFET.

 

Die Cost

While wafer cost is an important factor, die cost is a more vital factor for most companies. Our analysis includes yielded wafer cost, gross die/wafer and yield. 

IBS14_FDSOI_FinFET_diecost

At 28nm, FD-SOI has higher yield, slightly lower die cost (3%) and 30% lower power consumption than bulk CMOS. At 20nm, FD-SOI die cost is 13% lower than bulk CMOS, has higher yield, and is expected to provide 40% lower power consumption.

At 14nm/16nm, the FD-SOI die cost for a 100mm2 die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.

The lower cost of the FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI at this technology node.

However, despite the fact that FD-SOI is clearly more cost effective, large investments are being made by the pure-play foundries in 14/16nm FinFET wafer processes, and while FinFETs will be needed in the future, the issue is timing. It is clearly in the interest of the fabless industry to pay lower die prices, and collaboration with the foundry vendors is needed in this arena. The power structure in the industry has moved too much in favor of the provider rather than the user.

For the fabless industry, the key requirement for FD-SOI is to establish supply chains that can support the participation in high-volume end markets. The fabless companies need to be much more active in ensuring that their needs are being satisfied.

Strategic Considerations Within the FD-SOI Supply Chain

Strategic considerations within the FD-SOI supply chain include the following:

  • Complex, working products with FD-SOI at 28nm have been demonstrated by STMicroelectronics with significant performance and power consumption advantages compared to bulk CMOS.
  • The supply chain for FD-SOI starting (i.e., raw) wafers is in place (by Soitec, SunEdison, and Shin-Etsu Handotai (SEH)) and can be expanded rapidly to provide the required wafer capacity if a demand environment is established.
  • The use of body biasing provides significant performance and power consumption advantages for FD-SOI. Body-biasing methodologies for FD-SOI can use EDA tools that have been developed for bulk CMOS technology.  Also, design flows for FD-SOI are effectively identical to those for bulk CMOS. However, it is important for the EDA vendors to become more proactive regarding the potential opportunities for FD-SOI.
  • Libraries and basic IP developed for bulk CMOS can be easily modified for FD-SOI. The cost of modification between bulk CMOS and FD-SOI is approximately 10% of that required to migrate to a new technology node for bulk CMOS at 20nm.

An ecosystem needs to be set up for FD-SOI, and it is important for the electronics industry that this ecosystem is established.

Conclusion

There are many advantages for FD-SOI to be widely adopted for high volume, low cost, and lower power applications in the future. It is important for the semiconductor industry to be willing to make investments to provide optimum solutions to its customers rather than follow the roadmap of a specific company. The fabless companies need to be proactive in supporting the supply chain within an FD-SOI ecosystem.

Timing of the migration to 20nm, 14nm, and 10nm technology nodes need to be based on cost, power consumption, and performance metrics that can be easily verified. Being short-term focused and not willing to adopt new concepts can have large cost penalties within the foundry-fabless environment.

FD-SOI technology can be viable in many applications for the next ten years. The semiconductor industry needs to be willing to make the investments for the future rather than responding to short-term pressures.

Cost penalties resulting from very high design costs and long time-to-market can have a serious impact on the competitiveness of semiconductor vendors that select the FinFET approach at 14/16nm. Semiconductor companies that are participating in fast-moving markets cannot tolerate the additional costs of design and long time-to-market associated with trying to fine-tune technologies that are inherently high cost.

While migration to FinFETs may be required beyond the 10nm node, until then FD-SOI represents the best approach for many of the high volume segments of the semiconductor industry.

The reality is that the foundry vendors will not invest unless they have a high probability of getting customers. This means that the customers need to provide the leadership and accept that the present roadmaps in the industry will not provide them with the best financial returns.

ByGianni PRATA

New FD-SOI Presentation by ST on Design & Reuse Looks at Cost, IP

D+R_ST_FDSOIslideDesign & Reuse has posted an excellent presentation by Giorgio Cesana of ST entitled FD-SOI Technology for Energy Efficient SoCs: IP Development Examples (click here). It explains why the technology is faster-cooler-simpler – and more cost effective.

After a quick tour of the tech basics, Cesana gets into cost/performance ratios, comparing the technology to bulk planar (28/20nm) and bulk FinFET (16/14nm).  He then gives examples of ARM core IP, and how FD-SOI is leveraged in ultra-low-voltage, analog and high-speed apps.

By

Foundry, Experts at Shanghai FD-SOI Workshop Indicate Major Opportunities in China

Aiming to promote the benefits of SOI technology and reduce the barriers to market adoption, the SOI Industry Consortium (a group of leading companies with the mission of accelerating SOI innovation into broad markets), SIMIT (Shanghai Institute of Microsystem and Information Technology), CAS (a pioneer of SOI technology in China), and VeriSilicon Holdings Co., Ltd. hosted an “SOI Technology Summit” in Shanghai, China.

Executives of leading companies, universities and institutes, covering all the segments  (substrate, design, manufacturing, EDA, IP, etc.) gathered to discuss the solutions to scaling challenges and the market opportunities for FD-SOI in China.

Handel Jones from IBS presented the IC market overview (available here) and detailed the cost difference between the different available technologies. He made the point that FD-SOI is cost competitive at 28nm and has the advantage at 20nm.

IBS SHANGHAI

David Jacquet from ST highlighted (available here) the design benefits of back-biasing (the FD-SOI version of body biasing),  which is only going to be available in FD-SOI technology since it cannot be implemented in planar bulk or FinFET in an effective manner. ST showed how back bias can provide real time optimization of the power-performance trade off and therefore give the most efficient mobile power saving results.

XMC’s Simon Yang gave a foundry manufacturing perspective on FD-SOI technology  (available here), confirming that FD-SOI has a lot of advantages. In particular, it is perceived as the simplest way to enter the realm of fully depleted technologies. Also, he emphasized the necessity that the cost of FD-SOI be lower than competitive technologies, which aligned well with Handel Jones’ cost analysis.  The wafer manufacturers also confirmed that the substrate price will enable the technology to be lowest cost.

XMC Shanghai

Zhongli Liu, a very highly respected professor at IM CAS urged the Chinese IC industry to see the golden opportunity in FD-SOI technology. He detailed the technology benefits with well-chosen case studies (available here) and concluded that FD-SOI has broader markets since it has perfect features to match the needs of the mobile applications.

Imcas Shanghai

Rama Divakaruni from IBM presented a compelling talk on the IBM scaling path at 14nm, 10nm and 7nm (available here). For calculation-intensive applications such as servers, IBM is developing a 14nm FinFET on SOI with eDRAM that provide significant value propositions.  Rama reminded the audience that IBM has developed both FD-SOI and FinFET on SOI, the latter being more adapted for IBM’s applications. However, depending on application and design style FD-SOI might be better suited.

SEH, SunEdison and Soitec presented wafer specifications and available capacity for RF-SOI, FD-SOI and FinFET on SOI. They showcased RF-SOI to demonstrate that SOI can be a mainstream solution meeting the cost and volume of the market demand.

Panel discussions at the end of the workshop were passionate regarding China’s opportunity to develop FD-SOI capacity, which could be a great accelerating factor for the China IC industry. This would require a commitment from foundries and design companies, which all agreed looks like the right thing to do.

ByAdministrator

Ready for FD-SOI, Says World’s Largest Silicon Wafer Company

The world’s largest maker of silicon wafers, Shin‐Etsu Handotai (SEH) says it’s meeting the specs for FD-SOI wafers, and can quickly expand capacity to meet rising demand.

This message was delivered by Nobuhiko Noto of SEH during his presentation at the recent FD-SOI Workshop in Kyoto, Japan.

SEH, a $12.7 billion company supplying over 20% of the world’s bulk silicon wafers, has been making SOI wafers since 1988. In 1997, SEH introduced SOI wafers produced using Soitec’s Smart CutTM technology. (Soitec is the world leader in SOI wafer production.) Last year, the two companies extended their licensing agreement and expanded their technology cooperation.

The specs for FD-SOI wafers are very exacting.  As Soitec has pointed out, required silicon uniformity across a full 300mm-diameter wafer corresponds to about 5mm (less than a quarter of an inch) over the distance between Chicago and San Francisco.

Here’s what SEH is saying:

asn_2013-07-11

Presentations from the Kyoto FD-SOI workshop – including an excellent short course on FD-SOI design techniques – are now freely available on the SOI Consortium website.

ByAdministrator

GlobalFoundries On Cost vs. Performance for FD-SOI, Bulk and FinFET

According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die cost by 30%, while FD-SOI only increases die cost by 10%. (Both HPP and FD-SOI are HKMG/GateFirst).

GF

Moving to 20nm, the graph indicates that FD-SOI gets an additional 25% performance increase: that’s terrific. This slide doesn’t give a performance increase figure for 20LPM, but it’s clearly way below 20nm FD-SOI.

Now there are no actual figures given for die cost at 20nm, but the position on the graph indicates that the shrink to 20nm on FD-SOI costs substantially less than the cost for shrinking on bulk.   Later in the presentation, he indicated that a big part of the savings is in masks – FD-SOI requiring 10 fewer masks than bulk.

Interesting to note the position of 14XM, which is a bulk FinFET. Again, no actual figures are given, but die cost is substantially higher. However the relative performance increase does not appear to be very significant.

The presentation was made during the FD-SOI Workshop following VLSI in Kyoto, Japan. It is available from the SOI Consortium website.

Other presentations

Looking ahead to 14nm FD-SOI for high performance, ST’s  Laurent Le Pailleur showed this interesting slide in his Kyoto Workshop presentation, 28nm FD-SOI Industrial Solution: Overview of Silicon Proven Key Benefits – again, lots of masks saved:

ST

There are other presentations from the Workshop available on the Consortium website, including a terrific short course by David Jacquet of ST entitled Architectural choices & design-implementation methodologies for exploiting extended FD-SOI DVFS & body-bias capabilities.

For those wanting to know more about FinFETs on SOI, Terry Hook of IBM expanded on his excellent ASN article in a presentation entitled Elements for the Next Generation FinFET CMOS Technology. In particular, there are lots of clear explanations about why SOI makes a difference, and the role of wafer-level strain (aka “strained silicon directly on insulator” – which IBM calls SSDOI)  wafers by Soitec.

IBM

ByAdministrator

ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups

The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group.

Introduction to FD-SOIAs you no doubt know by now, at CES a few weeks ago, ST-Ericsson showed the new NovaThor L8580, which integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die. Process technology and manufacturing credit goes to ST.  In a live video from the show, the chip reached 2.8GHz in a high-performance demo, and in a low-power demo hit 1GHz using just 0.636V (which would take 1.1V on bulk).

Since then, Giorgio Cesana, Director of Technology Marketing at STMicroelectronics, has been everywhere, responding to questions from readers and correcting misunderstandings as they arise.

One of the top things people want to know more about is biasing in FD-SOI, which can provide a big performance boost or huge power savings.

LinkedIn In case you missed it, here’s what Giorgio had to say to questions posed in the big LinkedIn Semiconductor Professional’s Group:

Thank you all for this interesting discussion and for giving me the opportunity to provide more details about the ST 28nm FD-SOI technology. I hope this clarifies any misunderstandings.” 


Body bias, or more properly back bias (because biasing is done on the back face of the transistor) is a way to electrically control the Vt of the device by controlling of the polarization of the wells. 


Conceptually, it is like having the planar transistor controlled by two gates: the real “classical” gate, we build with a HKMG, gate-first manufacturing approach, and a virtual gate (represented in the video with a transparent gate below the transistor) that represents the capability to control the transistor through biasing. 


The back gate is the “virtual” one. It does not require any extra manufacturing steps to be fabricated. It is created simply by polarizing the well. 


The particular FD-SOI technology that ST is using, called UTTB (Ultra Thin Body and Box), benefits from a extremely thin (25nm) Buried Oxide (BOX) which enables extremely efficient control of the transistor threshold voltage through the biasing, up to 80mV/V. In addition, because of the insulator in FD-SOI, biasing is not limited to 300mV like in bulk technologies, allowing an extremely wide dynamic control of the transistor Vt. 


In terms of biasing efficiency, this past Dec 10th we published some figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at 0.6V. 

That said, exploiting body biasing is a matter of making a design that provides an independent supply to the wells, managed through the power supply controller, to optimize the Vt to reach proper energy efficiency, balancing the static and dynamic part of the power consumption. Of course biasing conditions should be considered at design optimization and sign-off phase. 


Finally body/back biasing in FinFETs simply does not work, because the transistor channel is vertical and the gate controls 3 sides of the channel. The 4th side (the one sitting on the substrate) is too narrow to be influenced through body biasing. Body biasing is simply not an option with FinFETs. 


Someone at one of the big programmable device companies then asked a follow-up question on the implementation. Giorgio responded:

In 28nm FD-SOI, threshold-voltage centering is a function of the gate work function, where the Vt is controlled by implanting a ground plane (GP) below the BOX (Buried Oxide). Depending on its type (N or P), Vt can be raised by more than 50mV, allowing the manufacturer to offer two device flavors: regular Vt and low Vt. 


Threshold voltage is also statically controlled by modulating the gate length. ST’s multi-channel standard-cell library allows us to modulate the gate length up to +16nm, offering a static leakage control of up to 50x for a single Vt design, almost twice the leakage control offered by dual-Vt designs plus multi-channel libraries of competing bulk planar technologies. 


Body bias is just one way to modulate the threshold voltage, and the dynamic nature of the control allows new and innovative design solutions to be implemented for extremely energy efficient designs.

I should note that body-bias usage is not mandatory in FD-SOI: we can make devices without using it and which still benefit from a good speed/power balance, low Vmin memories, better device variability, and all the other benefits FD-SOI processing offer. Chip architects can also decide to limit body-bias adoption only to some critical blocks/IPs in the SoC for the best trade-off between optimal energy efficiency and implementation simplicity. 

For further reference, you may read F. Arnaud, “Switching Energy Efficiency Optimization for Advanced CPU thanks to UTBB Technology,” IEDM 2012.

To reader questions posted in the comments sections of SST and EETimes articles, Giorgio cleared up some other misunderstandings. Here is a summary of some of the things he said:

FD-SOI vs. PD-SOIUltra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect.

In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

Self-heating: Self-heating is also a problem that exists with Partially-Depleted SOI technologies, where the Buried Oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects.

UTBB FD-SOI technology offers two advantages to overcome this self-heating:

– The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;

– The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

We are moving from a raw 12nm thick silicon film (=120A, +/- 5A) to a final film of 7nm (=70A) under the transistors. This is a perfectly repeatable process and is already qualified for production at ST.

Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

Manufacturability: to prove manufacturability, the recent announcement from ST-Ericsson about their NovaThor L8580 product, which was demonstrated at CES, is capable of running its eQuad ARM cores up to 2.8GHz, while still fitting a mobile smartphone thermal footprint and proving (if needed) the potential and the maturity of FD-SOI technology.

Additional recommended reading:

– O. Faynot et al, “Planar Fully Depleted SOI Technology: a powerful architecture for the 20nm node and beyond”, International Electron Device Meeting Technical Digest, 2010
– Advantages of UTBB FD-SOI:  A. Khakifirooz at al., “Extremely thin SOI for system-on-chip applications”, CICC 2012*, written by authors from IBM, STMicroelectronics, LETI, Renesas, and GLOBALFOUNDRIES.

*Editor’s note: ETSOI is what IBM calls its flavor of FD-SOI.

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To keep up-to-date on the latest in SOI-related news, please join us at the Advanced Substrate News LinkedIn group.

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IBS Study Concludes FD-SOI Most Cost-Effective Technology Choice at 28nm and 20nm

In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure).

For a technology to be utilized in high-volume production, costs must be lower than previous generations of technology.  The industry thus faces a critical juncture in the shrink from 28nm to the nodes around 20nm (the precise dimensions of which vary by foundry).  Making the wrong technology decisions at ~20nm can cost wafer manufacturers and fabless companies billions of dollars.  It is therefore appropriate to analyze the cost factors for the different versions of 28nm as a baseline.

Multiple factors need to be considered with the migration to ~20nm, and the highly visible experience to date in attaining high yielding, volume production on 40nm and 28nm from the industry’s largest players provides visibility into what is likely to happen at 20nm bulk.

IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy.

For the purposes of our analysis, we consider die sizes of both 100mm2 and 200mm2. The flavors we considered are for high-performance (HP) and low-power (LP) chips. The technology options at the 28nm node are high-k/metal-gate (HKMG) bulk CMOS vs. FD-SOI. For the ~20nm node, we add FinFET to the analysis.

Savings realized by using FD-SOI at the ~20nm node

As shown in this graph, the savings realized by using FD-SOI at the ~20nm node is significant. Even once FinFETs have matured in Q1/2016, FD-SOI will still offer comparative savings of 50-60%, depending on die size.

Result: FD-SOI die cost less

At the 28nm node, if you only look at the processed wafer cost, the FD-SOI solutions are roughly 7% higher. However, yield issues and the net die/wafer at 28nm have a major impact on the bottom line. When defect densities and parametric yields are factored in, the FD-SOI solution results in a lower per-die cost: from 8% lower for the smaller, low-power chips, to 18% for large, high-performance chips.

At 20nm, however, the FD-SOI processed wafer cost is less than both bulk CMOS and FinFET processed wafers. The FD-SOI processed wafer cost advantage is then massively increased when yields are factored in.

Once ~20nm bulk FinFETs have matured in Q1/2016, FD-SOI will still offer comparative per-die savings of 50-60%.

Related FD-SOI advantages

Power/performance characteristics of FD-SOI will be 30% to 40% superior to bulk HKMG CMOS at 20nm. Analog porting of FD-SOI will be easier than with the other options because of the superior sub-threshold characteristics.

Today, FD-SOI is the only technology that can operate safely in the 0.6V to 0.7V range at 28nm.  While there is some reduction in performance, operating power is reduced, giving a very compelling performance-power advantage against other technologies.

Although the real competition is likely to be between FinFETs and FD-SOI at 20nm, FinFETs are a new technology (from a high-volume production perspective), with significant cost penalties even in Q1/2016.

Bulk HKMG CMOS will have low parametric yields at 20nm.  A major source of yield loss for bulk CMOS is that of random dopant fluctuations from transistor implants. These implants are not required for FD-SOI.  ~20nm FinFET structures will be high-cost to manufacture, and parametric yields will be low.

The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs.

So compared to bulk CMOS or FinFET, the FD-SOI option cuts ramp time by as much as half.

The faster ramp-up of wafer volumes combined with more predictable yield ramp-up provides additional cost benefits in using FD-SOI over other options at 20nm.

There is ongoing work to assess the further scalability of FD-SOI beyond 20nm to ~14nm and the initial results from IBM and Leti look promising.

Notes on starting parameters

For the purposes of this analysis, the processed wafer costs are derived from experience with leading foundries, for their costs in Q1/13 with eight metal layers (8LM).  (Selling prices of processed wafers will of course be higher and will include the gross profit margins of the foundry vendors.)  The processed wafer costs include $500 for the ultra-thin SOI wafer used in the FD-SOI process, and $129 for the bulk wafer used in bulk CMOS and bulk FinFET technologies. (While there is the expectation that the SOI wafer prices will be reduced in the future, this is not built into our analyses.)

We assume a high-volume production with utilization rates of about 95%. The bulk version assumes three threshhold voltages (Vt) in the core of the chip, and takes into account support for SRAMS and interfaces. The FD SOI cost is based on 1Vt level for the core and use of body biasing. Body biasing can give two additional Vt levels in the core, which is equivalent to bulk CMOS design options.

Wafer and die costs vary at different stages of maturity. For FinFETs, for example, the cost takes into account the relatively long time for metrology checking in the process and also the manufacturing complexity related to the FinFET structures.

ByAdministrator

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.

What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact models from Leti – is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP (Circuits Multi Projets®). ST is releasing this process technology to third parties as it nears completion of its first commercial FD-SOI wafersWhat you can get from CMP is the same process technology that will be available to all at GlobalFoundries in high-volume next year.

The CMP multi-project wafer service allows organizations to obtain small quantities of advanced ICs – typically from a few dozen (for a prototype, say) to over a hundred thousand units (for low-volume production). CMP is a non-profit, non-sponsored organization created in 1981, with a long history of offering SOI and other advanced processes. It offers industrial quality process lines – with industrial-level, stable yields. Headquartered in Grenoble, France, CMP has over 1000 clients in 70 countries.

The cost of ST’s 28nm FD-SOI CMOS process at CMP has been fixed at 18,000 €/mm2, with a minimum of 1mm2.  At this point in scaling, that gets you about two million gates – about eight million transistors.  So the pricing is very aggressive for an advanced technology node – and it comes down if you get more than 3mm2, and even more if you get >15mm2, Kholdoun Torki, CMP Technical Director explained to ASN.

Dr. Torki was kind enough to elaborate a bit on the particulars for us. Here’s what he says. The ST design kit contains a full-custom part, and standard-cells and I/O libraries with digital design-flows supported under Cadence Encounter and Synopsys Physical Compiler. The design-kit is from ST Front-End Manufacturing and Technology, Crolles. CMP delivers this design-kit under NDA.

Devices are supported for UTSOI (ultra-thin SOI) models, which were developed by and are the property of Leti.

The UTSOI model is available under Eldo from Mentor and Hspice from Synopsys. It is also expected to be available for Spectre (Cadence) and for Golden Gate and ADS (Agilent) within the next few months.

CMP provides the first level support (installation, and general questions on the use of the kit). Multi-Projects Wafer runs are organized at ST Crolles. For low volume production, a quote is issued on a case-by-case basis, on request.

The ST 28nm FD-SOI offering has a true 28nm BEOL metallization with .1µ metal pitch, says Dr. Torki.

CMP also has offered the Leti 20nm FD-SOI R&D process since 2010. (In fact for those looking even further ahead, Leti has predictive model cards down to 11nm.) It is expected the 20nm FD-SOI process from ST, incorporating strategic technology from Leti, will be available from CMP towards the end of next year, although the exact date has not yet been fixed.

How it works

In Multi-Project Wafer runs, costs are shared (and reduced) because the reticle area is shared across customers. CMP offers one-stop shopping, including:

  • NDA processing
  • the design-kits linking CAD and processes, and related support
  • Design submission, checking, and final database to the Fab
  • Wafer sawing and Packaging
  • Export license processing
  • Chip delivery

Because reticles are shared across multiple designs, CMP customers benefit from very attractive pricing. (Courtesy: CMP)

Last year (2011), CMP handled 273 circuits, including prototypes, low-volume production runs and industrial applications.

For organizations like the 77 customers in 23 countries using 28nm bulk CMOS through CMP’s program, migrating from 28nm CMOS bulk to 28nm FD-SOI will be seamless, says Dr. Torki. There are no disruptions in process or design. There are the same layer numbers and names, so they can load a bulk design directly into an FD-SOI design environment. They use the common design-rules platform (ISDA alliance design-rules), and bulk devices can be co-integrated with FD-SOI devices as needed.

These are real, leading edge chips and circuits we’re talking about. Here’s what you get:

  • 28nm HK/MG FD-SOI with ultra-thin BOX and ground plane
  • 10 Cu metal layers: (6 thin + 2 medium + 2 thick)
  • Triple Well (Deep N-Well allows the P-Well to be isolated from the substrate)
  • Single IO oxide + Single core oxide.
  • Double VT: 1.0V Low Vt transistors (LVT) + 1.0V super Regular Vt transistors (RVT)
  • Low Leakage (high density) SRAM using LP core oxide
  • IO supply voltage: 1.8 V using the IO oxide.
  • Ultra Low k inter-level dielectric
  • 0.10µ metal pitch
  • Self-aligned silicided drain, source and gate
  • Poly and active resistors: Silicide protection over active areas for ESD protection
  • CMP for enhanced planarization (on STI, Contacts, Metals and vias).

FD-SOI Transistor (Courtesy: ST)

The 28nm FD-SOI standard-cells, IO cells and related IP are all from ST. The CORE cells Libraries include:

  • CORE_LL: Low Power LVT
  • CORE_LR: Low Power RVT
  • CLOCK (LL and LR): Buffer cells and the same for clock tree synthesis
  • PR: Place and route filler cells.

The IO cells Libraries include:

  • Digital
  • Analog
  • Flip-Chip bumps
  • ESD

You can find more details at the CMP website, or from the paper Dr. Torki presented at the 2012 SOI Conference.

So this represents a real opportunity.  Universities, often doing important research for industrial partners, have long known the value of using services like CMP’s. But with this latest ST-CMP-Soitec announcement, the fabless world can do more than kick the tires – they can take 28nm FD-SOI for a real test drive.

FD-SOI promises an extremely cost-effective, performance-enhanced, power-miser of a chip.  Wouldn’t you like to give it a try?