Tag Archive 22nm

ByAdele Hars

Quick Preview of (Great!) FD-SOI Design Tutorial Day (14 April ’17, Silicon Valley)

Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.

On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.

The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)

The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.  

(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)

Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.

FDSOI Short Overview and Advantages for Analog, RF and mmW Design – Andreia Cathelin, Fellow, STMicroelectronics, France

If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.

Summary slide from Professor Andreia Cathelin’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and ST)

She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology.  Then the focus  shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing.  For each category of circuits  (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass  filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.

Unique Circuit Topologies and Back-gate Biasing Scheme for RF, Millimeter Wave and Broadband Circuit Design in FDSOI Technologies – Sorin Voinigescu, Professor, University of Toronto, Canada.

Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics.  The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.

Summary slide from Professor Sorin Voinigescu’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and U. Toronto)

Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.

Design Strategies for ULV memories in 28nm FDS-SOI – Joachim Rodrigues, Professor, Lund University, Sweden

Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.

For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.

Summary slide from Professor Joachim Rodrigues’ course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Lund U.)

Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.

Energy-Efficient Processors in 28nm FDSOI – Bora Nikolic, Professor, UC Berkeley, USA

Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Summary slide from Professor Bora Nikolic’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and UC Berkeley)

Pushing the Envelope in Mixed-Signal Design Using FD-SOI – Boris Murmann, Professor, Stanford University, USA

If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.

Summary slide from Professor Boris Murmann’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Stanford U.)

Key Info About the FD-SOI Tutorial Day

  • Event: Designing with FD-SOI Technologies
  • Where: Samsung Semiconductor’s Auditorium “Palace”, San Jose, CA
  • When: April 14th, 2017, 8am to 3pm
  • Cost: $475
  • Organizer: SOI Industry Consortium
  • Pre-registration required – click here to sign up on the SOI Consortium website.

 

ByAdele Hars

New Advanced NV Memory IP for FDSOI – Attopsemi Joins GF’s FDXcelerator Program

There’s a new memory IP specialist on board for the FDSOI ecosystem. Attopsemi Technology has joined GlobalFoundries’ FDXcelerator™ Partner Program (read the press release here). Attopsemi is ensuring that its scalable, non-volatile one-time programmable (OTP) memory IP is compatible with GF’s 22FDX® technology. Their leading-edge I-fuse™ OTP IP is a fuse-based OTP technology that can guarantee zero-program defect, and offers up to 100x reliability, 1/100 the cell size, and 1/10th the program current compared to traditional e-fuse technologies. This advanced OTP targets customers and designers working on harsh, demanding applications such as automotive, 3D IC, and IoT.

“Attopsemi’s new offering should benefit our 22FDX customers in all the key market segments we address, especially for IoT and processor intensive applications,” said Alain Mutricy, senior vice president of product management at GF. “Their commitment continues to demonstrate strong industry interest in GF’s FDXcelerator program and the 22FDX value proposition.”

ByAdele Hars

San Jose Symposium: It Was an Epic Day for FD-SOI – Now Dubbed “The Smart Path to Success” [Part 1 of 2]

The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).

Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.

So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!

Samsung – in 28FDS mass production

Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:

Samsung_FDSOI_productionstatus_SanJose16c

Samsung’s foundry began commercial production of 28nm FD-SOI in 1Q2016.

ST_FDSOI_analog_SanJose16c

At the San Jose symposium, ST showed once again the enormous advantages FD-SOI provides in analog design.

As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).

NXP – integration, differentiation and passion

Ron Martino gave a talk full of energy and passion entitled, “Smart Technology Choices and Leadership Application Processors,” (which you can download from the SOI Consortium website – click here).

If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.

As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.

In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:

(Courtesy: NXP and SOI Consortium)

(Courtesy: NXP and SOI Consortium)

For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”

Sony – GPS (with 1/10th the power!) now sampling

You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).

In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.

As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.

Analog Bits – Lowest Power SERDES IP

SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.

AnalogBits_FDSOI_Serdes_SanJose16

With the port to 28nm FD-SOI, Analog Bits now has the industry’s lowest power SERDES.

In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”

Stanford – FD-SOI for the Fog

Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.

So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.

~ ~ ~

*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.

ByGianni PRATA

Implementing ARM Cortex A-series in 22nm FD-SOI – GloFo tech webinar

GloFo_FDSOI_22FDX_ARMCortexA_webinarRegistration is open for GlobalFoundries’ technical webinar, “How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology” (click here to go to the registration page). The webinar will cover the optimal steps to successfully implement ARM® Cortex®-A Series* processors using 22FDXTM 22nm FD-SOI technology.

GF Design Enablement Fellow Dr. Joerg Winkler will address:

  • Differentiated features of 22FDX including body-bias
  • Digital implementation flow using the Cadence tool suite
  • Initial 22FDX power-performance-area (PPA) results of an ARM Cortex sub-module
  • Understanding implementation details and results

This webinar will take place April 26, 2016 at10:00 am Pacific Time.

BTW, GF’s already done quite a few 22FDX-related webinars and videos – click here to see the current list.

~ ~ ~

* Per ARM, “Cortex-A processors are specifically designed to execute complex functions and applications such as those required by consumer devices like smartphones and tablets. Their performance efficiency is also making them an increasingly popular choice for servers and enterprise applications where large core clusters can be combined for optimal solutions.”

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GlobalFoundries and Synopsys Streamline the Move to 22nm FD-SOI

By: Tamer Ragheb, Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys

It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT).

GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 1_Benefits of 22FDX body-biasing

Figure 1: Benefits of 22FDX body-biasing

The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 2_22FDX Body Bias Optimizes Performance and Power

Figure 2: 22FDX Body Bias Optimizes Performance and Power

In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include:

  • Improved electrostatic control of the transistor acts as a performance booster and enables lower VDD (i.e., lower power consumption) while reaching significant performance
  • Low variability and body-biasing capability that can achieve 0.4 volt operation
  • Complete RF enablement with ‘knobs’ to reduce RF power by up to 50 percent

Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs.

There are four application optimized extensions available with 22FDX (Fig. 3). These are:

  • 22FDX ULP- an ultra low-power extension that provides logic libraries and memory compilers that are optimized for 0.4 volt operation.
  • 22 FDX ULL- an ultra low-leakage extension that brings in an expanded device suite capable of achieving one pico-amp per micron leakage.
  • 22 FDX UHP- an ultra high-performance extension that leverages the overdrive capabilities and body-biasing features to maximize the performance of technologies in a turbo or a burst mode. It has high performance libraries and high speed interfaces and BEOL stacks optimized for competing architectures or applications.
  • 22 FDX RFA- an RF and analog extension that brings in full characterization and enablement for RF applications, including optimized RF layouts and P cells, BEOL passives, and IP for Bluetooth LE and WIFI applications.
GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 3_22FDX Platform and Extensions

Figure 3: 22FDX Platform and Extensions

GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications.

GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.

Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include:

  • Design Compiler® Graphical synthesis with IEEE 1801 (UPF) driven bias-aware multi-corner multi-mode (MCMM) optimization
  • Formality® formal verification with bias-aware equivalence checking
  • IC Compiler™ and IC Compiler II™ layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation
  • StarRC™  parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF)
  • PrimeTime® timing analysis and signoff including distributed multi-scenario analysis (DMSA) static timing and noise analysis, using AOCV and POCV technology
  • IC Validator In-Design physical verification

The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.

ByAdministrator

Great FD-SOI start for 2016: Samsung, GF, Renesas, NXP/Freescale, ST, Soitec

Just a month into 2016 and we already have a raft of FD-SOI news from Samsung, GlobalFoundries, NXP/Freescale, Renesas and more. And of course RF-SOI continues ever stronger.

logo_soiconsortiumHere’s a quick update of what we’ve been seeing, starting with news from the recent SOI Consortium forum in Tokyo. Many of the presentations are now available on the SOI Consortium website – but keep checking back for more.

 

Samsung: 28nm FD-SOI hits maturity, mass production starts 1Q2016

Yongjoo Jeon, Principal Engineer in SEC Foundry marketing, Samsung, gave a talk entitled, The industry’s first mass-produced FDSOI technology for the IoT era, with single design platform benefits.

Here are his key messages with respect to 28nm FD-SOI:

  • The technology, which was qualified in 2015, is now ready for mass production, with the first commercial production set for 1Q2016.
  • Yield levels are excellent.
  • There were 12 tape-outs in 2015 in connectivity, security, games, set-top boxes, application processors for consumer and automotive, plus CMOS image sensors (aka CIS — for an excellent explanation of why FD-SOI is right for CIS and why leaders in this arena are considering it, see Junko Yoshida’s recent EETimes piece here).
  • The 16 tape-outs planned so far for 2016 expand to a wider range of automotive apps, plus we see the first in IoT and wearables, MCUs and programmable devices.
  • A production PDK for a version of 28nm FD-SOI with RF integration will be available in 2Q16.
  • eNVM (embedded non-volatile memory) will be ready in 2018.

For other key Samsung slides showing data on their success in manufacturability, check out EETimes.

 

GlobalFoundries: RF-SOI for 5G, FD-SOI Customers Engaged

Subramani Kengeri, VP of Global Design Solutions at GlobalFoundries talked about their 22nm FD-SOI, in his presentation Enabling SoC Innovations with 22FDXTM. He indicated that they’ve got over 40 customers engaged on it. Key points they’re hitting on that make them bullish on their prospects include:

  • FinFET-like performance and energy efficiency at 28nm cost
  • Ultra-low power consumption with 0.4V operation
  • Maximum flexibility in power/performance trade-off with software-controlled body biasing
  • Integrated RF cuts RF power in half and means designers don’t need an extra RF chip.
  • They’ll reach high-volume production by the middle of 2017.

For more on how GF see 22FDX as very well-positioned for IoT, see their Foundry Files blog. There’s also a really good piece in EEJournal by Byron Moyer entitled, A Non-FinFET Path to 10 nm – GlobalFoundries’ FD-SOI Alternative.

GF is of course also a dominant RF-SOI player, as seen in RFSOI: Defining the RF-Digital Boundary for 5G by Peter Rabbeni, Sr. Director RF Product Marketing and Business Development, GlobalFoundries. The presentation, which is available on the SOI Consortium website, notes that, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results,” so that, “SOI holds great promise in delivering on the key requirements of 5G systems.” (For an overview of GF’s RF-SOI position, see RF-SOI is IoT’s Future, and the Future in Bright on their Foundry Files blog.)

 

Renesas: in FD-SOI production at 65nm this year

Shiro Kamohara, Chief Engineer, Renesas Electronics Corp., lead off the presentations with Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era.

A Nikkei article reported from the conference that Renesas will be in mass production of 65nm FD-SOI – which they call Silicon-on-Thin-Box, or SOTB – for IoT products this year. Renesas reports the move cuts power to a tenth of what they’d seen in bulk. You can see the original article in Japanese here or a translated version here.

 

Soitec: wafers ready for mass adoption

Soitec_SOIsourcingIn the presentation Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms, Soitec Sr. VP of Digital Electronics Group Christophe Maleville, Senior Vice President, Digital Electronics BU provided data on every conceivable aspect of SOI wafers for FD-SOI and RF-SOI. He explained adaptations in the company’s Smart CutTM manufacturing technology that achieve astonishing levels of uniformity and thickness – or rather, thinness! With new metrology, they can predict and protect against variability in devices. And they are now producing FD-SOI wafers for 28nm processes with uniformity of +/- 1 atomic layer.

 

ST: making the case

For analog/RF, RF/mmW and mixed-signal/high-speed designers, Andreia Cathelin, Senior Member of Technical Staff at STMicroelectronics explained how and why FD-SOI makes their lives easier. Her presentation, FDSOI Technology Advantages for Analog/RF and Mixed-Signal Designs drills down to the technical for these folks.

Pietro Maestri, ST’s RF Product Line Director presented ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration. (BTW, we had an excellent high-level article by ST when H9SOI_FEM was first announced, describing the challenges faced by designers of smartphone front-end modules (FEMs) and how their H9SOI_FEM solves them – read it here.)

For anyone wondering about the status of FD-SOI following the just-announced company reorganization, COO Jean-Marc Chery told EETimes’ Peter Clarke that they remain fully committed to the technology. As noted in the article (read the whole thing here), “Chery emphasized that, following the announcement of ST’s withdrawal from STB and home gateway markets and of a proposed redeployment of 600 engineers, the company is now focused on automotive and Internet of Things applications and that therefore FDSOI is a core manufacturing process. Indeed it could be argued that moving engineers familiar with FDSOI from the STB group into MCUs and automotive will help to proliferate the technology through the company.”

 

NXP/Freescale: Loving FD-SOI

In another recent EETimes article, Peter Clark reported from the NXP “Smarter World Tour” that the newly merged NXP-Freescale is very bullish on FD-SOI (see the full article here).

He cites Goeff Lees, the GM for the MCU part of the merged businesses, who especially likes 28nm FD-SOI for IoT and MCUs. Ticking off the reasons, he lists energy efficiency, cost, analog support, security, temperature control and lower leakage current. In fact, he says, “I believe all MCU vendors could move to FD-SOI.” Wow.

So stay tuned – here at ASN we’ve got contributions from NXP/Freescale, Synopsys, GlobalFoundries, Surecore and more at the top of the 2016 queue. Yes, it’s going to be a good year.

ByGianni PRATA

Mentor tools being qualified for GlobalFoundries’ 22nm FD-SOI process

Mentor Graphics is collaborating with GlobalFoundries on 22nm FD-SOI to qualify the Mentor® RTL to GDS platform for the current version of GlobalFoundries 22FDX™ platform reference flow. (Read the press release here.) This includes including Mentor’s RealTime Designer™ physical RTL synthesis solution and Olympus-SoC™ place & route system. In addition, Mentor and GF are working on the development of the Process Design Kit (PDK) for the 22FDX platform. The PDK includes support for the Mentor Calibre® platform, covering design rule checking (DRC), layout vs. schematic (LVS) and metal fill solutions for 22FDX. These solutions help mutual customers optimize their designs using the capability of 22FDX technology to manage the power, performance and leakage.

“We are collaborating closely with Mentor Graphics on enabling their products to help customers realize the benefits of the 22FDX platform,” said Pankaj Mayor, vice president of Business Development for GlobalFoundries. “The qualification of Mentor tools for implementation flows and design verification will help designers to achieve an optimal balance between power, performance and cost.”

The next release of the 22FDX PDK will put GF’s differentiated DFM capabilities into the hands of designers, says a Mentor spokesperson, ensuring delivery of high-quality designs and ensuring faster ramps to production.

ByAdministrator

Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed

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Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

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ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

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Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

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Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

ByGianni PRATA

Leti Develops 22nm FD-SOI Local-strain Techniques to boost performance and lower power consumption

CEA-Leti announced it has developed two techniques to induce local strain in FD-SOI processes for next-generation FD-SOI circuits that will produce more speed or lower power consumption and improved performance. (For more details, read the press release here.) Targeting the 22/20nm node, the local-strain solutions are dual-strained technologies: compressive SiGe for PFETs and tensile Si for NFETs. In addition to clearing the path to improved performance in FD-SOI technology, they preserve its excellent electrostatic integrity and its in situ performance tunability, due to back biasing.

The two techniques Leti developed can induce local stress as high as 1.6 GPa in the MOSFETs channel. Strained channels enable an increase in the on-state current of CMOS transistors. As a result, chips can deliver more speed at the same power, or reduce consumed power for longer battery life at the same performance. The first technique relies on strain transfer from a relaxed SiGe layer on top of SOI film. The second technique is closer to strain memorization methods and relies on the ability of the BOX to creep under high-temperature annealing.

“These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices, and further position the technology to be a vital part of the Internet of Things and electronics products of the future,” said Maud Vinet, head of Leti’s Advanced CMOS Laboratory.

ByGianni PRATA

Cadence tools enabled for GF 22FDX FD-SOI. Validated on ARM Cortex-A17. Reference flow available.

Cadence has announced that its digital and signoff tools are now enabled for the current version of the GLOBALFOUNDRIES® 22FDX™ platform reference flow (see press release here). GF has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of software-controlled body bias to manage power, performance and leakage needed to create next-generation chips for mainstream mobile, IoT and consumer apps. In addition, the ARM® Cortex®-A17 processor was used to validate the implementation flow with the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution.

Cadence collaborated with GF on the development of the PDK for the 22FDX platform. The Cadence digital implementation tools support the capability of forward and reverse body bias (FBB/RBB) to optimize the performance/power tradeoffs, implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules. The digital implementation tools also support double-patterning aware parasitic extraction (PEX) and design for manufacturing (DFM).

“The 22FDX reference flow can enable customers to achieve real-time tradeoff between static power, dynamic power and performance to create innovative products,” said Pankaj Mayor, GF Biz Dev VP.