Tag Archive 28nm

ByAdele Hars

Industry 1st and It’s on FD-SOI: ARM’s eMRAM Compiler IP for Samsung’s 28FDS

Per Arm, the industry’s first eMRAM compiler IP is now on Samsung’s 28nm FD-SOI technology. The announcement was made in a post by Kelvin Low, VP Marketing for ARM’s Physical Design Group (read it here). He said that ARM has successfully completed their first eMRAM IP test chip tapeout. The Arm eMRAM compiler IP will be available from 4Q 2018 for lead partners.

Samsung Foundry’s 28nm FD-SOI process technology is called 28FDS. eMRAM (which stands for embedded MagnetoResistive RAM) is a novel non-volatile memory (NVM) option positioned to replace incumbent NVM eFLASH, which has hit its limits in terms of speed, power, and scalability.

Arm’s new eMRAM compiler IP gives Samsung’s 28FDS customers the flexibility to scale their memory needs based on the complexity of various use-cases, explains Low. “What drives the cost-effectiveness of this compiler IP is that eMRAM can be integrated with as few as three additional masks, while eFlash requires greater than 12 additional masks at 40nm and below,” he says. “Also, the eMRAM compiler can generate instances to replace Flash, Electrically Erasable Programmable Read-Only Memory (EEPROM) and slow SRAM/data buffer memories with a single non-volatile fast memory – particularly suited for cost- and power- sensitive IoT applications.”

A key slide shown by Arm at the 2017 SOI Consortium’s Silicon Valley Symposium (Courtesy: Arm and the SOI Consortium)

At the SOI Consortium’s 2017 Silicon Valley Symposium, Arm said that they were stepping up their support of FD-SOI (read about that here) – and clearly they are! At that event, Arm VP Ron Moore gave a great presentation, which is freely available on our website: Low Power IP: Essential Ingredients for IoT Opportunities.

Samsung, btw, has been offering 28FDS for about three years now. (ASN did a 3-part interview with Kelvin Low back in 2015 when he was a senior director of marketing for Samsung Foundry. It’s still a useful read – you can get it here.) As of last fall, Samsung said it had taped out more than 40 products for various customers. And at the SOI Consortium’s 2018 Silicon Valley Symposium, Hong Hoa, SVP said they’d already taped out another 20 this year (read about that here).

Samsung says the write speed of their eMRAM is 1000x faster than eFlash. They actually announced the industry’s first eMRAM testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here). They also did an eMRAM test chip with NXP. (BTW, Samsung has a really nice video explaining their eMRAM offering – you can see it above or on YouTube here.)

As noted in ASN’s Silicon Valley 2018 symposium coverage, the basic PDK for the Samsung 18nm FD-SOI process (18FDS) will be available in September 2018, with full production slated for fall of 2019. It will deliver a 24% increase in performance, a 38% decrease in power, and a 35% decrease in area for logic. RF for the 18FDS platform will be ready by the end of this year, and eMRAM beginning in 2019.

ByAdele Hars

Dolphin Showcases New EDA Tool for FD-SOI – More THINGS2DO Results

Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin’s cutting-edge EDA tool for safe Power Regulation Networks implementation.

THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, >€120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design & development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology — read about that here.)

“Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.”

The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications.

Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity.

The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization.

Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation & activity control networks for best SoC PPA.

Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. “Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX,” Michel Depeyrot, Dolphin Integration’s Chairman, said at the time. “As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA.”

See the Dolphin Integration website for the full catalog of their IP, EDA and ASIC/SoC service offerings, including for GF’s 22FDX.

ByAdele Hars

Outstanding 28nm FD-SOI Chips Taped Out Through CMP

ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP Annual Meeting. Now posted and freely available, Performance of Recent Outstanding 28nm FD-SOI Circuits Taped Out Through CMP highlighted eight examples – though she told ASN that she had easily over 50 from which to choose.

CMP is a Multi-Project Wafer (MPW) service organization in ICs, Photonic ICs and MEMS. They’ve been organizing prototyping and low volume production in cooperation with foundries for over 37 years. In partnership with ST since 1994, in the fall of 2012 they opened access to MPW runs in the 28nm FD-SOI process. More than 180 tape-outs have been fabricated since then using the process.

As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.

Here’s a quick recap of what she presented (some of which she co-authored), followed by some other SOI-related updates from the CMP meeting.

8 (of Many) Great Chips

FD-SOI, said Dr. Cathelin, “…is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance.” In the first dozen slides of her presentation, she gave the technical details on the advantages of FD-SOI in  analog, RF/millimeter wave,  Analog/Mixed-Signal and digital design. If you’re a designer, you’ll want to check those out.

Then she ran through eight great chips – all manufactured by ST on 28nm FD-SOI through CMP’s MPW services. Here they are. (You can click on the illustrations to see them in full screen.)

1. A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI

(Courtesy: CMP, ST, ISEN)

This chip was presented at ESSCIRC ’16 by a team from ISEN Lille, Professors Andreas Kaiser and Antoine Frappé (you can get the complete paper by I.Sourikopoulos et al on IEEE Xplore – click here.) As noted in the abstract, “Delay controllability has always been the major concern for the reliable implementation of circuits whose purpose is timing.” By leveraging body biasing in FD-SOI, this novel low-power design architecture for 60GHz receivers enables very high bandwidth together with fine-grain wide range delay flexibility, for implementing Delay Feedback Equalizer techniques in the Intermediate Frequency (IF) reception path. The results are state-of-the-art: ultra wide range, linear control, fs/mV sensitivity and energy efficient controllable delay cells.

2. 28FD-SOI Distributed Oscillator at 134 GHz and 202GHz

(Courtesy: CMP, ST, ims)

Presented at RFIC ’17 by a team from the IMS Bordeaux lab, Professor Yann Deval and STMicroelectronics, this chip demonstrates the highest oscillation frequency attainable so far at the 28nm node, be it planar bulk or FD-SOI. (Click here to get the full paper by R. Guillaume et al from IEEE Xplore.) As noted in the abstract, solutions on silicon for mmW and sub-mmW applications have been demonstrated for high-speed wireless communications, compact medical and security imaging. The main challenges are for the signal generation at high frequencies, and this implementation demonstrates spectacular oscillation frequencies close to the transistor’s transition frequency (fT). In this chip, they used body bias tuning to optimize the phase noise, demonstrated very low on-wafer variability, and simulation methods that permit measurement prediction precision within 0.1%.

3. A 128 kb Single-Bitline 8.4 fJ/bit 90MHz at 0.3V 7T Sense-Amplifier-less SRAM in 28nm FD-SOI

(Courtesy: CMP, ST, Lund U.)

Extremely energy efficient SoCs are key for the IoT era – but SRAM gets very tricky at ultra-low voltages (ULV). Presented at ESSCIRC ’16 by B. Mohammadi et al (on IEEE Xplore here) from Professor Joachim Rodrigues’ team at the Lund University, this is a 128 kb ULV SRAM, based on a 7T bitcell. The minimum operating voltage VMIN is measured as just 240mV and the retention voltage is as low as 200mV. FD-SOI enabled them to overcome ULV performance and reliability challenges by letting the Lund U.-lead team selectively overdrive the bitline and wordline with a new single-cycle charge-pump. Plus they came up with a new scheme so it doesn’t need a sense amplifier, yet delivered 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access.

4. Matched Ultrasound Receiver in 28FDSOI

(Courtesy: CMP, ST, Stanford U.)

Presented at ISSCC ’17 (with an extended relative paper at JSSC ’17) by M-C Chen et al with Professor Boris Murmann’s team at Stanford, the full title of the paper about this chip is A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. (Click here to get it on IEEE Xplore.) It’s a a proof-of-concept for a big ultrasound receiver: a “pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging.” PA is “…an emerging medical imaging modality based on optical excitation and acoustic detection.” It’s used in studying cancer progression in clinical research, for example. As noted in the paper abstract, “The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation.” One of the (many) advantages of FD-SOI in this context is for front-end signal conditioning in each pixel. This unique type of pixel pitch-matched architecture implementation is possible only in a 28nm (or less) node of an FD-SOI technology, as it is matched with the pitch sizing needed for the ultrasound transducers in order to generate signals for a 3-D reading.

5. SleepTalker – 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC

(Courtesy: CMP, ST, UCL)

Presented at VLSI ’16 and JSSC ’17 by G. de Streel et al from Professor David Bol’s team at Université Catholique de Louvain la Neuve, the full title of the paper about this chip is SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping (get it on IEEE Xplore here). This chip tackles the IoT requirement for sensing functions that can operate in the ULV context. That means creating wireless sensor nodes (WSN) that can be powered on an energy harvesting power budget – and that’s a real challenge if you want to incorporate an RF component that can handle medium data rates (5-30 Mb/s) for vision or large distributed WSN networks. The energy efficiency has to be better than 100 pJ/b. To get there, the UCL-lead team used wide-range on-chip adaptive forward back biasing for “…threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. […] Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the transmitter (TX) alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.”

6. A 128×8 Massive MIMO Precoder-Detector in 28FDSOI

(Courtesy: CMP, ST, Lund U.)

This massive MIMO chip was presented at ISSCC ’17 by a team from Professors Liang Liu and Ove Edforss at the Lund University  in a paper entitled 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI (H. Prabhu, et al; get it from IEEEE Xplore here). While Massive MIMO (MaMi) will be needed for next-gen communications, it can’t be achieved by just scaling MIMO – that would be too costly in terms of flexibility, area and power. As noted in the Lund U. team’s intro, “Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.”

7. ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI

(Courtesy: CMP, ST, KU Leuven)

Today’s solutions for always-on visual recognition apps are an order of magnitude too power hungry for wearables. Running at 10’s to several 1OO’s of GOPS/W, they use classification algorithms called ConvNets, or Convolutional Neural Networks (CNN). The paper about this chip was presented at ISSCC ’17 by a team from professor Marian Verhelst at Katoliek Universiteit Leuven (B. Moons, et al, get it from IEEE Xplore here), and it changes everything. Leveraging FD-SOI and body-biasing, the KU Leuven team solved the power challenge with, “…the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.”

8. Fine-Grained AVS in 28nm FDSOI Processor SoC

(Courtesy: CMP, ST, UC Berkeley)

As we learned at SOI Consortium FD-SOI Tutorial Day in SiValley last year, Professor Borivoje “Bora” Nikolic of UC Berkeley is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI!) They presented the RISC-V chip here at ESSCIRC ’16 and JSSC ’17, in a paper entitled Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (B.Keller, et al, on IEEE Xplore here). As they noted in the intro, a major challenge for mobile and IoT devices is that their workloads are highly variable, but they operate under very tight power budgets. If you apply adaptive voltage scaling (AVS), you can improve energy efficiency by scaling the voltage to match the workload. But in the current gen of SoCs, the AVS timescales of hundreds of microseconds is too slow. The chip the Berkeley team presented brought that down to sub-microseconds by aggressively applying body-biasing throughout the chip, including to workload measurement circuits and integrated power management units. The result is “… extremely fine-grained (<1μs) adaptive voltage scaling for mobile devices.” (BTW, they expand on some of the details in another paper published in 2017.)  These design techniques are now taught at UC Berkeley, as this kind of implementation is the subject of a course in SoC design (including the RF part of transceivers); a first educational chip has already been taped-out and successfully measured. (BTW, Professor Nikolic will once again join Dr. Cathelin and other luminaries in teaching at the SOI Consortium’s FD-SOI Training Day in Silicon Valley, 27 April 2018 –  click here for sign-up information.)

More SOI Through CMP

At the meeting, CMP also made a presentation on all their MPW offerings – you can get it here. On ST’s SOI (in addition to 28nm FD-SOI, of course), that includes the new 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power (for automotive sensor interface ICs, 3D ultrasound, MEMS & micro-mirror drivers); and 130nm H9-SOI-FEM: Front-End Module (for radio receiver/transceiver, cellular, WiFi, and automotive keyless systems).

CMP also provides tutorials that are used by institutions across the globe. A new update to the tutorial, RTL to GDS Digital Design Flow in 28nm FD-SOI Process is now available – you can see the presentation they did about that here. (It now includes LVS and DRC steps with Mentor/Calibre or Cadence/PVS.) Other services, like the 2-day, hands-on THINGS2DO FD-SOI training days at the end of March are always fully booked almost immediately, but don’t hesitate to inquire, as they’ll be adding more.

For some more examples of 28nm FD-SOI chips run through CMP over the years, see their website pages on Examples of Manufactured ICs. There are also some nice examples on pages 21 and 23 of their most recent annual report.

For those in the photonics world, CMP has teamed up with Leti to offer Si-310 PHMP2M, a 200mm CMOS SOI platform. CMP is cooperating with Tyndall for the photonics packaging – see that presentation here.  Training kits and tutorials will be available in Q3 of this year.

And in partnership with MEMSCAP, CMP offers Multi-User MEMS Processes (aka MUMPs) for SOI-MEMS.

So lots of terrific SOI resources for CMP – check it out!

~ ~ ~

Note: special thanks to Andreia Cathelin of ST and Kholdoun Torki of CMP for their help on this piece.

ByAdele Hars

Quick Preview of (Great!) FD-SOI Design Tutorial Day (14 April ’17, Silicon Valley)

Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.

On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.

The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)

The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.  

(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)

Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.

FDSOI Short Overview and Advantages for Analog, RF and mmW Design – Andreia Cathelin, Fellow, STMicroelectronics, France

If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.

Summary slide from Professor Andreia Cathelin’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and ST)

She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology.  Then the focus  shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing.  For each category of circuits  (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass  filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.

Unique Circuit Topologies and Back-gate Biasing Scheme for RF, Millimeter Wave and Broadband Circuit Design in FDSOI Technologies – Sorin Voinigescu, Professor, University of Toronto, Canada.

Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics.  The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.

Summary slide from Professor Sorin Voinigescu’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and U. Toronto)

Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.

Design Strategies for ULV memories in 28nm FDS-SOI – Joachim Rodrigues, Professor, Lund University, Sweden

Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.

For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.

Summary slide from Professor Joachim Rodrigues’ course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Lund U.)

Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.

Energy-Efficient Processors in 28nm FDSOI – Bora Nikolic, Professor, UC Berkeley, USA

Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.

Summary slide from Professor Bora Nikolic’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and UC Berkeley)

Pushing the Envelope in Mixed-Signal Design Using FD-SOI – Boris Murmann, Professor, Stanford University, USA

If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.

Summary slide from Professor Boris Murmann’s course at the upcoming FDSOI Tutorial (Courtesy: SOI Consortium and Stanford U.)

Key Info About the FD-SOI Tutorial Day

  • Event: Designing with FD-SOI Technologies
  • Where: Samsung Semiconductor’s Auditorium “Palace”, San Jose, CA
  • When: April 14th, 2017, 8am to 3pm
  • Cost: $475
  • Organizer: SOI Industry Consortium
  • Pre-registration required – click here to sign up on the SOI Consortium website.

 

ByAdele Hars

NXP’s new i.MX 7ULP On 28nm FD-SOI – Yes! Industry’s Lowest Power General Purpose Applications Processor (part 1)

They’re calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It’s NXP’s new i.MX 7ULP general-purpose processor, and it’s on 28nm FD-SOI. They’ve got a nifty video summing it all up – you can watch it here.

NXP is first to market with a general-purpose processor on FD-SOI: the i.MX 7ULP. It’s got both ultra-low power consumption and rich graphics for battery powered applications. (Courtesy: NXP)

With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.

The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.

Hello, IoT!

The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.

With the i.MX 7ULP, NXP’s targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it’s designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)

The details

The i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It’s got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors.

(Courtesy: NXP)

NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.

Leveraging body biasing and more

NXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.

In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages:

  • Large dynamic gate and body biasing voltage range

  • Domain and subsystem optimization with custom standard cell library with mixed voltages

  • Low quiescent current (Iq) bias generators

  • Enhanced ADC performance with unique FD-SOI attributes

  • Fail Safe I/O for simplified low power system design

To that, add a note about security. As the chip’s fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it’s needed.

Samsung fabs, Verisilicon adds IP

Two other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP’s results.

“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”

NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.

“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”

So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.

— By Adele Hars, ASN Editor-in-Chief

ByAdele Hars

Part 2: NXP’s new i.MX 7ULP – More on Why It’s On 28nm FD-SOI

i.MX 7ULP (Courtesy: NXP)

As you learned in Part 1 of this article, NXP is calling its new i.MX 7ULP general-purpose processor, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” Now let’s get into a little more detail about why it’s on 28nm FD-SOI.

If you read NXP VP Ron Martino’s terrific, two-part ASN piece last year on designing the i.MX 7 and 8, you knew this was coming – and you know why they chose to put it on 28nm FD-SOI. (If you missed it then, be sure to read it here now.)

To recap briefly, Ron cited (then expanded upon – so really: read his piece!) the following points that made 28nm FD-SOI the right choice for NXP’s designers:

  • Cost: a move from 28nm HKMG to 14nm FinFET would have entailed up to a 50% cost increase.

  • Dynamic back-biasing: forward body-bias (FBB) improves performance, while reverse body-bias (RBB) reduces leakage (so effectively contributes to power savings). It’s available with FD-SOI (but not with FinFETs), and gets you a very large dynamic operating range.

  • Performance: because body-biasing can be applied dynamically, designers can use it to meet changing workload requirements on the fly. That gets them performance-on-demand to meet the bursty, high-performance needs of running Linux, graphical user interfaces, high-security technologies, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.

  • Power savings: FD-SOI lets you dramatically lower the supply voltage (Vdd) (so you’re pulling less power from your energy source) and still get good performance.

  • Analog integration: traditionally designers have used specialized techniques to deal with things like gain, matching, variability, noise, power dissipation, and resistance, but FD-SOI makes their job much easier and results in superior analog performance.

  • RF integration: FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example.

  • Environmental conditions: FD-SOI delivers good power-performance at very low voltages and in a wide range of temperatures.

  • Security: 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart. And FBB delivers the bursts of high performance many security features require.

  • Overall manufacturing risks: FD-SOI is a lower-risk solution. Foundry partner Samsung provided outstanding support, and very quickly reached excellent yield levels.

But in the end, ultra-low power consumption was biggest driver. Joe Yu, VP of low power MPUs at NXP had the following to say about the new i.MX 7ULP. “Power consumption is at the heart of every decision we made for our new applications processor design, which now makes it possible to achieve stunning visual displays and ultra-low power standby modes in a single processor. From the selection of the FD-SOI process and dual GPU architecture, to the heterogeneous processor architecture with independent power domains, every aspect of our new processor design is aimed at providing the best performance and user experience with unprecedented energy efficiency.”

Next up: i.MX 8 for automotive +

At Embedded World, NXP also presented the new i.MX 8X family – and yes, it’s also on 28nm FD-SOI. It’s the first i.MX offering to feature Error Correcting Code (ECC) on the DDR memory interface, combined with reduced soft-error-rate (SER) and increased latch-up immunity, to support industrial Safety Integrity Level 3 (SIL 3). NXP says that opens new opportunities for innovative industrial and automotive applications.

We’ll cover it in an upcoming ASN blog, so stay tuned!

— By Adele Hars, ASN Editor-in-Chief

ByAdele Hars

Samsung Adding eFlash and eMRAM Options to 28nm FD-SOI (EETimes)

Samsung is adding two embedded NVM (non-volatile memory) options to its 28nm FD-SOI line-up, Kelvin Low told EETimes‘ Peter Clark in a recent interview (read the whole piece here).

Low, who heads up marketing and bizdev for Samsung Foundry, indicated the following roll-out for 28nm FD-SOI:

  • eFlash – risk production by the end of 2017; volume in 2018
  • eMRAM (SST-MRAM) – risk production by the end of 2018; volume in 2019

 

ByAdele Hars

ST moving digital automotive to 28nm FD-SOI (EETimes)

FD-SOI is the default choice for digital in ST’s automotive and discrete group (ADG), Marco Monti, EVP of the business unit told EETimes’ Peter Clarke in a recent article (read it here). The next generation of ST’s most advanced microcontrollers (currently on 40nm bulk) will be on 28nm FD-SOI, he said. Monti also gave examples of other FD-SOI automotive chips ST is doing for partners, including chips for WiFi, satellite radio, telematics, entertainment and ADAS (advanced driver assistance systems). “FD-SOI is not just a manufacturing node for us. It’s a whole cluster of technologies for all things in the car,” Monti told Clarke.

ByGianni PRATA

Use 28nm FD-SOI, Samsung advises new customers and designers (SemiEngineering)

“We intend to focus all new engagements in design using 28nm FD-SOI,” Samsung Semi’s Kelvin Low told SemiEngineering’s Mark Lapedus in a recent article (read it here).

Low, who’s senior directory of the company’s foundry marketing says they’ll of course continue to support existing 28nm bulk customers, “But we think FD-SOI has enough benefits to attract new customers and designers.”

 

ByAdele Hars

San Jose Symposium: It Was an Epic Day for FD-SOI – Now Dubbed “The Smart Path to Success” [Part 1 of 2]

The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).

Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.

So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!

Samsung – in 28FDS mass production

Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:

Samsung_FDSOI_productionstatus_SanJose16c

Samsung’s foundry began commercial production of 28nm FD-SOI in 1Q2016.

ST_FDSOI_analog_SanJose16c

At the San Jose symposium, ST showed once again the enormous advantages FD-SOI provides in analog design.

As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).

NXP – integration, differentiation and passion

Ron Martino gave a talk full of energy and passion entitled, “Smart Technology Choices and Leadership Application Processors,” (which you can download from the SOI Consortium website – click here).

If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.

As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.

In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:

(Courtesy: NXP and SOI Consortium)

(Courtesy: NXP and SOI Consortium)

For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”

Sony – GPS (with 1/10th the power!) now sampling

You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).

In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.

As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.

Analog Bits – Lowest Power SERDES IP

SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.

AnalogBits_FDSOI_Serdes_SanJose16

With the port to 28nm FD-SOI, Analog Bits now has the industry’s lowest power SERDES.

In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”

Stanford – FD-SOI for the Fog

Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.

So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.

~ ~ ~

*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.