Tag Archive 3D


NXP, Qualcomm, Skyworks to Keynote IoT Theme in Upcoming IEEE SOI-3D-SubVt (S3S) Conference (San Francisco, Oct.’16) – Late News Submissions Open, Advance Program Available

IEEE S3S Conference

10-13 October 2016

Hyatt Regency San Francisco Airport

IEEE SOI3DSubthreshold Microelectronics Technology Unified Conference

Theme: Energy Efficient Technology for the Internet of Things

Late News submissions open and Advance Program available

S3SconflogoThe IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.

This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.

We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.

Our Keynote speakers are decision-makers from major industries:

  • Nick Yu, VP, Qualcomm, will explain why “The Homogeneous architecture is a dead fairy tale”
  • Ron Martino, VP, NXP, will present “Advanced Innovation and Requirements for future Smart, Secure and Connected Applications”
  • Peter Gammel, CTO, Skyworks, will describe “RF front end requirements and roadmaps for the IoT”

Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.

Applications will be illustrated in our session dedicated to SOI circuit implementations.

ieee_logo_mb_taglineYou can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.EDS-Logo-Reflex-Blue-e1435737971222

And you still have time to actively participate by submitting a late news paper before August 31st.

The conference has a long tradition of allying technical and social activities.

This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.

Hyatt Regency San Francisco Airport

Hyatt Regency San Francisco Airport

With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.

Deadline for Late News submissions is

August 31st, 2016


For further information, please visit our website at s3sconference.org or contact the conference manager:

Joyce Lloyd • 6930 De Celis Pl., #36

Van Nuys, CA 91406

T 818.795.3768 • F 818.855.8392 • E manager@s3sconference.org

ByGianni PRATA

Reminder re: top SOI Conference – IEEE S3S ’16 (SOI/3D/SubVt) CFP deadline April 15th. Keynotes: NXP, Skyworks, Qualcomm

S3SconflogoDon’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.

As of this writing, the following keynote speakers have been confirmed:

  • Ron Martino, NXP : “Advanced Innovation and Requirements for Future Smart, Secure and Connected Applications”
  • Peter Gammel, Skyworks : “RF front end requirements and roadmaps for the IoT”
  • Nick Yu, Qualcomm : topic TBAieee_logo_mb_tagline

Invited speakers include:

  • Jamie Schaffer, GlobalFoundries : topic TBA
  • Philippe Flatresse, ST Microelectronics : “Body bias and FDSOI for Automotive”
  • Akram Salman, Texas Instruments : “ESD for advanced digital and analog technologies”
  • Xavier Garros, CEA-Leti : “Reliability of FDSOI”

As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.

Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :

  • SOI
  • 3D Integration
  • Subthreshold MicroelectronicsEDS-Logo-Reflex-Blue-e1435737971222

For current information on the conference visit the S3S website at: http://s3sconference.org/

LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.

ByGianni PRATA

IEEE S3S, Top SOI/3D/SubVt Conference, Issues Call for Papers. Theme: Energy Efficient Tech for IoT. (Best Student Paper wins $1000)

ieee_logo_mb_taglineEDS Logo PMS3015_revu_smallThe IEEE S3S (SOI/3D/SubVt) has issued its call for papers for the 2016 conference (click here for details). The theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”. This industry-wide event gathers together widely known experts, contributed papers and invited talks focused on SOI Technology, Low-Voltage Devices/Circuits/Architectures, and 3D Integration. In addition to over 100 contributed and invited papers, the conference will feature prestigious Keynotes and a Hot Topics session.

logo_soiconsortiumFor the first time, the Conference will include two Tutorials free-of-charge with Conference registration: one on FD-SOI Circuit Design and another on Technologies for Monolithic 3D Integration. A full-day short course addresses Energy Efficient Computing and Communications including RF circuit technology.

The paper submission deadline is the 15th of April 2016. As always, there will be a Best Paper Award and a Best Student Paper Award. But for the first time, the Best Student Paper Award includes a $1,000 prize from one of the conference’s industry sponsors.

The papers presented here give industry an excellent window on what’s coming next. For example, work demonstrating a viable integration path for stacked nanowires that was first presented in a Leti paper at the 2015 S3S Conference was awarded the Paul Rappaport IEEE Prize two months later at IEDM 2015.

S3S is a great conference – don’t miss it.

ByGianni PRATA

Don’t miss EuroSOI-ULIS, 25-27 January 2016 in Vienna. Call for papers still open.

logo_eurosoi_ulisThe 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, aka EUROSOI-ULIS 2016 will be taking place January 25-27, 2016 in Vienna, Austria. The event will be hosted by the Institute for Microelectronics, TU Wien. The focus of the sessions is on SOI technology and advanced nanoscale devices. The organizing committee invites active participation and submission of high quality papers (the Paper Submission deadline has been extended until Dec. 14 2015).
EuroSOI is a conference that’s been going on for decades. Many of the leading edge SOI technologies making headlines today were first presented here. This year’s conference features talks by top researchers from Europe and Japan, and a plenary talk from ON Semi entitled SOI technology for advanced power management: context and trends.
Click here for conference registration details.

Advanced substrates for 3D and other new markets drive new fab inspection equipment – interview with Altatech GM

New approaches in chipmaking and fast-evolving specialty markets are driving the need for new equipment on the fab floor. 3D chips (be they stacked or bonded), MEMS, lighting, power – they’re all leveraging wafer substrates in new ways. Altatech, the equipment division of SOI-wafer leader Soitec, has just announced new inspection equipment for foundry and IDM customers fabbing 3D and other chips. ASN talks to Jean-Luc Delcarri, Altatech general manager, about the company and its recent announcements.

Advanced Substrate News (ASN): Can you tell us briefly about the company and the markets it serves?


Jean-Luc Delcarri, Altatech general manager

Jean-Luc Delcarri (JLD): Altatech makes specialty equipment for the fab floor. We have two main areas of deep expertise: one is in defect inspection, and the other is in CVD* technologies for semiconductor, LEDs, MEMS and photovoltaic devices. I founded the company in 2004, and then in 2012 we became a subsidiary of SOI wafer leader, Soitec.

ASN: At Semicon Europa 2015, you announced “…a new, high-speed inspection system for ultra-thin, transparent and bonded substrates inspection for 3D applications in power, MEMS and mobile technologies.” What’s driving that market?

JLP: Yes, at Semicon we announced the Eclipse TS, which is a unique, high-reliability and easy-to-implement inspection system solution that’s now ready for mass production.

You’ve got the need for these advanced substrates that’s being driven by really rapidly growing markets in automotive, industrial power and mobile electronics. We’ve been working quietly on this tool for years, and now the Eclipse TS has been qualified for volume manufacturing at a leading-edge semiconductor manufacturer, so we’re really excited about it.


Altatech’s Eclipse TS, a high-speed inspection system for ultra-thin substrates in 3D applications.

ASN: What makes the Eclipse TS different from other inspection sytems?

JLP: When you’re looking for defects on these advanced wafer solutions, you have to do much more than scan the top: you need to inspect the front side, the back side and the edge of very thin wafers – and you have to do it without touching them. Our ability to do all this makes us totally unique on the market: we have built this tool on a strong IP portfolio.

So with the Eclipse TS, you have a high-speed inspection system that can measure very thin and stacked wafers down to 50 microns, as well as Taiko rings, stacked substrates and silicon-on-glass wafers. Plus we can do the front-side, back-side and edge inspection in one pass with no back-side contact.

In today’s 3D technologies, substrates undergo grinding, stacking and gluing, so you can end up with wafers with a very high bow, or  wafers with a warp of up to 6 mm. We can handle those wafers. In fact, the Eclipse system can monitor these sorts of processes. The inspection occurs without any contact on the active surface, and at a throughout of more than 90 wafers per hour for 300-mm substrates.

We’re of course compliant with the latest automation standards, so the system can be fully integrated into the line, and provide comprehensive reporting for defects classification and yield maps.

Our full Altatech Eclipse series covers advanced metrology and holistic inspection systems. That means we can detect, count and bin defects during the wafer manufacturing process as well as do continuous outgoing wafer-quality inspection. So the quality of both the wafer-surface and edge is ensured. We also have proprietary Eclipse sub-modules that detect specific sorts of particles and defects of interest for both patterned or unpatterned wafers.

All that puts Altatech in a leading position in what is a very large market opportunity.


Altatech’s AltaCVD 3D Memory Cell deposits the ultra-thin semiconductor films used in high-density, low-power memory chips 10 times faster than conventional ALD systems.

ASN: You also make CVD – deposition – equipment. Can you tell us a little about that, and what’s driving those markets?

JLP: Sure. Last year we introduced the AltaCVD 3D Memory Cell™, which is the newest member of our AltaCVD product line. This is used for depositing ultra-thin semiconductor films when you’re manufacturing the high-density, low-power memory chips used throughout mobile electronics. Our new system does atomic-layer deposition 10 times faster than conventional ALD** systems, which is of course huge when you’re manufacturing advanced memories where you need to run in very high-volume production with extreme cost efficiency.

In the new 3D device architectures for mobile apps, our customers are looking to really increase memory capacity and boost performance. And to do this, they need very advanced material deposition to create atomic-layer films with high uniformity – you really are at the atomic level of control here. The AltaCVD 3D Memory Cell deposits layers of chalcogenide*** materials by using a combination of precursors, which is very leading edge.

So with our tool you can use conventional gaseous or solid precursors, but we also have a patented pulsed technology, which means you can also use advanced CVD precursors that are available only in liquid form. This is remarkable versatility: it allows us to achieve exceptional step coverage over features with very high aspect ratios – that’s a key performance requirement when you’re talking about vertical integration high-density memory circuits.

You can also use it for advanced pre-treatment of semiconductor surfaces (which improves circuit functionality), as well as post-treatment of surfaces (which enhances electrical performance).

Because it’s used in everything from research to high-volume manufacturing, it can process 200-mm or 300-mm substrates, and uses a single-wafer, multi-chamber architecture. One of our key customers demonstrated it last year. We’re now selling production units, and we’re pleased to say it’s been very successful.

ASN: Do you have other products in the pipeline?

JLP: Next up we have a new solution for high aspect ratio 3D copper deposition. The system, which is called RUBY, can deposit a barrier layer of titanium nitride or tantalum nitride with almost 100% step coverage on an aspect ratio higher than 10:1. This is followed by deposition of a copper seed layer with similar performance. Combined with a proprietary copper cleaning process, it will be able to meet the growing challenge of copper metallization in MEMS and semiconductor 3D integration. We’ll release it as soon as we’ve completed our product milestones for reliability and performance.

ASN: Where do you see the highest-growth areas?

JLP: We’ve developed the right technology for the right time in a number of key markets, so we’re really well-positioned to answer the needs of a number of high-growth markets. The move to 450mm wafers is something we’re ready for, which will probably happen first in advanced memories. But in the meantime we also see significant activity in MEMS, RF, high power and LEDs. We’re winning customers in China who are looking to be leaders in these markets. All in all, much of the future of the phone in your pocket depends on what we can help our customers do in high-volume and cost-effectively on the fab floor – so it’s a very exciting time to be in this business.

~ ~ ~

*CVD=chemical vapor deposition

**ALD=atomic layer deposition

*** chalcogenides include sulphides, selenides, and tellurides

ByFanny Rodriguez

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.


Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:


The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.


IEEE SOI-3D-Subthreshold Conference (S3S, Oct. Sonoma, CA) Welcoming Papers til mid-May

Bacchus Entry

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) will be held in Sonoma Valley, CA 5-8 October 2015. (Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015.

Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than in 2013.

EDS Logo PMS3015_revu_smallThe conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.

sponsor-ieeeWhile paper submissions are still accepted, the 2015 edition of the conference already promises a rich content of high-level presentations.


Geoffrey Yeap from Qualcomm will open the plenary session. He will give us a broad overview of the Ultra-Low Power SoC technologies.

Invited speakers from major industries (Intel, On Semiconductor, ST, Freescale, NXP, Soitec and more) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration.

There will be two short courses again this year: One on SOI Application, and the other on Monolithic 3D.

Welcome to Doubletree Hotel Sonoma Wine Country

(Photo courtesy: The DoubleTree by Hilton Sonoma Wine Country)

There will also be a class on Logic devices for 28nm and beyond as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.

The Hot Topics session will, this year, be about Ultra-Low Power.

During the Rump session we will debate about the What does IoT mean for semiconductor technology?

Scope of the conference:

The Committee will review papers submitted by May 18 in the three following focus areas of the conference:


Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.


Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.


3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.

Students are encouraged to submit papers and compete for the Best Student paper awards. Details on paper submission are given on the call for papers webpage.

Important dates:

Paper submission deadline: 18 May, 2015

Notification of acceptance: 07 June, 2015

Short course date: 5 October, 2015

Conference date: 5 – 8 October, 2015

More details are available on the S3S website.

ByGianni PRATA

Interview (Leti): How a new platform helps designers get the most out of FD-SOI for IoT, ULP

CEA-Leti Clean Room (© Pierre Jayet)

CEA-Leti Clean Room (© Pierre Jayet)

A driving force in FD-SOI, Leti recently announced a service called Silicon Impulse®, a new FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume. Olivier Thomas, who’s in charge of the program and Ali Erdengiz, who’s Business Development Manager for Leti explain how it works.


Advanced Substrate News (ASN): What exactly is Silicon Impulse? What services does it offer?


Olivier THOMAS is the project leader of Silicon Impulse for Leti.

Olivier Thomas (OT): Silicon Impulse provides design services from emulation to test program development and qualification (emulation, advanced building blocks and IPs access, full control design flow, industrial MPW, packaging and board, test and qualification).

So you can consider Silicon Impulse as a silicon enablement and development platform: a unique IC prototype development and production hand-off partner for companies in need of the latest low-power semiconductor technologies and heterogeneous integration solutions (FD-SOI, BEOL NVM, MEMS, 3D…). We work with a strong network of industrial partners and offer a single entry point along product maturation.

Silicon Impulse leverages Leti’s* and List’s** expertise as well as top industrial partners belonging to a global network of experts in analog, RF, digital and memory design, as well as hardware/software-integrated solutions.

CEA-Leti Clean Room (©Pierre Jayet)


In a nutshell, Silicon Impulse offers:

  • a pool of expertise from device to system
  • access to world-class, leading-edge technologies
  • regularly scheduled industrial multi-project wafer (MPW) shuttles
  • access to a proven supply chain
  • customized collaboration to fit partner needs

[Editor’s note: Click here to download the Silicon Impulse brochure.]

ASN: Who is it aimed at?

Ali Erdengiz is Business Development Manager for Leti/List.

Ali Erdengiz is Business Development Manager for Leti/List.

Ali Erdengiz (AE): We saw that the increasing cost of leading semiconductor technologies, the level of expertise, tools and resources required to develop innovative products using such advanced processes can make it really challenging for new entrants (product and solution innovators). So CEA Leti created the Silicon Impulse initiative to help innovative companies to get their projects off the ground. We provide an advanced silicon development platform, help them develop their IC and/or subsystem and then hand it off to the production supply chain.

We did this because we see that today’s new markets are driven by a variety of applications and new players – it’s not just the big players scaling for PCs and mobiles anymore. IoT is a great opportunity for the emergence of innovations and ideas from new entrants. We’ve been getting more and more requests from partners looking to integrate the advanced technologies developed in Leti such as BEOL NVM and MEMS. They’re thinking outside of the box, so they are also interested in using 28nm FD-SOI while requesting advanced features and specific performance at low-voltage. Leti has always done technology research. Now with Silicon Impulse we provide a new service in collaboration with other industrial partners to help companies evaluate, design, prototype, and launch their products.

ASN: If FD-SOI design is so easy and so close to what designers have done in bulk, why do they need this sort of service?

Leti and List have a long history of launching innovation, as seen here in the CEA-Leti Showroom (©Pierre Jayet)


OT: Indeed, one can easily migrate from bulk to FD-SOI and benefit immediately from its low power/low leakage characteristics. However, we’ve seen that many of the companies that port their circuits to FD-SOI don’t exploit the full potential of the technology. Silicon Impulse leverages Leti’s strong expertise and experience in FD-SOI technology from device to Digital/RF modeling and advanced design solutions and maximizes the gains of the technology. Our competence center provides its industrial partners with quick access to information, know-how and silicon proven advanced design and architecture solutions to efficiently manage performance, power consumption and process variability. Here are some examples: PVT sensors, timing fault tracking, control theory module (i.e. algorithm to figure out the optimum energy point), fast feedback loop on the top of tailored charge pump and other blocks to back bias efficiently.

In addition, Leti’s Silicon Impulse’s expertise is not limited to designing FD-SOI IC’s. Leti brings a wealth of system knowledge and application know-how from device technology through embedded software that ensures full success and differentiation for its partners’ projects.

ASN: Why should designers consider FD-SOI?

OT: The 28nm/22nm technology nodes are seen as a long-lived technology node and a sweet spot for performance, power and cost. FD-SOI is optimized for low-voltage, low-power applications that can nevertheless need high performance.

For digital design, the extended range (+/-2V) of back biasing along with PVT sensors, timing fault tracking, theory control module and fast feedback loops controlling the back bias enable efficient process compensation and energy optimization for a wide range of applications (E. Beigne et al. ISSCC’14).

For SRAM design, the un-doped planar technology offers a large portfolio of SRAM bit-cells (High-density, Low power, High-performance) enabling very good performance over a wide voltage range. The Single P-Well bit-cell architecture combined with a wide back bias range enables both low operating voltage and fast access time. In sleep mode, the back bias can be set to minimize the bit-cell standby leakage current and the data retention voltage (O. Thomas et al. IEDM’14).

For RF design, one key aspect shown in the paper presented at ISSCC 15 is the continuous re-configurability through VT adjustment by the back-gate. The Power Amplifier discussed in the paper can pass from a high-linearity/high-efficiency state to a high power state by continuous linear tuning; something that cannot be done in other technologies. At the same time, the 28 FD-SOI allows designers reach much higher FT/Fmax than bulk. The result is higher available gain in mm Wave (as shown in our example at 60GHz). This approach drastically reduces the PA’s power consumption in 90% of the use cases, thus enabling WiGig for example in mobile applications.

ASN: What are the logistics for getting started?

OT, AE: Silicon Impulse can help innovators with their projects from concept through production hand-off. To get started on a project, we do a business review to determine where and how Silicon Impulse can contribute. We can provide architectural advice and shape the product from a very high level, develop a feasibility study and make recommendations as to how to implement the system. Leti and its partners can provide unique IP and/or technology components such as foundation IP or more complex system level IP blocks, RF, MEMS, 3D components and any other advanced technology to shape a truly unique and advanced yet manufacturable product. Another layer of contribution of Leti, List would be in providing embedded software to complete the whole product. So Silicon Impulse’s involvement can be limited to architectural consulting or extended to developing and delivering the whole system or anything in between.

Construction of an extension to the Minatec campus is now underway, which will be the new home to Leti’s Silicon Impulse® service. (Architect’s rendering of the IC Design Competence Center building, north view shown here, ©Futur A Architectes)


ASN: You’re running multi-project wafer (MPW) shuttles – can you tell us more about that?

OT: Leti offers its MPW shuttles to open the doors to a wider set of users and projects (some of whom might not have access to or be ready yet for full service foundries). An MPW shuttle serves two main purposes:

  • Enable innovators to test their ideas, especially mixed-signal, analog or RF or any new IP that would require silicon validation in FD-SOI
  • Provide an affordable platform for startups and other small companies to build their prototypes and run small volumes until they can raise enough funds and/or demonstrate market traction to build their own mask set.

However, we’ll also be making an announcement in the near future with details of schedules for planned MPW shuttles with our industrial partners.

ASN: How long will it take to get to a working design?

AE: This is project dependent, but leveraging Leti’s experience and already proven IPs and methodologies it is likely that our partners will develop a successful design even faster than if they did it on their own regardless of whether they used FD-SOI or bulk. Using FD-SOI for digital design targeting low power without compromising performance will certainly get you there faster than using bulk. In addition, the intrinsic characteristics of FD-SOI and much better control of device variability will accelerate analog and RF design and reduce time to market.

ASN: Will the design then be transferable to a full-service, high-volume fab?

OT: The purpose of Silicon Impulse is to ease IC prototype development and enable/accelerate production ramp-up. Silicon Impulse completes the Leti R&D offering by transferring the technology into a manufacturable product. The production is then handed off to a full service fab and/or supply chain partner. We’ll begin announcing the names of these partners shortly.

For information on contacting Leti’s Silicon Impulse service, click here.

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Olivier THOMAS is the project leader of Silicon Impulse for Leti. He received the M.S. Electrical Engineering degree from ISEN in 2001 and the Ph.D. degree from the Telecom ParisTech in 2004. He joined the CEA-LETI Laboratory in the Center for Innovation in Micro & Nanaotechnology (MINATEC), Grenoble, France in 2005. From 2005 to 2014 his research work was focused on advanced low-power digital and memory design in leading edge SOI technologies (PDSOI, FDSOI) and heterogeneous technology co-integration (ReRAM, 3DVLSI). From 2010 to 2012, he was a visiting researcher at Berkeley Wireless Research Center (BWRC) of University of California at Berkeley. He worked on methodologies to characterize on large-scale static/dynamic SRAM performances. From 2012 to 2014, he launched and led the Leti’s advanced memory design activity. He is author or co-author of 75 articles in international refereed journals and conferences and 25 patents.

Ali Erdengiz is Business Development Manager for Leti/List. He has spent 20 years in Silicon Valley and held various engineering, marketing, product and business unit management functions at companies such as ST Micro, National Semiconductor, Fujitsu, Altera, Abound Logic and eSilicon. Ali holds a BSEE from ESME, an MSEE from Université Parix XI and an MBA from San Jose State University.

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Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

*CEA-Leti is a research-and-technology organization with a large and word class expertise from device through system integration. It specializes in nanotechnologies and their applications. NEMS and MEMS are also at the core of its activities. Leti is capable of not only developing semiconductor devices (analog, mixed-signal, RF, digital, MEMS) but also integrating them into subsystems using PCB, MCM, 2.5D and 3D technologies as well as developing embedded and application software to deliver full system level solutions.


**A sister organization to CEA-Leti, CEA-List conducts R&D in fields that create value for the economy and society. As such, the primary mission is to give businesses the tools they need to turn their innovative ideas into marketable products.



2015 – Turning the Tables for FD-SOI, RF-SOI and More

If current momentum is any indication, 2015 will be the year the tables turn in favor of FD-SOI designs (with a big shout-out to IoT).  The RF-SOI juggernaut will continue cutting an enormous swath through the mobile market.   Attention to the exciting possibilities of monolithic 3D (M3D) technology (like Leti’s “CoolCube”) will continue to grow, and SOI-based power apps will continue their strong drive into automotive and other markets. More exciting apps in MEMS, NEMS, photonics and sensors will come over the horizon. Players in China will join the upper echelons of SOI-based design and manufacturing. And you’ll read about it all here in ASN.

Riding on the success of the Shanghai RF-SOI and FD-SOI workshops last fall, 2015’s getting off to a great start with free FD-SOI/RF-SOI workshops in Tokyo (23 January, just after ASP-DAC) and San Francisco (27 February just after ISSCC – click here to register).


As of this writing, we just got the news that registrations for the Tokyo workshop had far exceeded expectations. There’s lots of excitement surrounding the prospect of the Sony presentation on their FD-SOI design experience, which we hear will be excellent.  Samsung is slotted for a full half-hour presentation on their FD-SOI offering.  There’ll be press coverage, and here at ASN we’ll be sure to bring you the full wrap-up.

ST and partners Leti, Soitec and IBM have long been leading the FD-SOI charge.  At IEDM ’14 last month, they showed us how the roadmap extends to 10nm. (If you missed that, click here to read about it.) Now we’re looking forward to hearing about those 28nm FD-SOI chips hitting the markets this year.

And with Samsung on board now for ST’s FD-SOI process, things are looking ever more interesting. Earlier this month, Samsung’s Kelvin Low (Senior Director, Foundry Marketing) noted in his blog that, “28FDSOI comes with a complete design ecosystem” (PDK, Library, IP, and DFM – click here to read about it). “Customers who are looking to manufacture faster, cooler, and simpler devices at 28nm should look no further – 28FDSOI is the ideal choice,” he concluded.

Kelvin will also be presenting in the who’s who line-up at the prestigious Electronic Design Process Symposium (aka EDPS, coming up at Monterey Beach, CA in April – click here for more info.) In fact, the lead session of this year’s EDPS is entitled “FinFET vs. FDSOI – Which is the Right One for Your Design?” We look forward to some lively discussions there!

We heard a lot of promising developments at the Semicon Europa Low-Power Conference in the fall (if you missed that ASN coverage, click here to read it).  Although they’ve been quiet in the press, at the conference it was clear that GloFo foundry guys are chomping at the bit.  To recap, Manfred Horstmann, Director of Products & Integration for GlobalFoundries in Dresden said that FD-SOI would be their focus for the next few years. They’re also calling it ET-SOI (for extremely thin), and he said it’s the right solution for SOCs, especially with back biasing. Plus, it’s good for the fab because they can leverage their existing tool park. Asked if they have customers lined up, he said yes – so we’ll look forward to hearing about them this year.

And finally, this April we’ll be celebrating the 10th anniversary of ASN. It’s hard to believe 10 years have sped by since we published our first edition. Thank you for your continued support.

With best wishes for a safe, happy, healthy and prosperous 2015.

ByGianni PRATA

IEEE SOI-3D-Substhreshold (S3S) Conference Issues Call for Papers

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) has issued the 2015 Call for Papers.

Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco, October 5-8. This industry-wide event will gather together widely known experts, contributed papers and invited talks on three main topics: SOI technology, subthreshold architectures with associated designs and 3D integration. With its 40-year history, the SOI segment continues as world’s premier conference to present and discuss state of the art SOI technical papers.

The 2014 edition was a great success (click here to read about it).  The deadline for submissions for the 2015 conference is April 15, 2015 (click here for complete submission information).