Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.
On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.
The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)
The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.
(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)
Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.
If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.
She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology. Then the focus shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing. For each category of circuits (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.
Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics. The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.
Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.
Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.
For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.
Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.
Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.
If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.
GlobalFoundries has announced availability of its 45nm RF-SOI technology (read the press release here). Dubbed 45RFSOI, the company says it’s the first 300mm RF solution for next-gen mmWave beamforming applications in future 5G base stations and smart phones.
The technology supports mmWave spectrum operation from 24GHz to 100GHz band, 5x more than 4G operating frequencies.
Skyworks’ CTO Peter Gammel says that the 45RFSOI process, “…is enabling Skyworks to create RF solutions that will revolutionize emerging 5G markets and further advance the deployment of highly integrated RF front-ends for evolving mmWave applications.”
The news was quickly picked up by publications across the industry, with EETimes noting that RFSOI has been a big GF success story.
Production will be at the company’s East Fishkill fab. The PDKs are available now.
The 45RFSOI news follows hard on the heels of GF’s announcement a few days prior that the company is teaming up to build a fab offering 22nm FD-SOI in western China, that it’s expanding its Dresden FD-SOI capability by 40 percent, and that it’s adding new RF-SOI capabilities to its fab in Singapore.
GlobalFoundries is a member of the SOI Industry Consortium.
12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).
The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”
Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”
The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”
GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.
The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.
“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”
Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).
Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.
Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.
Initial FDXcelerator Partners have committed a set of key offerings to the program, including:
Additional FDXcelerator members will be announced in the following months.
Three of the world’s More-than-Moore and SOI technology development powerhouses have signed a comprehensive agreement for ongoing collaboration and cooperation in developing new technologies for the emerging IoT market. SITRI of Shanghai, and CEA-Leti and Minatec of Grenoble will work together to accelerate the adoption of their latest technologies and create a global innovation ecosystem for emerging IoT applications (read the press release here).
The framework agreement broadly covers all joint areas of research at SITRI and Leti, including MEMS and sensors, 5G RF front ends, ultra-low power computing and communication, RF-SOI and FD-SOI.
In fact, the trio cites SOI as a key technology in the development of both Moore’s Law and “More than Moore” solutions for the IC industry, as it brings cost, performance, power and integration advantages to the areas of ICs, RF, MEMS, and communications.
“We are confident that this collaboration will be positive for China’s electronics industry, as well as for the Grenoble region’s growing SOI technology ecosystem,” said MINATEC Director Jean-Charles Guibert.
Adds Marie-Noëlle Semeria, CEO of Leti, “Through this partnership, SITRI, MINATEC, CEA-Leti and the entire ecosystem will be able to promote and extend this ecosystem to SOI partners worldwide, and provide SOI solutions to the emerging Chinese IoT market.”
“MINATEC is a world-class international innovation center that fosters a wide range of leading-edge IoT technology research and development which is home to CEA-Leti, the renowned international research institute in microelectronics,” said Charles Yang, President of SITRI. “Through this agreement and SITRI’s established platform for ‘More than Moore’ commercialization, we can accelerate the adoption of these latest technologies and create a global innovation ecosystem for emerging IoT applications.”
Just a month into 2016 and we already have a raft of FD-SOI news from Samsung, GlobalFoundries, NXP/Freescale, Renesas and more. And of course RF-SOI continues ever stronger.
Here’s a quick update of what we’ve been seeing, starting with news from the recent SOI Consortium forum in Tokyo. Many of the presentations are now available on the SOI Consortium website – but keep checking back for more.
Samsung: 28nm FD-SOI hits maturity, mass production starts 1Q2016
Yongjoo Jeon, Principal Engineer in SEC Foundry marketing, Samsung, gave a talk entitled, The industry’s first mass-produced FDSOI technology for the IoT era, with single design platform benefits.
Here are his key messages with respect to 28nm FD-SOI:
For other key Samsung slides showing data on their success in manufacturability, check out EETimes.
GlobalFoundries: RF-SOI for 5G, FD-SOI Customers Engaged
Subramani Kengeri, VP of Global Design Solutions at GlobalFoundries talked about their 22nm FD-SOI, in his presentation Enabling SoC Innovations with 22FDXTM. He indicated that they’ve got over 40 customers engaged on it. Key points they’re hitting on that make them bullish on their prospects include:
For more on how GF see 22FDX as very well-positioned for IoT, see their Foundry Files blog. There’s also a really good piece in EEJournal by Byron Moyer entitled, A Non-FinFET Path to 10 nm – GlobalFoundries’ FD-SOI Alternative.
GF is of course also a dominant RF-SOI player, as seen in RFSOI: Defining the RF-Digital Boundary for 5G by Peter Rabbeni, Sr. Director RF Product Marketing and Business Development, GlobalFoundries. The presentation, which is available on the SOI Consortium website, notes that, “Significant R&D has been done in evaluating the application of SOI to 5G architectures, with very positive results,” so that, “SOI holds great promise in delivering on the key requirements of 5G systems.” (For an overview of GF’s RF-SOI position, see RF-SOI is IoT’s Future, and the Future in Bright on their Foundry Files blog.)
Renesas: in FD-SOI production at 65nm this year
Shiro Kamohara, Chief Engineer, Renesas Electronics Corp., lead off the presentations with Ultralow-Voltage Design and Technology of Silicon-on-Thin-Buried-Oxide (SOTB) CMOS for Highly Energy Efficient Electronics in IoT Era.
A Nikkei article reported from the conference that Renesas will be in mass production of 65nm FD-SOI – which they call Silicon-on-Thin-Box, or SOTB – for IoT products this year. Renesas reports the move cuts power to a tenth of what they’d seen in bulk. You can see the original article in Japanese here or a translated version here.
Soitec: wafers ready for mass adoption
In the presentation Substrate maturity and readiness in large volume to support mass adoption of ULP FDSOI platforms, Soitec Sr. VP of Digital Electronics Group Christophe Maleville, Senior Vice President, Digital Electronics BU provided data on every conceivable aspect of SOI wafers for FD-SOI and RF-SOI. He explained adaptations in the company’s Smart CutTM manufacturing technology that achieve astonishing levels of uniformity and thickness – or rather, thinness! With new metrology, they can predict and protect against variability in devices. And they are now producing FD-SOI wafers for 28nm processes with uniformity of +/- 1 atomic layer.
ST: making the case
For analog/RF, RF/mmW and mixed-signal/high-speed designers, Andreia Cathelin, Senior Member of Technical Staff at STMicroelectronics explained how and why FD-SOI makes their lives easier. Her presentation, FDSOI Technology Advantages for Analog/RF and Mixed-Signal Designs drills down to the technical for these folks.
Pietro Maestri, ST’s RF Product Line Director presented ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration. (BTW, we had an excellent high-level article by ST when H9SOI_FEM was first announced, describing the challenges faced by designers of smartphone front-end modules (FEMs) and how their H9SOI_FEM solves them – read it here.)
For anyone wondering about the status of FD-SOI following the just-announced company reorganization, COO Jean-Marc Chery told EETimes’ Peter Clarke that they remain fully committed to the technology. As noted in the article (read the whole thing here), “Chery emphasized that, following the announcement of ST’s withdrawal from STB and home gateway markets and of a proposed redeployment of 600 engineers, the company is now focused on automotive and Internet of Things applications and that therefore FDSOI is a core manufacturing process. Indeed it could be argued that moving engineers familiar with FDSOI from the STB group into MCUs and automotive will help to proliferate the technology through the company.”
NXP/Freescale: Loving FD-SOI
In another recent EETimes article, Peter Clark reported from the NXP “Smarter World Tour” that the newly merged NXP-Freescale is very bullish on FD-SOI (see the full article here).
He cites Goeff Lees, the GM for the MCU part of the merged businesses, who especially likes 28nm FD-SOI for IoT and MCUs. Ticking off the reasons, he lists energy efficiency, cost, analog support, security, temperature control and lower leakage current. In fact, he says, “I believe all MCU vendors could move to FD-SOI.” Wow.
So stay tuned – here at ASN we’ve got contributions from NXP/Freescale, Synopsys, GlobalFoundries, Surecore and more at the top of the 2016 queue. Yes, it’s going to be a good year.
SOI wafer leader Soitec and SITRI (aka Shanghai Industrial µTechnology Research Institute) have announced a collaboration agreement. (Read the press release here.) They say the strategic partnership will strengthen their leadership in high-growth wireless communications and the global market for RF apps, with a special emphasis on the fast-developing Chinese RF ecosystem.
They’ll focus on developing RF-SOI using advanced circuit designs based on Soitec’s substrate materials and technologies.
“Experience shows that Soitec’s engineered substrates can optimize RF-SOI technology and applications in terms of both cost competitiveness and power efficiency. This strategic partnership will enable us to push the limits of RF circuits and meet future connectivity needs,” said Soitec CTO Carlos Mazure.
“Enhancing RF signal integrity is a key focus of the mobile communications industry as it builds toward 4G-LTE Advanced and 5G standards. We are excited to partner with Soitec in developing next-generation SOI communication solutions. It is consistent with SITRI’s mission to create a collaborative R&D and commercialization environment to catalyze the growth of advanced technologies,” said Dr. Charles Yang, president of SITRI.