Tag Archive AMAT

ByAdele Hars

PCM/MRAM Workshop by Leti and Applied Materials During 2019 IEEE Intl. Memory Workshop

Two of the big, recent breakthroughs in memory technology – eMRAM and ePCM – have gotten their start in volume manufacturing on 28nm FD-SOI. In conjunction with the 2019 IEEE International Memory Workshop, SOI Consortium members Leti and Applied Materials have teamed up to give a technical program to explore short-term and long-term memory solutions. While the workshop is not specific to SOI, given the recent foundry announcements about ePCM and eMRAM for FD-SOI, the organizers predict it will be of particular interest to those following the greater SOI ecosystem. The event takes place at the end of the Sunday IMW tutorial day, starting at 5:30pm at the Hyatt Regency in Monterey, CA. Please see this page for the program and registration information.

Here is the program:

  • Emerging Non-Volatile Memory Promises Toward New Energy-Efficient Design and Applications – Michael Tchagaspanian, VP Business Development, CEA-Leti
  • Technologies That Enable MRAM and PCRAM in Volume Manufacturing – Kevin Moraes, Vice President, Metal Deposition Products, Applied Materials
  • Technology Improvements Directions of Emerging Non-Volatile Memory for New Applications Solutions – Etienne Nowak, Head of Memory Laboratory, CEA-Leti
  • Integration Schemes and Challenges for New Memories in a New Artificial Intelligence Era –Michel Frei, Director, Advanced Product & Technology Development, Applied Materials

Jean-Eric Michallet, Head of Leti’s Microelectronics Components Department, Silicon Component Division is one of the organizers. Here is his overview:

FD-SOI is expected to be a long-lived technology. It enables planar CMOS scaling and accommodates a great deal of More-than-Moore developments where its ability for low power and great analog performance can make a difference for IoT, Automotive, Machine Learning or 5G applications. But to do this it requires a high-performance and cost-effective non-volatile embedded memory option. The incumbent Flash cell is reaching the end of its roadmap due to the difficulty of shrinking the bitcell and manufacturing, as well as the finished wafer cost increase. Back-end integrated Random Access Memory in advanced CMOS process has been explored for many years now as a competitive solution for fast-write and low-voltage non-volatile embedded memories. Foundry availability of embedded Magnetic RAM and Phase Change RAM for FDSOI 28nm platforms has been announced recently, showing that these technologies have now reached industrial maturity. CEA-Leti and Applied Materials invite you to attend a technical program to explore short-term and long-term memory solutions, from early research to industrialization.

Registration is open, free, and available to all IMW attendees, and others. However, as seating is limited and as we have already several participants pre-registered, registration is by invitation only and early registration is recommended. If you are interested, please email Jean-Eric Michallet.

The event is presented in conjunction with the 2019 IEEE International Memory Workshop, to be held on Sunday, May 12th, 2019, Hyatt Regency, Monterey CA, starting at 5:30 pm.

ByAdele Hars

Tokyo SOI Workshop – Day 2 Recap (Part 2)

This is the second part of ASN coverage of Day 2 of the recent SOI Workshop in Tokyo, which was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available – click here to see the full list.

(In case you missed them, Day 1 and Day 2 – Part 1 were covered in previous posts.)

GlobalFoundries & 5G

Peter Rabbeni, GlobalFoundries’ Sr. Director of 5G BizDev and Product Line Marketing focused on mmWave and why/how 5G. In his talk, Delivering on the Promise of 5G: Semiconductor Solutions for the Next Wave of Data, he pointed out that there’s not one solution for all use cases – but there is an SOI solution for all the opportunities.

(Courtesy: GlobalFoundries, SOI Consortium)

You need mmWave for latency, simultaneous connectivity, energy-efficiency and mobility, he explained. mmWave addresses the trade-off between distance and data rates. In a phase array, the beam is steered, but because of atmospheric absorption, you have to do multiple beams at high frequencies.

RF-SOI technology is already found in virtually every smartphone in the world. Now, he sees two main benefits in RF-SOI (a partially depleted technology that uses “trap-rich” substrates, btw) in the move to 5G and mmWave. One is device stacking, which you can do in SOI to overcome the Johnson Limit (a tradeoff between breakdown voltage and frequency). The other comes from the benefits inherent in the substrate: high-resistivity, high-Q and isolation. It means you can have smaller arrays for each element, and fewer chips per array. That’s key: you need those smaller arrays for handsets and customer premises equipment.

(Courtesy: GlobalFoundries, SOI Consortium)

Different designers are taking different approaches to RF, he notes.  There are those doing FEM-centric designs, which integrate from the antenna back toward the transceiver.  And then there are those that are doing integration-centric designs, which target integration from the transceiver/BB toward the antenna.  The first approach is being driven by those customers with unique IP and presence in the front-end module space.  The other is being driven by folks with IP and presence in the SOC space.  Both will exist in some form, he contends.  45RFSOI is well aligned with the first case and focused primarily with FEM leadership performance and integration.  22FDX, on the other hand, is very well suited for transceiver/baseband ADC/DAC integration and can integrate the FEM functionality as well.  Pathfinding on the FEM integration component is on-going for 22FDX.


SOI is “…the perfect solution to our needs”, said Steven Yeung, Design Manager with MIPS/Imagination Technologies in his talk, MIPS Leading Heterogenous Compute in Automotive & IP. The cost of failure is increasing he noted, citing the ISO standard 26262 for functional safety in road vehicles, and SOI “helps a lot”.

(Courtesy: MIPS/Imagination Technologies & the SOI Consortium)

Leti Paves the Road Ahead With SOI

As noted in the presentation title, research powerhouse Leti sees that the Future of the Automotive Industry is Paved With SOI. Vincent Roger of Leti’s Corporate Business Development made convincing arguments as to why FD-SOI is the right solution for automotive:

  • you need advanced digital circuitry for all computational tasks in the automotive environment

  • the 3-generation node gap between automotive and consumer is closing

  • FD-SOI is more power efficient than planar bulk (both at 28 and 22nm) or FinFET (16nm)

  • it’s simpler in terms of design and IP portability than FinFET

  • it’s a proven solution, with better reliability and lower design costs

  • it addresses all performance levels and communications

  • it simplifies integration of control electronics for distributed sensors

Leti is actively working on getting RF capabilities in FD-SOI adopted more quickly. For example, they are developing RF models for their UTSOI-2 modeling suite for FDSOI, including back bias effects. And they’re also developing innovative basic design blocks that prove the technology validity and add new functionality.

(Courtesy: Leti and the SOI Consortium)

He also sees an even bigger role for RF-SOI, the technology of choice for RF Front End Modules for connected vehicles and 5G applications. With Soitec, they’re working to keep improving existing substrates and introduce new concepts.

SOI Wafer Capacity Expanding

SOI wafer suppliers (Soitec, SEH and Simgui) are expanding capacity, said Soitec EVP Thomas Pilisczcuk. His talk, The Role of Substrates in Accelerating Mass Adoption of SOI Technologies, reviewed the various SOI substrates and partners across FD-SOI, RF-SOI, photonics, power, image sensors and more.

Soitec is launching a program called FIRST (for First Integration Ramp of SOI Toolbox) to help customers reach competitive yields fast. They are also help customers facilitate SOI integration into design and manufacturing.

More Joining In, Looking Ahead

There are still more talks that are now posted on the SOI Consortium website. IHS/Markit made a very interesting high-level presentation on LIDARs & Sensor Fusion ECUs Advancing ADAS Architectures Toward Automated Driving, which called for chipmakers to integrate more features. Nokia Future X Network for 5G & IoT looked at infrastructure (they use their own chipsets). ST looked at smart cities in Sensor-to-Cloud Connectivity for IoT.

Equipment makers are also eager participants in the FD-SOI ecosystem. Screen’s presentation was entitled Full Participation Within the SOI Consortium. The Applied Materials talk, Enabling SOI and IoT: An Equipment and Materials Engineering Perspective, covered how they’re working with their customers and their customers’ customers to understand the trends and enable the device roadmap.

Next Stop: Shanghai!

Mark your calendars: the next workshop sponsored by the SOI Consortium will be in Shanghai this September 26th and 27th  (one  day is all about FD-SOI, the other about RF-SOI). You can now register or ask for an invitation: see  Events on the SOI Consortium website. Last year’s Shanghai event was really dynamic and absolutely packed, so you’ll want to make sure you register early. (But if you can’t make it, you can of course read about later it in ASN!)


Strain and SOI Lead to Faster, Cooler Transistors

Applied Materials responds to evolving requirements.

Prior to 65nm device manufacturing, performance improvements from one generation to the next have been gained primarily through continuous reduction of transistor dimensions. However, for the 65nm generation and below, following this approach without change leads to unacceptably high leakage and power consumption. To help navigate this formidable challenge and continue enhancing device performance, IC manufacturers are adopting new methodologies, processes, and materials. Key among the advanced technologies that contribute to faster transistor speeds with reduced leakage are strained silicon and silicon-on-insulator (SOI). Read More