Tag Archive AMD

ByFanny Rodriguez

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

S3Sadvprgmpic_lowres

Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:

S3S15lineup

The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.

ByGianni PRATA

Strong uptick in FD-SOI patent activity, according to KnowMade report

There’s been a significant uptick in patents related to fully-depleted SOI, according to a new report by KnowMade (click here to get the report brochure).  The report looks at both FD-SOI and SOI-FinFETs (both of which are fully depleted technologies).  More than 740 patent families have been published to date, of which planar FD-SOI accounts for 340 families.  Following a rush of activity about 10 years ago there was a dip, but activity over the last couple of years has once again been very strong.

The report provides a comprehensive overview, essential patent data for fully depleted SOI, plus a searchable database with links.  It identifies more than 30 patent holders of FD-SOI related intellectual property, providing in-depth analysis of key technology segments and key players. “The major proponents of the FD-SOI technology have strong IP arms, but other unexpected players known as not supporting FDSOI [including TSMC and Intel] are also present,” notes the report.

ByGianni PRATA

AMD has made two new 32nm SOI-based product announcements: the 2013 Elite A-Series Accelerated Processing Unit codenamed “Richland” and the AMD FX-9590

AMD has made two new 32nm SOI-based product announcements:

ByGianni PRATA

AMD’s second generation A-Series Accelerated Processing Units is now available in retail and distribution channels

Based again on 32nm SOI, AMD‘s second generation A-Series Accelerated Processing Units (APUs) (formerly codenamed “Trinity”) for mainstream and ultrathin notebooks, All-in-One and traditional desktops, home theater PCs and embedded designs is now available in retail and distribution channels. The new x86 cores, codenamed “Piledriver,” are an evolution of the revolutionary “Bulldozer” cores with some major performance enhancements, hitting up to 4.2 GHz. But consumer-savvy reviewers also cite the impact of Trinity’s excellent performance-per-watt on battery life.

ByGianni PRATA

Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)

The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.

Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.

Meritage Resort and Spa in Napa Valley

The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California.
(Photo Credit: Rex Gelert)

This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.

The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.

(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)

The papers

ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.

Here’s a rundown of the sessions:

  1. Plenary: talks by Soitec and ARM
  2. FullyDepleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
  3. FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
  4. Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
  5. RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
  6. Memory: contributors from IMEP, ST, TI, R&D institutes and academia
  7. Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
  8. MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
  9. RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
  10. Hot Topics: FullyDepleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
  11. Late News: tbd, of course…

The courses & panel

Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.

The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.

Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.

All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?

ByGianni PRATA

The new 32nm SOI Bulldozer-based AMD Opteron™ Processors will power the National Science Foundation’s Blue Waters project

The new 32nm SOI Bulldozer-based AMD Opteron™ Processors will power the National Science Foundation’s Blue Waters project. Per the TOP500 Supercomputers list, more than two million AMD Opteron cores power many of the world’s fastest supercomputers across 14 countries.

ByGianni PRATA

AMD Bulldozer Architecture Leverages 32nm SOI

With performance, efficiency, and power optimization as top priorities, AMD’s innovative Bulldozer architecture is built on 32nm SOI.

As of the Fall of 2011, AMD is shipping both client and server CPUs based on the new Bulldozer architecture. The first of the new APUs (CPU + GPU) incorporating Bulldozer modules will start shipping in 2012.

All of AMD’s innovative new Bulldozer architectures are built on 32nm SOI technology fabbed by GlobalFoundries.

Bulldozer is the code name for AMD’s next-generation CPU core, which targets the two key “heavy lifting” markets:

  • servers, and
  • the high-performance end of the client platform.

As indicated on the AMD roadmap, all of the company’s CPUs for the “server” market – chips in the Opteron family – are based on the 32nm SOI Bulldozer architecture.

The roadmap for “client” products also shows key chip families for desktop processors and high-performance notebooks based on the 32nm SOI Bulldozer architecture.

Opteron/Interlagos

OpteronInterlagos is the codename for AMD’s 12- or 16-core 32nm SOI server processors based on the new “Bulldozer” processor core. It carries the AMD Opteron™ 6200 and 6100 Series processor brands and is supported by the AMD Opteron™ 6000 Series (“Maranello”) platform.

Interlagos includes the world’s first 16-core x86 processors. The first Interlagos shipments began in August 2011 to large custom supercomputer installations: 25,000 to Oak Ridge labs and 38,000 to Los Alamos, for example.

FX

Unlocked FX ProcessorThe latest AMD FX series marks the first retail availability of Bulldozer-based processors. Available in 8-, 6- and 4-core configurations, these CPUs targets extreme multi-display gaming, mega-tasking and HD content creation for PC and digital enthusiasts.

The new FX includes the first-ever eight-core desktop processor, which took the Guinness World Record for the “Highest Frequency of a Computer Processor,” hitting a top speed of 8.429 GHz.

Up next: APUs

AMD has dubbed the company’s new Fusion APUs the era of “Personal Supercomputing”. The A-Series APUs, codenamed Llano, that started shipping in mid-2011 are based on 32nm SOI, but their CPUs are based on the previous generation of the x86 CPU architecture, and as such are not yet Bulldozer.

However, the next generation in the A-Series APUs, codenamed Trinity and scheduled for release in 2012, will also be based on 32nm SOI with next-generation Bulldozer CPU cores.

Power-optimized design

The Bulldozer architecture is based on “modules” of two cores each. AMD explains that this means two simultaneous threads can be executed more efficiently than two threads running on a single integer core.

Bulldozer module

(Courtesy: AMD)
Bulldozer specs⁴:
> each module has 2 cores
> 213 million transistors/module
> 11 metal layers, 32nm SOI, HKMG
> 0.8 – 1.3V operation
> Area/module: 30.9mm2 (for a 2-core CPU module + 2MB L2 cache)

For each two-core module, there is a shared 2MB L2 cache. The shared L3 cache varies from 8MB to 16MB, depending on the processor.

The Bulldozer design is new from the ground-up. It required co-development of power efficiency, timing, and functionality¹. The team reduced leakage power by 95% when both cores are idle by module-level VSS (rather than VDD) power gating, first used in the 32nm Llano CPU. SOI enables this to be done without extra processing steps².

The L1 caches use an 8T storage cell. The design team said that the change from a 6T cell in 45nm to 8T in 32nm improved the low-voltage margin and read timing and reduced power³.

This game-changing architecture on SOI promises an exciting new era of high performance and low power in systems ranging from sleek but powerful notebooks to the fastest supercomputers on the planet.

1. Design Solutions for the Bulldozer 32nm SOI 2-Core Processor Module in an 8-Core CPU. Tim Fischer et al. IEEE ISSCC 2011, p.78.
2. An x86-64 Core Implemented in 32nm SOI CMOS, by Ravit Jotwani, et al. IEEE ISSCC 2010, p. 106.
3. Idem, Fisher et al.
4. Idem, Fisher et al.

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Thank you to AMD for help on this article.

ByGianni PRATA

AMDFX (Bulldozer) CPU has entered the Guinness World Book of Records

AMD FX processorOverclocked to 8.429 GHz , the AMDFX (Bulldozer) CPU has entered the Guinness World Book of Records for “Highest Frequency of a Computer Processor”. On 32nm SOI from GlobalFoundries, the 8-core FX will launch in Q4 2011, targeting gamers.

ByGianni PRATA

AMD has begun revenue shipments of its new 32nm-SOI “Interlagos” processors

Opteron processorCalling it “a monumental moment for the industry”, AMD has begun revenue shipments of its new  32nm-SOI  “Interlagos” processors, the first CPUs based on the “Bulldozer” architecture. Fabbed by GlobalFoundries, “Interlagos” is the codename for AMD’s 12- or 16-core 32nm SOI server processor based on the new “Bulldozer” processor core.  It carries the AMD Opteron™ 6200 Series processor brand and is supported by the AMD Opteron™ 6000 Series (“Maranello”) platform.

ByAdministrator

The SOI Papers at ISSCC 2011

The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront.

As always, performance gains generate plenty of buzz. But the SOI papers were also notable for work reducing power consumption, extending scalability and overcoming threshold voltage variation.

IBM presented the world’s highest frequency microprocessor to date, clocking in at 5.2 GHz. On 45nm SOI, it’s the first commercial processor ever to break through the 5GHz speed barrier, and is the centerpiece of Big Blue’s new zEnterprise 196 system.

In another paper, IBM presented the first embedded high-k/metal-gate (HK/MG) SRAM on 32nm SOI enabling operation at down to 0.7V.

AMD presented its Bulldozer 2-core modules, which are on 32nm SOI with HK/MG. Clocking in at 3.5GHz, we’ll see them beginning in desktop and server Fusion chips this year.

In a quieter but clearly significant paper, ST and Leti compared 65nm low power (LP) partially depleted (PD) SOI with standard 65nm LP CMOS bulk. They found that PD-SOI, when combined with a low resistivity produced with forward body bias of the power switch, can reduce leakage current by 52.4% vs. bulk and increase the frequency by 20% at 1.2V, while decreasing power by 30% at 360MHz.

For summaries of additional SOI-based papers at ISSCC and other recent conferences, see ASN’s PaperLinks.