Tag Archive ASIC

Dolphin Showcases New EDA Tool for FD-SOI – More THINGS2DO Results

Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin’s cutting-edge EDA tool for safe Power Regulation Networks implementation.

THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, >€120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design & development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology — read about that here.)

“Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.”

The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications.

Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity.

The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization.

Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation & activity control networks for best SoC PPA.

Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. “Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX,” Michel Depeyrot, Dolphin Integration’s Chairman, said at the time. “As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA.”

See the Dolphin Integration website for the full catalog of their IP, EDA and ASIC/SoC service offerings, including for GF’s 22FDX.

12nm FD-SOI on the Roadmap for H1/2019 Customer Tape-out! Says GloFo (While Giving 22FDX Ecosys a Great Boost)

gf_logo12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).

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(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology.  “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”

The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

All About 12

GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.

The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.

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(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).

22 Design Plug ‘n Play

Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.

Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.

Initial FDXcelerator Partners have committed a set of key offerings to the program, including:

  • tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features,
  • a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements,
  • platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX,
  • reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market,
  • resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology; and
  • product packaging and test (OSAT) solutions.

Additional FDXcelerator members will be announced in the following months.

Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed

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Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

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ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.

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Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.

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Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

Interview: Leti Is the Moving Force Behind FD-SOI. CEO Marie Semeria Explains the Strategy (part 1 of 2)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?

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Marie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.

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Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

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Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.

Click here to read part 2 of this exclusive interview.

28nm FD-SOI cryptocurrency ASIC first to debut in silicon, surpasses expectations with 0.45V operation

(Courtesy: SFARDS)

SFARDS’ SF3301 cryptocurrency ASIC is the world’s first chip to use 28nm FD-SOI. Surpassing expecttions, it operates at a stunning 0.45V. (Courtesy: SFARDS)

Right on schedule, the SFARDS cryptocurrency ASIC on 28nm FD-SOI has made its debut in silicon, and is surpassing expectations. In what is clearly a stunning success, the company announced that the ASIC’s lowest working voltage is 0.45V. This means it operates stably at a power supply voltage that’s about half that of competing 28nm offerings.

An article published on the SFARDS website (see the whole thing here) said, “Using the latest in FD-SOI processing technology, SFARDS has successfully completed its 28nm SF3301 dual-algorithm ASIC chip. The SF3301 is the world’s first chip to use this manufacturing process and is at the same time the world’s first 28nm dual-algorithm (SHA-256 & Scrypt) chip, capable of mining these two algorithms simultaneously or singularly.

“SFARDS’ SF3301 fully utilizes the advantages of the FD-SOI technology. This brings increased forward body bias; the chip is operational at lower voltage while maintaining a higher frequency. The chip boasts impressive power efficiency while affording high hash power, allowing for much lower wastage per hash. The ASIC’s lowest working voltage is 0.45V.”

As noted in ASN’s Buzz in March 2015 (read it here), cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips.  As well-explained in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.

28nm FD-SOI Cryptocurrency Mining ASIC tapes out, to debut April 2015

Cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015. (You can read the announcement here.)

At the time of this post, tape out of the company’s SF3301ASIC has been announced as complete. Cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips.  As noted in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.

As posted on the SFARD blog, “By using FDSOI technology not currently present in any other chip on the market, power efficiency when mining with SHA-256 is predicted to reach below the 0.3 J/GH range, and 2.0 J/MH when mining with Scrypt.

“The SF3301 is extremely versatile, allowing you to mine multiple currencies with one device. This means price fluctuations can be harnessed and being forced to turn off your miner is far less likely.

“A condition can arise where altcoins are utilized to cover electricity costs while bitcoin is continuously and simultaneously being mined. This ability is something never seen before with 28nm technology.”

Memoir Systems’ Memory IP Now in ST’s FD-SOI ASICS & SOCs

Memoir Systems has made its revolutionary Algorithmic Memory Technology available for embedded memories in ASICs and SoCs manufactured in STMicroelectronic’s FD-SOI process technology. ST is a leading manufacturer of ASICs.

“With our commitment to breakthrough memory technology, accelerated design times, and extreme high-performance, making our best-in-class Algorithmic Memory Technology available on FD-SOI was important to us and our customers, “said Sundar Iyer, co-founder and CEO at Memoir Systems. “The ease of porting, together with the performance we’ve seen, confirms that FD-SOI is faster, cooler, and simpler.”

Interview: How NXP’s SOI Technology Enables Major Advance in Automotive Position Sensors

Guenter Reiniger, Marketing Manager for NXP’s Automotive Sensors, explains how SOI helps eliminate the need for external components in a new magnetic sensor family.

Günter ReinigerAdvanced Substrate News (ASN): NXP recently announced the KMA210, the first in a new family of magnetoresistive (MR) sensor chips. What is it used for?

Guenter Reiniger (GR): The KMA210 is a position sensor for automotive applications wherein a precise mechanical angle needs to be measured. So on one hand you can use it in things like electronic steering, active suspension and automatic headlight adjustment. But because it’s very accurate and very robust, it’s also an excellent choice for under-the-hood applications such as power train, throttle control and air control valve measurements. And since it operates in temperature ranges up to 160°C, it’s ideal for things like emissions control and clean diesel applications.

ASN: The MR technology isn’t new – what’s new about this chip?

GR: MR technology was pioneered by Philips and a few others over 30 years ago, so it’s proven and robust. We’ve been selling MR sensors in very high volumes for many years – Continental alone has used over half a billion in its ABS systems. What’s new here is our ability to incorporate the signal-conditioning ASIC with the MR sensor in a full system-in-package solution. That’s where the SOI comes in.

ASN: Why did you need SOI?

GR: Our customers now have to meet extremely rigorous requirements, especially with respect to safety, emissions controls, electromagnetic compatibility (EMC) and electrostatic discharge (ESD). Previous solutions involved the sensor plus separate bulk-silicon-based components that our customers would incorporate on a board. To cost-effectively incorporate the sensor with the requisite electronics in a single package, we need to put the signal-conditioning ASIC on 140nm SOI using our latest ABCD9 process technology.

ASN: Why is that?

GR: SOI gives our chip designers a number of advantages, such as:

  • Reduced resistance for the transistor in the on-state (Rds(on)), so much less waste heat is produced, which we leveraged to make a much smaller chip.
  • Much greater packing densities
  • Latch-up-free behavior, since there are no parasitic junctions between N-type and P-type devices.
  • Ability to handle voltage spikes from the starter motor or alternator
  • Greatly improved heat tolerance.
  • Easy integration of multiple power devices, bridge rectifiers, and flyback diodes on the same piece of silicon. In combination with a significant reduction in parasitic capacitance, this simplifies and speeds the chip design process.

ASN: In addition to the cost effectiveness for you, what advantages does SOI confer to your customer, the automotive designer?

NXP's KMA210 magneto-resistive sensor

An example of how NXP's KMA210 magneto-resistive sensor would be used in a throttle position application. Because the KMA210 is manufactured using NXP's ABCD9 process technology on SOI, the signal-conditioning ASIC and the sensor are fully integrated in a system-in-package solution that requires no additional external components. (Courtesy: NXP)

GR: We created this product in very close partnership with our customers. By implementing the ASIC on ABCD9 SOI, the interface areas of the ASIC have 16V overvoltage protection – in bulk the chip would have been too big and too expensive. From the automotive designer’s perspective, they can use the same socket they used for previous generations when it was just the sensor – but now they don’t have to design a board to go with it – everything’s in there. The device contains two embedded block capacitors (for Vdd and output) within the same package. And of course you get the advantages you always get with SOI: robustness in terms of EMC, ESD and high temperatures. The package really reduces system cost: there’s no additional design, no boards, no external filter components, no lead frames. All told, the KMA210 position sensor with the integrated ASIC on SOI gives the automotive designer the key to a cheaper, smaller and more robust measurement solution.

ASN: What does the future hold?

GR: With ABCD9 on SOI, we are working on a next generation of these chips for temperatures up to 200°C. For next year, we’ll also have a redundant version (with two devices in one package), and a version with digital output. While perhaps we could have done all this without ABCD9 and SOI, we couldn’t have done it under the same commercial conditions. These are really cost-effective devices.

IBM has developed a 32nm SOI prototype of the smallest

IBM has developed a 32nm SOI prototype of the smallest, densest and fastest on-chip eDRAM. It uses four times less standby power and has up to a thousand times lower soft-error rate. The technology will be used by a wide range of ASIC and foundry clients, and as well as in IBM’s servers. An initial 32nm ARM library is available now, with 22nm development also underway. Details will be described at IEDM in December.

Sandia National Laboratories

Sandia National Laboratories’ fab in Albuquerque, N.M., has been accredited by the U.S. Department of Defense to provide “trusted foundry” services for its strategically radiation-hardened, 3.3-volt, 0.35-micrometer SOI process, which produces custom, low-volume, high reliability ASICs for conditions of extreme temperature fluctuations, shock and radiation.