ARM is stepping up its effort to support the FD-SOI ecosystem. “Yes, we’re back,” confirmed Ron Moore, VP of ARM’s physical design group. This and much more good news came out of the recent FD-SOI Symposium organized in Silicon Valley by the SOI Consortium.
The full-day Symposium played to a packed room, and was followed the next day by a full-day design tutorial. Though it was a Silicon Valley event, people flew in from all over the world to be there. (BTW, these symposia and tutorials will also be offered in Japan in June, and Shanghai in the fall). I’ll cover the Silicon Valley FD-SOI design tutorial (which was excellent, btw) in a separate post.
Most of the presentations are now posted on the SOI Consortium website. Here in this ASN post, I’ll touch on some of the highlights of the day. Then in upcoming posts I’ll cover the presentations from Samsung and GlobalFoundries.
If you’re designing in FD-SOI, we’ll help: that was the key message from ARM’s Ron Moore during the panel discussion at the end of the day. Earlier that morning, he’d given an excellent presentation entitled Low-Power IP: Essential Ingredients for IoT Opportunities.
CAGR for most IoT units is roughly 50%, he said, counting home (1.6B units by 2020), city (1.8B), industrial (0.6B) and automotive (1.1B). Compare that to the 2.8B smart phones – which he sees as a remote control and display device. The key differentiator for IoT is that 90% of the time the chip is idle, so you really don’t want leakage.
FD-SOI, he said, gives you a silicon platform that’s highly controllable, enables ultra-low power devices, and is really good with RF. ARM’s worked with Samsung’s 28FDS FD-SOI offering comparing libraries on bulk and FDSOI, for example, and came up with some impressive figures (see the picture below).
The foundry partners and wafer providers are in place. So now ARM is asking about which subsystems are needed to fuel FD-SOI adoption. Ron recognizes that the ARM IP portal doesn’t yet have anything posted for FD-SOI, but they know they need to do it. He called on the SOI Consortium to help with IoT reference designs and silicon proof points.
In the Q&A, audience member John Chen (VP of Technology and Foundry Management at NVIDIA) asked about FD-SOI and low-cost manufacturing of IoT chips. Moore replied that we should be integrating functionality and charging a premium for IoT chips – this is not about your 25-cent chip, he quipped.
Geoff Lees, SVP & GM of NXP’s Microcontroller business gave a terrific talk on their new i.MX 7 and 8 chips on 28nm FD-SOI. (And Rick Merritt gave it great coverage in EETimes – see NXP Shows First FD-SOI Chips.)
NXP’s been sampling the i.MX 7 ULP to customers over the last six months, the i.MX 8QM is ramping, and the i.MX 8QXP, 8Q and 8DX are enroute. Each of these chips is optimized for specific applications using biasing. A majority of the design of each chip is hard re-use, and the subsystems can be lifted and dropped right into the next chip in the series. Power consumption and leakage are a tiny fraction of what they’d had been in previous generations. Ultra low power (aka ULP) is heading to new levels, he says.
With FD-SOI, it’s easy to optimize at multiple points: in the chip design phase, in the production phase and in the use phase. They can meet a wide range of use cases, precisely targeting for power usage. FD-SOI makes it a win-win: it’s a very cost effective way to work for NXP, plus their customers today need that broader range of functionality from each chip.
Geoff tipped his hat to contributions made here by Professor Boris Murmann of Stanford, who’s driving mixed signal and RF into new areas, enabling high-performance analog and RF integration. (Folks attending the FD-SOI tutorial the next day had the good fortune to learn directly from Professor Murmann.)
Finally, he cited something recently pointed out by Soitec (they’re the SOI wafer folks) Chief Scientist Bich-Yen Nguyen: if half your chip is analog and/or RF, she’s observed, the future is very bright indeed for FD-SOI.
Briefly, here are some more highlights.
Synopsys: John Koeter, VP of the Marketing Solutions group showed slides of what they’ve done in terms of IP for Samsung and GlobalFoundries’ FD-SOI offerings. But there’s a lot they’ve done with partners he couldn’t show because it’s not public. In terms of tools and flows, it’s all straightforward.
Dreamchip: Designing their new chip in 22nm FD-SOI was 2.5x less expensive than designing it in FinFET would have been, said COO Jens Benndoorf in his presentation, New Computer Vision Processor Chip Design for Automotive ADAS CNN Applications in 22nm FDSOI. One application for these chips (which taped out in January) will be “digital mirroring”: replacing sideview mirrors with screens. Why hasn’t this been done before? Because LED flickering really messes with sensor readings – but they’ve mastered that with algorithms. The chip will also be used for 360o top view cameras and pedestrian detection. They’re using Arteris IP for the onchip networking, and implemented forward body bias (FBB). The reference platform they created for licensing has generated lots of interest in the automotive supply chain, he said.
Greenwaves: CEO Loic Lietar talked about the high performance, ultra-low power IoT applications processor they’re porting from bulk to FDSOI with a budget of just three million euros. The RISC-V chip leverages an open source architecture (which he says customers love) and targets smart city, smart factory, security and safety applications. As such, it needs to wake up very fast using just microwatts of power – a perfect match for body biasing in FD-SOI.
Leti: In her talk about roadmaps, CEO Marie-Noelle Semeria said the main two drivers they’re seeing in the move to FD-SOI are #1: low power (a customer making chips for hearing aids can cut power by 8x using body biasing, for example) and #2: RF (with Ft and Fmax performance that “…will be hard for FinFET to achieve”). Leti knows how to pull in all kinds of boosters, and is finding that RF performance is still excellent at the 10/7nm node. They’ve developed a low-power IoT platform with IP available for licensing. Other recent FD-SOI breakthroughs by Leti include: demonstration of a 5G mmW 60GHz transceiver developed with ST; the first 300mm Qbit, opening the door to quantum computing; a photodiode opening the door to a light-controlled SRAM; and a new 3D memory architecture leveraging their CoolCubeTM that they’re working on with Stanford.
IBS: CEO Handel Jones predicts that there “will be war in the year to come” at the 22nm node, as all the big foundries take aim. FD-SOI is the best technology for RF, ULP and AMS, and there’s a huge market for it. He also said China made the right decision to support FD-SOI, and will come out ahead in 5G.
The day ended with a lively panel discussion (moderated by yours truly) featuring experts from ARM, GF, Invecas, Soitec, Synopsys, Verisilicon and Sankalp. IP availability was a big theme, but generally there was agreement that while some gaps still exist, they’re being filled: lack of IP is no longer an issue. Soitec VP Christophe Maleville confirmed that the wafers for FD-SOI are readily available and that they’re seeing excellent yields.
All in all, it was another really good day for FD-SOI in Silicon Valley.
SOI Consortium member GlobalFoundries is teaming up with the Chengdu municipality to build a fab in western China offering FD-SOI (see press release here). The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX®, GF’s 22nm FD-SOI process technology. The Chengdu fab is expected to begin volume production of 22FDX in 2019.
In Germany, GF plans to grow the overall FD-SOI capacity of its Fab 1 facility in Dresden by 40 percent by 2020. GF says they need the new capacity to meet demand for IoT, smartphone processors, automotive electronics, and other battery-powered wirelessly connected applications. Dresden will continue to be the center for FDX technology development. GF engineers in Dresden are already developing the company’s next-generation 12FDXTM technology, with customer product tape-outs expected to begin in the middle of 2018.
In Singapore, GF will also add new capabilities to its industry-leading RF-SOI technology.
12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).
The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”
Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”
The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”
GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.
The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.
“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”
Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).
Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.
Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.
Initial FDXcelerator Partners have committed a set of key offerings to the program, including:
Additional FDXcelerator members will be announced in the following months.
FD-SOI is the default choice for digital in ST’s automotive and discrete group (ADG), Marco Monti, EVP of the business unit told EETimes’ Peter Clarke in a recent article (read it here). The next generation of ST’s most advanced microcontrollers (currently on 40nm bulk) will be on 28nm FD-SOI, he said. Monti also gave examples of other FD-SOI automotive chips ST is doing for partners, including chips for WiFi, satellite radio, telematics, entertainment and ADAS (advanced driver assistance systems). “FD-SOI is not just a manufacturing node for us. It’s a whole cluster of technologies for all things in the car,” Monti told Clarke.
Dan Hutcheson, CEO of VLSIresearch, Inc. finally likes FD-SOI. That’s important, because he’s a really influential person in the chip world. Everybody who’s anybody in the chip biz pays attention to what VLSIresearch, Inc. has to say.
Dan recently gave a talk entitled “FD-SOI: Disruptive or Just Another Process?” to a packed-to-the-brim room during the FD-SOI Symposium in San Jose. (The ppt he used there is available on the SOI Consortium website – download it for free here).
Happily for those who didn’t make it to San Jose, Dan then went into the studio and made a video encore of his presentation for all to see – and it’s now posted on his weSRCH site. So you get not just his slides, but also his explanations and comments.
But for those of you who just want a quick recap, here are some of his key points.
Dan, as he’s always quick to point out, is an economist, albeit one extremely well-versed in chip technology. He always thought SOI was an elegant solution, but didn’t see cost savings in the fab as a driver. When asked to give a talk in San Jose, he decided to brush up a bit on what people were saying about FD-SOI. So he did an informal survey – and of course, being Dan, he can talk to just about anyone he wants.
In this case, he talked to decision makers from about a dozen top companies in the chip biz – enough to give him a 95% confidence level in his results. And the results are impressive: almost ¾ said they had FD-SOI designs underway or had already used it, while only about a third said they’ll stick firmly to bulk.
It turns out that there are companies out there doing both FinFETs and FD-SOI. Why? They’ve figured out the differentiable features, they told him. And some designers are now saying that FD-SOI is actually easier to design in than FinFETs, with one company reporting that design time in FD-SOI was half that of FinFETs.
Dan learned that the two biggest drivers of FD-SOI are IoT and automotive – IoT because those super power-stingy chips get enormous leverage out of back biasing, and automotive for reliability (and for both they get ease of analog integration).
But at the heart of it, it’s a business case: “It’s not about cost,” he says. “It’s about time-to-money.” With FD-SOI, TTM is significantly faster.
Those that go with FinFET are more often a big company (so they can afford the high NRE* costs) with a huge market, big die and a lot of digital. But if the market’s smaller, faster-moving and needs scaled-down NRE costs, then the people Dan talked to said they are turning to FD-SOI. They see it getting them to market faster, gives them lots of “knobs” and advantages in terms of power, reliability and analog integration, it’s easier to design in, and really enables product differentiation. In fact Dan had analog folks telling him that FD-SOI gave them back some of their favorite tricks and tools that they’d lost after the 130nm node.
Finally, Dan sees FD-SOI as a technology with both a long history and a long lifetime ahead. FD-SOI is not in itself disruptive, but is rather an enabler of disruption. The disruption, he says, is IoT. By all means check out his video if you want more detail on his perspective on IoT, automotive and the foundry offerings.
In conclusion, he urges users to strengthen the ecosystem’s momentum by disclosing their success stories – though he also sees how they might be reluctant to, as FD-SOI is the secret sauce that gives them a huge competitive advantage. But in the end rewards will be reaped, as driving volume up will drive costs down.
If you have a good FD-SOI design story you’d like to share, let us know here at ASN – we’ll be happy to consider it for publication, to help get the word around.
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*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, load-boards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
“We intend to focus all new engagements in design using 28nm FD-SOI,” Samsung Semi’s Kelvin Low told SemiEngineering’s Mark Lapedus in a recent article (read it here).
Low, who’s senior directory of the company’s foundry marketing says they’ll of course continue to support existing 28nm bulk customers, “But we think FD-SOI has enough benefits to attract new customers and designers.”
Registration is open for GlobalFoundries’ technical webinar, “How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology” (click here to go to the registration page). The webinar will cover the optimal steps to successfully implement ARM® Cortex®-A Series* processors using 22FDXTM 22nm FD-SOI technology.
GF Design Enablement Fellow Dr. Joerg Winkler will address:
This webinar will take place April 26, 2016 at10:00 am Pacific Time.
BTW, GF’s already done quite a few 22FDX-related webinars and videos – click here to see the current list.
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* Per ARM, “Cortex-A processors are specifically designed to execute complex functions and applications such as those required by consumer devices like smartphones and tablets. Their performance efficiency is also making them an increasingly popular choice for servers and enterprise applications where large core clusters can be combined for optimal solutions.”
By Ronald M. Martino, Vice President, i.MX Applications Processor and Advanced Technology Adoption, NXP Semiconductors
At NXP, we’re very excited about the prospects for our new i.MX 7 and 8 series of applications processors, which we’re manufacturing on 28nm FD-SOI.
As noted in part 1 of this article series, the new i.MX 7 series, which leverages the 32-bit ARM v7-A core, is targeting the general embedded, e-reader, medical, wearable and IoT markets, where power efficiency is paramount. The i.MX 8 series leverages the 64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, and well as high-performance general embedded and advanced graphics applications.
Choosing an FD-SOI solution gave our designers some specific tools that helped them to more easily and robustly deliver the features our customers are looking for. Here in part 2, we’ll look a little more deeply into the markets each of these chip families is targeting, and the role FD-SOI plays in helping us meet our specs.
Announced last June, the first members of our new 7 series — the i.MX 7Solo and i.MX 7Dual product families — will be hitting the market shortly. We’ve been shipping samples since last year, and the response has been tremendous. (You can read about the i.MX 7 IoT ecosystem we’re helping create for our customers here and support for wearable markets here.)
Our i.MX 7 customers are building products for power- and cost-sensitive markets. That of course includes a vast array of innovative IoT solutions and wearables, but also solutions for other parts of the embedded market like handheld point-of-sale (POS) and medical devices, smart home controls and industrial products. The i.MX 7 series also continues NXP’s industry leading support for the e-reader market via integration of an advanced, fourth-generation EPD controller.
For all these markets, excellent performance is very important, but both dynamic and static power figures are really key. When you’re creating a system with power efficient processing and low-power deep sleep modes, you enable a new tier of performance-on-demand, battery-operated devices that are lighter and cheaper, and in a virtuous cycle require smaller batteries.
The next members of the NXP i.MX 7 series combine ultra-low power (dynamically leveraging the reverse back biasing you can do with FD-SOI) and performance-on-demand architecture (boosted when needed with FD-SOI’s forward back-biasing). It’s the industry’s first general purpose microprocessor family to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (customers can choose between single or dual A7 cores). These technologies, together with our new companion PF3000 power management IC, unleash the potential for dramatically innovative, secure and power efficient end-products for wearable computing and IoT applications.
The initial offering of i.MX 7 was designed (on 28nm bulk) with Cortex-A7 cores operating up to 1 GHz, while the Cortex-M4 core operates at up to 200 MHz. The Cortex-A7 and Cortex-M4 achieve processor core efficiency levels of 100 microWatts (μW) /MHz and 70 μW /MHz respectively.
A Low Power State Retention (LPSR), battery-saving mode can be improved by FD-SOI and consumes only 250 μW, representing a 3x improvement over our previous generation (on 40nm bulk). That’s almost 50% better than our competitors. Plus it minimizes wake up times without requiring Linux reboot, while supporting DDR self-refresh mode, GPIO wakeup, and memory state retention.
The next members of the i.MX 7 series, with FD-SOI dynamic back-biasing, enable different blocks to be reverse or forward back-biased on the fly to attain always-optimal power savings or performance. Additional power optimization features are enabled to achieve leadership power efficiency. We’ve optimized FD-SOI dynamic back-biasing to enable performance-on-demand architecture through which the i.MX 7 series meets the bursty, high-performance needs (this is when forward back-biasing kicks in) of running Linux, graphical user interfaces, high-security technologies like Elliptic Curve Cryptography, as well as wireless stacks or other high-bandwidth data transfers with one or multiple Cortex-A7 cores.
When high levels of processing are not needed, low-power modes kick in with reverse back biasing of the critical subsystems, and the ongoing, real-time work is carried on by the smaller, lower powered Cortex-M4.
All things considered, it’s perhaps no surprise that we expect i.MX 7 series solutions for cost-sensitive markets to be a key driver of our long-term i.MX portfolio expansion.
Our new i.MX 8 series portfolio, based on 28nm FD-SOI process technology, targets highly-advanced driver information systems and other multi-media intensive embedded applications. It incorporates those same key attributes as the i.MX 7, but extends them into realms the industry has never experienced. We believe the i.MX 8 series is poised to revolutionize interactivity in multimedia and display applications across all kinds of industries.
i.MX 8 incorporates innovations in the processor — complex graphics, vision, virtualization and safety to help revolutionize interactivity for a wide range of uses in many, many markets. The capabilities of this family is broad, but one of the places it’s going to be the biggest game-changer is in what is becoming the e-cockpit of your car.
For almost two decades, SOI has shone in the embedded processing world. In addition, NXP counts every major automotive maker in the world amongst its customers for our devices. Entering the new e-cockpit frontier, 28nm FD-SOI is the logical choice in making the i.MX 8 series meet and exceed the stringent requirements of top automotive OEMs for years to come.
The i.MX 8 series leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s. All the FD-SOI advantages discussed above for the i.MX 7 are also being brought to bear here (the power envelope for automotive designers being extremely strict). But in the hot and electrically noisy automotive environment, FD-SOI also plays an important role in ensuring robust operation.
The way we see it, your car’s multimedia centric e-cockpit will revolve around the i.MX 8, a single chip that drives all displays from infotainment to heads-up-displays (HUD) to instrument clusters. It’s optimized for the intelligent transfer of data and information management from multiple subsystems within the IC – as opposed to only delivering raw performance through one or two processing blocks.
For drivers and passengers alike, we’re looking at a very different world: one that includes the spread of advanced heads-up displays, intuitive gesture control, natural speech recognition, augmented reality, enhanced convenience and device connectivity. (I wrote a blog exploring the possibilities last fall – you can read it here.)
And of course, it will be secure from hackers, and fail-safe for critical systems.
From our customers’ standpoint, they can design a single hardware platform and scale it across multiple market segments with the unique approach to pin and software compatibility within the i.MX product families.
The i.MX family has been leveraged in over 35 million vehicles since it was first launched in vehicles in 2010. So with all these new features, and low-power and robust performance, we see a very bright future for FD-SOI and the i.MX 8 in automotive. It’s going to be a great ride.
By Ronald M. Martino, Vice President, i.MX Applications Processor and Advanced Technology Adoption, NXP Semiconductors
The latest generations of power efficient and full-featured applications processors in NXP’s very successful and broadly deployed i.MX platform are being manufactured on 28nm FD-SOI. The new i.MX 7 series leverages the 32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets, where power efficiency is paramount. The i.MX 8 series leverages the 64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, as well as high-performance general embedded and advanced graphics applications.
Over 200 million i.MX SOCs have been shipped over six product generations since the i.MX line was first launched (by Freescale) in 2001. They’re in over 35 million vehicles today, are leaders in e-readers and pervasive in the general embedded space. But the landscape for the markets targeted by the i.MX 7 and i.MX 8 product lines are changing radically. While performance needs to be high, the real name of the game is power efficiency.
The bottom line in chip manufacturing is always cost. A move from 28nm HKMG to 14nm FinFET would entail up to a 50% cost increase. Would it be worth it? While FinFETs do boast impressive power-performance figures, for applications processors targeting IoT, embedded and automotive, we need to look beyond those figures, taking into account:
In fact, both NXP and the former Freescale have extremely deep SOI expertise. Freescale developed over 20 processors based on partially-depleted SOI over the last decade; and NXP, having pioneered SOI technology for high-voltage applications, has dozens of SOI-based product lines. So we all understand how SOI can help us strategically leverage power and performance. For us, FD-SOI is just the latest SOI technology, this time with a design flow almost identical to bulk, but on ultra-thin SOI wafers and some important additional perks like back-biasing.
When all the factors we care about for the new i.MX processor families are tallied up, FD-SOI comes out a clear winner for i.MX SOCs.
For our designers, here’s why FD-SOI is the right solution to the engineering challenges they faced in meeting evolving market needs.
In terms of power, you can lower the supply voltage (Vdd) – so you’re pulling less power from your energy source – and still get excellent performance. Add to that the dynamic back-biasing techniques (forward back-bias improves performance, while reverse back-bias reduces leakage) available with FD-SOI (but not with FinFETs), you get a very large dynamic operating range.
By dramatically reducing leakage, reverse back-biasing (RBB) gives you good power-performance at very low voltages and a wide range of temperatures. This is particularly important for IoT products, which will spend most of their time in very low-power standby mode followed by short bursts of performance-intense activity. We can meet the requirements for those high-performance instances with forward back-biasing (FBB) techniques. And because we can apply back-biasing dynamically, we can specify it to meet changing workload requirements on the fly. [Editor’s note: click here and here for helpful ASN articles with descriptions and discussions of back-biasing, which is also sometimes called body-biasing.]
Devices for IoT also have major analog and RF elements, which do not scale nearly so well as the digital parts of the chip. Furthermore analog and RF elements are very sensitive to voltage variations. It is important that the RF and analog blocks of the chip are not affected by the digital parts of a chip, which undergo strong, sudden signal switching. The major concerns for our analog/RF designers include gain, matching, variability, noise, power dissipation, and resistance. Traditionally they’ve used specialized techniques, but FD-SOI makes their job much easier and results in superior analog performance.
In terms of RF, FD-SOI greatly simplifies the integration of RF blocks for WiFi, Bluetooth or Zigbee, for example, into an SOC.
Soft error rates (SER)* are another important consideration, especially as the size and density of SOC memory arrays keep increasing. Bulk technology gets worse SER results with each technology node, while FD-SOI provides ever better SER reliability with each geometry shrink. In fact, 28nm FD-SOI provides 10 to 100 times better immunity to soft-errors than its bulk counterpart.
Our process development strategy has always been to leverage foundry standard technology and adapt it for our targeted applications, with a focus on differentiating technologies for performance and features. We typically reuse about 80% of our technology platform, and own our intellectual property (IP). Looking at the ease of porting existing platform technology and IP, and analyzing die size vs. die cost, again, FD-SOI came out the clear choice.
In terms of manufacturing, FD-SOI is a lower-risk solution. Integration is simpler, and turnaround time (TAT) is much faster. 28nm FD-SOI is a planar technology, so it’s lower complexity and extends our 28nm installed expertise base. Throughout the design cycle, we’ve worked closely with our foundry partner, Samsung. They provided outstanding support, and very quickly reached excellent yield levels, which is of course paramount for the rapid ramp we anticipate on these products.
In the second part of this article, we’ll take a look at the new i.MX product lines, and why FD-SOI is helping us make those game-changing plays for specific markets.
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* Soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.
From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
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ASN: In which areas do you see SOI giving designers an edge?
MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.
ASN: What is Leti doing moving forward?
MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….
The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.
ASN: What role does Leti play in the SOI roadmap?
MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.
Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.
ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?
MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.
ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?
MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..
In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.
We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.
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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)