Tag Archive BSI

IP Value Starts at the Substrate Level

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.

Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI)  in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.

Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.

In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents.  This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.


So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.

For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.

In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.

One example of how effective our IP policy is came about in 1997 when we contracted with  Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.

Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.

The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.

Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.

Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.

The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level.   We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.

In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.

Soitec has licensed some of its intellectual property portfolio related to back-side illumination technology for image sensors to TSMC

Soitec, a world leader in generating and manufacturing revolutionary semiconductor materials for the electronics and energy industries, has licensed some of its intellectual property (IP) portfolio related to back-side illumination (BSI) technology for image sensors to TSMC. BSI is a key enabling technology in the race to develop small-pixel, high-quality image sensors used in consumer products such as digital cameras, smart phones and other portable electronics.  In this case, the BSI technology uses some of the key process steps of Soitec’s Smart Stacking™ generic technology.

The company also announced that it has received ISO 22301:2012 certification for its Bernin site (near Grenoble, in South-East France). This international standard provides a framework for companies in implementing procedures that will ensure the continuity of their critical businesses during exceptional circumstances. Soitec, the first ISO 22301:2012 certified company in France, has thus received recognition for the quality of its business continuity management system to protect the company from disruptive incidents (fires, unavailability of its information system, pandemics, malicious acts, etc.) by reducing their potential impact on its business.

In solar news, Soitec announced its newest concentrated photovoltaic (CPV) module featuring a record power-generating efficiency of 31.8 percent. The new module, which is already in industrial volume production, has the highest efficiency of any commercial product available for multi-megawatt installations.

What Smart Stacking™ can do for you

Transferring a processed (or partially processed) layer of circuits from one wafer onto another enables innovative new solutions for BSI, MEMS, RF, 3D and more.

Smart Stacking™ is Soitec’s wafer-to-wafer stacking technology platform for partially or fully processed wafers (see Figure 1). It enables the transfer of very thin processed layers in a high-volume production environment.

Smart Stacking is particularly well-suited to advanced semiconductor applications such as Back-Side Illuminated (BSI) image sensors, RF front end modules, MEMS with cavities and emerging 3D integration.

It is a cost-effective, production-proven technology. The platform scales from 150 to 300mm wafer diameters and is compatible with various wafer types (Si, Glass, Fused silica, poly SiC,…).

How it works

The core technologies of Smart Stacking are surface conditioning, low temperature direct oxide-oxide bonding, and wafer thinning.

Figure 1a: Process schematic of the Smart Stacking technology.

To address the thermal budget constraints imposed by stacking of backend of the line (BEOL) processed wafers (i.e. < 400°C), specific pre-bonding surface conditioning and post-bonding thermal treatment were developed to control and increase the bonding strength within the reduced thermal budget window (see Figure 2).

Figure 1b: Acoustic microscope image of a typical wafer that has been stacked using Smart Stacking technology. An entire layer of partially processed circuits has been transferred from another wafer and bonded onto this wafer.

Figure 2: High bond strength at reduced thermal budget

For mobile camera apps

As the demand for CMOS image sensors in mobile devices continues to increase, these devices require continuous pixel shrink for higher resolution and smaller form factor. But as pixel sizes get smaller with traditional processing technologies, the fill factor gets worse and sensor efficiency degrades.

Smart Stacking for BSI image sensors involves bonding the processed wafer face down on a handle wafer, then thinning and exposing the pixel from the back of the wafer.

This provides the most direct path for light into the pixel, providing enhanced efficiency with continuous pixel shrink, minimum distortion and higher yield. Smart Stacking for BSI image sensors is compliant with military reliability standards.

For mobile consumer devices

With the evolution of new cellular standards and band frequencies, the demand for integrating complex RF front end modules is increasing. As the high-frequency performance of CMOS improves with process shrinks, silicon-on-engineered insulating substrates are being implemented for low-power and low-cost RF applications.

Smart Stacking is the enabling technology for silicon-on-engineered insulating substrate solutions. It combines the benefits of state of the art CMOS processes with the very low parasitic capacitance of the insulating substrate, thus providing increased speed, lower power consumption, better linearity, and more isolation than bulk silicon.


As the industry is now entering a next phase on the MEMS technology roadmap, Smart Stacking technology is very well-suited for bonding wafers with pre-etched cavities. The advantages include simplifying the process flow, allowing optimized geometries key for sensitive devices as well as permitting access to thin membranes (e.g. gyroscopes, resonators).

For 3D Integration

3D integration is becoming of critical interest for smaller, faster electronics with extended and new functionalities.

However, achieving a robust mechanical bond without introducing new materials is a requisite for maintaining manufacturing and reliability standards.

Smart Stacking based on low-temperature direct oxide-oxide bonding with sub-micron alignment is a promising path for 3D stacking of processed wafers. This integration achieves a mechanical bond between face-to-face bonded wafers or back-to-face by double transfer.

High-volume now

Soitec’s Smart Stacking technology is currently being leveraged in high-volume manufacturing in partnership with leading foundries and IDMs.

It provides an excellent, cost-effective solution to manufacturing challenges faced by designers as they look to new and improved technologies and integration schemes.

We have combined our core technology know-how, strong IP portfolio, industrial infrastructure, and licensing options to enable and deliver Smart Stacking as a wafer level solution serving applications on the forefront of innovation.

News from Soitec

From Soitec:
• teaming with TowerJazz to offer a backside illumination platform for high-end image sensors
volume production of a new generation of high-resistivity SOI substrates for cellular phone and Wi-Fi markets
• joining forces with CEA-Leti to speed commercial adoption of 3D integration
• supplying SOI substrates to CSMC in China for display and other applications

Production-Worthy Backside-Illuminated Image Sensors

This SOI-based process requires no post-thinning passivation step.

Demand for better cameras in less expensive mobile phones is pushing researchers to find higher performance image sensor solutions for that cost-conscious end of the market. Last year, a research team from MagnaChip and JPL presented a paper at the International Electron Devices Meeting (IEDM 2007, Washington, DC) demonstrating the development of a production-worthy, backside-illuminated (BSI) monolithic sensor with 2.2 µm pixels. We used low-cost, standard fabrication techniques and available, mature technology modules. Compared to a conventional, frontside-illuminated (FSI) sensor, our 2-megapixel (MP) sensor exhibited comparable dark current and noise, but much higher quantum efficiency (QE) and sensitivity.

As shown in the figure, the height of the optical stack is much lower for the BSI pixel, leading to significant advantages in the effective pixel f/ (effective focal length) number. Furthermore, thanks to the high refractive index of silicon, light converges at the center of the pixel, and the optical energy is well-contained therein.

Performance of the MagnaChip 2-Megapixel Imager

Starting with SOI

We began the fabrication process with SOI wafers, which enables the oxide to act as an etch-stop for accurate backside thinning. A special SOI layer configuration suppressed dark current generation at the BOX interface. This prevents QE loss at short wavelengths, reduces cross-talk, and provides a low-resistance backplane. An imager-compatible bulk-CMOS process was then used for fabrication. Before thinning, a handle wafer offering mechanical support was bonded to the processed wafer using a low temperature oxide-oxide process.

We connected the front-side metals to the bond pads on the (exposed) backside using tungsten-filled and liner-oxide-isolated through-silicon vias (TSVs). However, we did not use “3D” stacked technologies such as multi-wafer vias or bonding of multiple wafers with sub-micron alignment. This significantly enhanced manufacturability.

Next, we used backgrind to remove most of the silicon, followed by a dry silicon etch. This wafer-level thinning produced a thinned monolithic imager with a planar back surface, which is important for subsequent color filter and microlens processing. The processing finished with the connection of the backside bond pads to the TSVs, standard oxide/nitride passivation, and hydrogen anneal. We did not apply any special anti-reflective coating. The die assembly used a simple wire-bonded package, which is similar to that used in an FSI part.

Clear advantages

As seen in the table, the BSI approach has a clear advantage over FSI in key areas. On a black and white sensor, the broadband QE (81% for BSI) was 2.7x better than FSI. Other parameters were comparable to or better than FSI. The fact that the mean dark current value and the hot pixel counts were similar for BSI and FSI indicates that we achieved a high-quality back interface without any post-thinning backside treatment.

Our results showed that a BSI sensor can capture a bright image using just one third of the light required by an FSI sensor. In practical terms, with BSI those birthday cake-and-candle pictures should have a much better chance of turning out – even when the lights are dimmed.

The effective optical stack height, which is the distance between the microlens and the absorbing silicon layer, is much smaller in the case of BSI. The dotted line shows where photon absorption begins. (Dimensions are in microns)

Tom Joy has worked in the CMOS industry for over twenty-eight years, including Hewlett Packard, Chartered Semiconductor, Agilent Technologies and Magnachip Semiconductor. For the last four years, he has been workinng on image sensor process development, and most recently on SOI based back illuminated sensors. He has a Ph.D. EE from the University of Notre Dame.

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3D at the Wafer Level

Soitec’s core technologies are building blocks for 3D integration.

At the wafer level, molecular bonding techniques and Smart Cut technology add significant value to 3D integration. A good application for these building blocks is backside illuminated image sensors (BIS), which is probably the most mature 3D technology and close to mass production.

For standard front side illuminated imagers the photodiode quantum efficiency (QE) suffers with decreasing pixel size and an increasing number of metal layers. The industry has identified BIS as the path to keep increasing pixel density, resolution and speed without sacrificing QE.

After imager fabrication, the processed wafer is bonded to a handle wafer and the original substrate is thinned down leaving only few microns of silicon and exposing the photodiodes. In this way the exposure to light of the photodiodes can be maximized, translating into a very high QE.

Molecular bonding and IC layer transfer are enabling techniques that make possible the fabrication of BIS without die deformation and post-processing by the imager maker. We have developed low-temperature bonding techniques that are compatible with the aggressive wafer grinding and thinning processes and meet the requirements for IC post processing.

BIS imagers take full advantage of this core know-how. Moreover, if SOI wafers are initially used to fabricate the imagers then the overall process becomes less complex and more robust. The buried oxide of the SOI wafer acts as a built-in etch stop during the substrate removal process and protects the active Si layer of the photodiodes.

Bonding expertise

Stacking layers of CMOS devices pre-interconnect formation is another very interesting application for Smart Cut technology and low temperature molecular bonding. The challenges here are even bigger because the transferred layer will go through a full CMOS fabrication step.

The pre-existing CMOS device layer limits bonding temperatures to below 850°C. If the underlying layers happen to already have interconnects the situation is even tougher because bonding temperatures cannot go beyond 450°C.

The knowledge and experience in the development of engineered substrates, with buried metal structures and strong CTE mismatch, brings valuable synergy to this 3D technology, an enabling Soitec know-how.
Finally, fully processed wafer-to-wafer bonding including wafer-to-wafer alignment is a building block in development that will enable more complex 3D architectures.

Smaller Pixels, Brighter Pictures

ST’s 3-megapixel back-illuminated image sensor for digital cameras leverages SOI, direct wafer-level bonding and thinning technologies, improving 1.45 x 1.45 µm² pixel quantum efficiency over 60%.

To meet consumer demand for higher-quality digital cameras embedded in a widening array of mobile devices, designers need image sensors with very small pixels (higher resolution, smaller, cheaper and lower power) that maximize the available light.

In response, the image sensor industry is coming out with a new generation of back-illuminated CMOS image sensors. In contrast to the current generation of front-illuminated devices, the back-illumination scheme moves the electronics to the bottom of the stack, so the light enters the device unimpeded. While this enables high-quality pictures or video even under low light conditions and simplifies some aspects of the design (particularly of the metal layers), it also introduces cost-effective manufacturing challenges.

STMicroelectronics has demonstrated the feasibility of manufacturing 3-megapixel CMOS image sensors with a very small pitch (just 1.45µm x 1.45µm) in a back-illuminated design. We have attained a high quantum efficiency (QE) of >60%. The QE indicates the percentage of photons that are converted into electrons.

The back-illumination design starts with an SOI wafer. We evaluated several SOI thicknesses in order to find an optimal balance between QE and crosstalk.

Crosstalk quelled

In a back illumination scheme, you don’t have the problem of the electronics getting in the way of the light’s path; however, the electrons generated by the light still have to reach the photodiode. Different colored lights have different wavelength ranges; blue light for example, which has a short wavelength, is particularly tricky.

Figure 1. Thicker SOI layers are preferable: higher light absorption and higher QE.

The longer the photo-generated electrons have to travel, the greater the chance that they’ll diffuse into neighboring pixels, thereby increasing electrical crosstalk. A thicker SOI layer increases QE, but it also increases crosstalk – hence the need for finding the optimal balance. We have determined this balance in the context of a manufacturable product (see Figure 1)

Lowering dark current

Dark current is essentially leakage current that flows even when the device is not operating. It can really deteriorate image quality badly. As such, it is a challenge in all CMOS image sensors, whether you’re using front or back illumination. Dark current is linked to crystalline defects in the silicon. The quality of the wafer-bonding interface, especially between silicon and the oxide interface, is critical to diminishing dark current.
We have achieved a mean low dark current of 1e/s at 25°C due to dedicated frontside and backside process steps such as a p+ pinning layer and thermal treatment. Other parameters such as conversion gain, lag and temporal noise are comparable to state-of-the-art frontside image sensors.


In our back-illumination scheme, after the final metal layers are created, a passivation layer and subsequent wafer-bonding layer (WBL) are deposited. The WBL is planarized and a support wafer is bonded to the processed wafer, then thinned through a subsequent grind-back.

We have demonstrated the manufacturing feasibility, and are now concluding work related to further cross-talk reduction as well as color filter and micro-lens processing.

Image from a 3MP back-illuminated array with 1.45µm pixel pitch

With these image sensors embedded in the next generation of cell phone cameras, dark and fuzzy snapshots should soon be a thing of the past

Process flow

  • SOI wafer
  • CMOS image process
  • Wafer bonding layer (WBL) and preparation
  • Wafer bonding and backside grinding
  • Anti-reflective coating (ARC)
  • Pad opening
  • Color filters and micro-lens

Acknowledgements: Tracit Technologies for wafer bonding and thinning studies; the CEA-LETI process teams; and the STM front-end technology and manufacturing group.

Reference: “A 3 Mega-Pixel Back-illuminated Image Sensor in 1T5 Architecture with 1.45 μm Pixel Pitch.”, Francois Roy*, Perceval Coudrain*, Xavier Gagnard*, Josep Segura*, Yvon Cazaux*, Didier Herault*, Nicolas Virollet*, Norbert Moussy**, Benoit Giffard**, Pierre Gidon** (* FTM Imaging, STMicroelectronics, Crolles, France; ** CEA-LETI-MINATEC, Grenoble, France). 2007 International Image Sensor Workshop. Jens Prima

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Figure 1. Light passing through a thinned silicon wafer

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