Suddenly they’re everywhere: opportunities to learn more about FD-SOI and RF-SOI. Over the next couple of months you can find them in China, Europe and Silicon Valley. Some are organized by the SOI Consortium, others by foundries and partners.
Here’s a quick listing with links for more info on how to register for upcoming China events.
Nanjing, China. SOI Workshop & Tutorial, 21-22 September 2017.
Organized by the Nanjiing city government and the SOI Consortium. The first day is packed with top presenters, including NXP, ST, Samsung, GlobalFoundries, Cadence, Synopsys, as well as design and IP partners. The second day is a tutorial covering FD and RF-SOI, as well as imagers and photonics. Sessions will be given by Synopsys, Silvaco, Incize, ST, Soitec, and the SOI Consortium.
Shanghai, China. FD-SOI Tutorial. 25 September 2017.
Organized by VeriSilicon and the SOI Consortium. Tutorial covers: tech overview; analog/RF/mixed-signal; neuromorphic and IoT processors; EDA & design process flow; eNVM; and using forward & reverse body bias. Session leaders are from SOI Consortium, GlobalFoundries, ST, Soitec, UCBerkley, Evaderis and Greenwaves.
Shanghai, China. FD-SOI Forum. 26 September 2017.
Organized by VeriSilicon, Simgui, SIMIT and the SOI Consortium. The focus is on Ultra Low Power computing, RF, EDA/IP ecosystem growth and accelerating adoption. Presentations by Dr. Xi Wang of China’s SIMIT/CAS, GF’s CEO Dr. Sanjay Jha, Samsung’s EVP & GM Dr. ES Jung, as well as from Ron Martino, VP & GM from NXP; Paul Boudre, CEO of Soitec; IBS, NSIG, GF, UC Berkeley, VeriSilicon, Cadence and Synopsys. There’s also a very impressive line-up for a final panel discussion.
Shanghai, China. International RF-SOI Workshop. 27 September 2017.
Organized by Simgui, Sitri, SIMIT, VeriSilicon and the SOI Consortium. Now in its 5th year, this conference has grown very quickly: last year it was in a ballrooom with standing room only (note that RF-SOI chips are now found in pretty much every smart phone on the planet). The focus this year is on IoT, mobile, 5G connectivity, and mmW. Keynotes are from TowerJazz, Sony and China Mobile. Presentations from RDA, SMIC, Simgui, Will-Micro, GF, Soitec, Silvaco and Screen.
BTW, for events organized by the SOI Consortium, many of the presentations are available on the website (from Tokyo this summer, for example, and Silicon Valley last spring – and going on back through 2015). Scroll down through Events to Past Events to find them.
Day 2 of the recent SOI Workshop in Tokyo was dedicated to the “Convergence of IoT, Automotive through Connectivity”. Many of the presentations are now posted and freely available – click here to see the full list.
It was a really full day, so the recap in this post covers about half of the Day 2 presentations. My next post will cover the rest of them. (In case you missed it, Day 1 was covered in my previous post – you can read it here.)
Another Sony GPS Win!
The day kicked off with a talk by Sony GM Kenichi Nakano, entitled Sony Semiconductor Low-Power IoT Solution. He reminded the audience that Sony started looking at FD-SOI in 2013, and announced at ISSCC last year (the paper’s available from the IEEE – click here). Power, he said, is everything.
And that low-power GPS in Casio’s latest Pro Trek Smart watch, the WSD-F20? It’s based on Sony’s new CXD5602 – and that’s on FD-SOI, to which they give largely give credit for the >75% reduction in power from the previous generation.
Samsung: Surf’s Up!
FD-SOI is mature, and they’re ready to surf it, said Principle Designer at Samsung Foundry Marketing, Yongjoo Jeon. But, he added, they’ll continue to evolve it.
Covering a wide range of applications, he sees FD-SOI as a key in the 4th industrial revolution. In terms of power/performance, the “…excellent short channel effect enables better performance and lower power than bulk technology.” And, “Body bias enhances further performance [FBB – forward body bias] and power reduction [RBB – reverse body bias].”
That provides some unique benefits, he pointed out.
in automotive, it’s safety: the physical dielectric isolation is almost free from SER (soft error rate)
for analog/RF, the long channel gain is more significant with excellent noise immunity
for every application, lower doping enhances variation immunity
Samsung reached high yield (defect density D0<0.2) very quickly, and ramped rapidly to mass production (which is where they are with NXP as of Q1/17). This, he said, shows the maturity of their 28FDS FD-SOI technology.
Then he turned to design. Samsung (which does btw, offer Design Services) has an IP portfolio that is wide and deep, with a strong, well-established reference flow, supported by both Cadence and Synopsys.
In terms of RF, 28FDS has better fT than 28nm bulk. The physical isolation of the SOI structures enables a “no guard ring” approach, and specific RF offerings include LDMOS for PAs (power amplifiers). Samsung is supporting a new mm-Wave Pcell, which will be added in the V1.1 PDK.
Samsung is also adding eMRAM (embedded magnetoresistive RAM – it’s already yielding at 60%), as they see 28nm is probably the last node for eflash. “We’re very proud of these technologies,” he said.
Samsung’s next generation of FD-SOI will be 18nm, which provides a 20% increase in performance, a 40% decrease in power, and a 30% reduction in logic area.
Cadence EDA & IP Update
FD-SOI enablement usually means PDKs and tech files, noted Jonathon Smith, Director of Strategic Alliances at Cadence. But for deep benefits, you need to work with the foundries on characterizing libraries, and that’s just what Cadence is doing with both Samsung and GlobalFoundries, he said.
He gave a very frank and interesting talk entitled Enabling an Interconnected Digital World: Cadence EDA & IP Update. IoT, he noted, will include a lot of mixed-signal and complex packaging. Customers need modular reference flows, and they want flexibility and multiple foundry nodes. For FD-SOI, Cadence has been working on PDK enablement, tool readiness and design tools for several years. There is one database for both digital and analog.
For Samsung’s 28FDS, everything from logic synthesis to sign-off and analog tools are certified. In fact Cadence recently announced its custom/analog tools and full-flow digital and signoff tools have achieved Samsung certification for the PDK and foundation library (see the press release here).
For GlobalFoundries 22FDX, Cadence is certified across the entire design flow, and the reference flows are downloadable.
In terms of IP, he acknowledged that what Cadence has is not very extensive, so they are working with both partners and competitors. However, he did point out that their Tensilica IP for automotive is gaining traction: it is used in the Dreamchip ADAS chip fabbed on GF’s 22FDX, for example.
Wait, There’s More!
Day 2 in Tokyo was really packed with excellent presentations – too much for just one post. See Part 2 of my Day 2 coverage for highlights from Leti, GlobalFoundries, Soitec, MIPS/Imagination and more.
Looking for insight into the state of SOI and FD-SOI in Japan? Want to find out who’s doing IP and design support? Wondering about the major drivers? If you’re in the region, you can find out – and network with the top players in the ecosystem – at the 3rd Annual SOI Tokyo Workshop. The SOI Consortium has put together a great line-up of speakers.
This year it will take place over the course of two days, May 31st and June 1st . Click here for registration information on the SOI Consortium website. (While there is no charge for the event, please register in advance to guarantee your place.) You’ll find the full program here. A brief summary follows.
The first day – Wednesday, May 31st – is an afternoon session hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem. Speakers include top executives from GlobalFoundries and IP/design leaders Synopsys, Silvaco, Invecas and Attopsemi, as well as the SOI Consortium.
It will take place on the 25th floor of the Yokohama Landmark Tower. The reception at the end of the day will give participants an extended opportunity to network with the speakers and other attendees.
The second day of the workshop – Thursday, June 1st – will focus on Convergence of IoT, Automotive Through Connectivity. This full-day workshop, with talks by top executives in the industry, will be held at Tokyo University’s Takeda Hall.
It kicks off with talks on ultra-low power applications from Sony IoT and Samsung. Next up, speakers from Imagination/MIPS, IHSMarkit and Leti address automotive technologies. After lunch, the first group of speakers from GlobalFoundries, Cadence, Nokia and ST tackle IoT, Connectivity and Infrastructure. The day wraps up with talks by some of the key supply chain providers: Applied Materials, Soitec and Screen.
Coffee breaks and lunch will give attendees and speakers time for further discussion.
This is a great opportunity – don’t miss it!
12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here).
The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. “We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”
Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”
The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”
GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch.
The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.
“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”
Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here).
Simultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.
Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services.
Initial FDXcelerator Partners have committed a set of key offerings to the program, including:
Additional FDXcelerator members will be announced in the following months.
If you’re headed to DAC (June 5-9 in Austin,TX) and are interested in learning more about FD-SOI, there will be lots of opportunities. Here’s a quick rundown.
Synopsys (stands 149 & 361) and GlobalFoundries are hosting a dinner on Tuesday evening (7 June) at the Austin Hilton around the theme, What’s Important for IoT—Power, Performance or Integration… or All of the Above? They’ll be talking about how FD-SOI addresses these challenges. Panel members will discuss design techniques to push the envelope on low power, low leakage, burst performance and optimal cost to enable the design of innovative IoT-based products. Attendance is free, but registration is required and seating is limited. Click here to go to the registration site.
Samsung Foundry (stands 607 and 706) and partners will be doing a number of presentations on Samsung’s 28nm FD-SOI offering, 28FDS. They’ll be showcasing 28FDS wafers, offering multiple presentations by Samsung Foundry’s experts, and sharing solutions built on the 28FDS technology by their Foundry Ecosystem partners. As noted in ASN coverage of the recent SOI Consortium event in San Jose (read it here), Samsung is now in commercial production of 28FDS. They have a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast.
IP Track: Minimizing SOC Power Consumption: A Top Down Design Methodology or Bottoms Up Starting With the Process Selection Problem? Panelists include Carlos Mazure (of the SOI Industry Consortium & Soitec) and Ron Martino (of NXP) Monday, June 6th from 4:00pm – 5:00pm in Ballroom G.
Variation-Aware Design at Advanced and Low-Power Processes. Panelists include Azeez Bhavnagarwala (ARM), Glen Wiedemeier (IBM), John Barth (Invecas) and Jeff Dyck (Solido). Monday, June 6th from 10:30am – 11:30am, Room: 9BC.
Presentation 9.1 Impact of Leakage & biasing on Power in 22FDX Process. By Krishnan Subramanian et al (Invecas) and Sankar Ramachandran – (Apache Design). Monday, June 6th, 3:30pm – 4:00pm, Ballroom G.
Presentation 50.4 Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search. By Johannes M. Kuehn et al (Eberhard Karls Univ. Tubingen & Keio Univ.) Wednesday, June 8th, 1:30pm – 3:00pm, Room: 17AB. This presentation will be given at 2:15. (You can also get the paper from the ACM site here.)
101.12 Parametric Exploration for Energy Management Strategy Choice in 28nm UTBB FDSOI Technology. By Jorge Rodas et al (CEA-Leti Minatec & Univ. Grenoble Alpes) Work-in-Progress (WIP) poster session, Wednesday, June 8th, 6:00pm – 7:00pm, Room: Trinity St. Foyer
Stands & More
Cadence Theater (stand 43 – full schedule here)
Tuesday, June 7th
Wednesday, June 8th
Leti (stand 1818) – a driving force behind all things SOI, stop by to learn more about Silicon Impulse®, their FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume (more here).
And finally, the opening keynote on Monday morning (at 9:15 in Ballroom A) will be given by NXP’s Lars Reger, CTO of their Automotive Business Unit. The topic is Revolution Ahead – What It Takes to Enable Securely Connected, Self-Driving Cars. When it comes to automotive, NXP is the original SOI pioneer, dating to back to 1999. NXP’s sold billions of SOI-based chips for high-voltage automotive applications – they’re used by virtually every carmaker on the planet (read about the early history here and here).
And now with the Freescale acquisition, NXP is full speed ahead with FD-SOI applications processors. If you missed it, you’ve got to read the recent ASN series by Ron Martino (NXP’s VP for i.MX Applications Processor and Advanced Technology Adoption). He explains why they chose 28nm FD-SOI, and exactly what it does for the i.MX 7 series (32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets) and i.MX 8 series (64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, as well as high-performance general embedded and advanced graphics applications) Click here to read it now. NXP gave a demo of the I.MX 8 at FTF 2016 a few weeks ago – check out the video they posted on Twitter here.
If you go to DAC and you have a Twitter account, be sure to tweet #FDSOI and #53rdDAC – @followASN will be happy to pass it along!
The #1 take-away message from the recent FD-SOI Symposium in San Jose is that “FD-SOI is the smart path to success”. With presentations echoing that theme by virtually all the major players – including (finally!) ARM – to a packed house, it really was an epic day for the FD-SOI ecosystem. The presentations are now starting to be available on the SOI Consortium website – click here to see them (they’re not all there as of today, though, so keep checking back).
Since there’s so much to cover, we’ll break this into two parts. This is Part 1, focusing on presentations related to some of the exciting products that are hitting the market using 28nm FD-SOI. Part 2 will focus on the terrific presentations related to 22nm FD-SOI. In future posts we’ll get into the details of many of the presentations. But for now, we’ll just hit the highlights.
So back briefly to FD-SOI being smart. (A nice echo to the Soitec FD-SOI wafer manufacturing technology – SmartCutTM – that make it all possible right?) It started with the CEO of Sigma Designs (watch for their first IoT products on FD-SOI coming out soon) quipping, “FD-SOI is the poor man’s FinFET.” To which GlobalFoundries’ VP Kengeri riffed that really, “FD-SOI is the smart man’s FinFET”. And NXP VP Ron Martino, summed it up saying, “FD-SOI is the smart man’s path to success”. Yes!
Samsung now has a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast, said Kelvin Low, the company’s Sr. Director of Foundry Marketing. His presentation title said it all: “28FDS – Industry’s First Mass-Produced FDSOI Technology for IoT Era, with Single Platform Benefits.” They’ve already done 12 tape-outs, are working on 10 more now for various applications: application processor, networking, STB, game, connectivity,…., and see more coming up fast and for more applications such as MCU, programmable logic, IoT and broader automotive. It is a mature technology, he emphasized, and not a niche technology. The ecosystem is growing, and there’s lots more IP ready. 28nm will be a long-lived node. Here’s the slide that summed up the current production status:
As you see, the production PDK with the RF add-on will be available this summer. Also, don’t miss the presentations by Synopsys (get it here), which has repackaged the key IP from ST for Samsung customers, Leti on back-bias (get it here), Ciena (they were the Nortel’s optical networking group) and ST (it’s chalk-full of great data on FD-SOI for RF and analog).
If you read Ṙon’s terrific posts here on ASN recently, you already know a lot about where he’s coming from. If you missed them, they are absolute must-reads: here’s Part 1 and here’s Part 2. Really – read them as soon as you’re done reading this.
As he noted in his ASN pieces, NXP’s got two important new applications processor lines coming out on 28nm FD-SOI. The latest i.MX 7 series combines ultra-low power (where they’re dynamically leveraging the full range of reverse back biasing – something you can do only with FD-SOI on thin BOX) and performance-on-demand architecture (boosted when and where it’s needed with forward back-biasing). It’s the first general purpose microprocessor family in the industry’s to incorporate both the ARM® Cortex®-A7 and the ARM Cortex-M4 cores (the series includes single and dual A7 core options). The i.MX 8 series targets highly-advanced driver information systems and other multimedia intensive embedded applications. It leverages ARM’s V8-A 64-bit architecture in a 10+ core complex that includes blocks of Cortex-A72s and Cortex-A53s.
In his San Jose presentation, Ron said that FD-SOI is all about smart architecture, integration and differentiating techniques for power efficiency and performance. And the markets for NXP’s i.MX applications processors are all about diversification, in which a significant set of building blocks will be on-chip. The IoT concept requires integration of diverse components, he said, meaning that a different set of attributes will now be leading to success. “28nm FD-SOI offers advantages that allows scaling from small power efficient processors to high performance safety critical processor,” he noted – a key part of the NXP strategy. Why not FinFET? Among other things, it would bump up the cost by 50%. Here are other parts of the comparison he showed:
For NXP, FD-SOI provides the ideal path, leading to extensions of microcontrollers with advanced memory. FD-SOI improves SER* by up to 100x, so it’s an especially good choice when it comes to automotive security. Back-biasing – another big plus – he calls it “critical and compelling”. The icing on the cake? “There’s so much we can do with analog and memory,” he said. “Our engineers are so excited!”
You know how using mapping apps on your smartphone kills your battery? Well now there’s hope. Sony’s getting some super impressive results with their new GPS using 28nm FD-SOI technology. These GPS are operated at 0.6V, and cut power to 10x (!) less than what it was in the previous generation (which was already boasting the industry’s lowest power consumption when it was announced back in 2013).
In San Jose, Sony Senior Manager Kenichi Nakano presented, “Low Power GPS design with RF circuit by the FDSOI 28nm”, proclaiming with a smile, “I love FD-SOI, too!” All the tests are good and the chip is production ready, he said. In fact, they’ve been shipping samples since March.
As of this writing, his presentation is not yet posted. But til it is, if you’re interested in the background of this chip, you can check out the presentation he gave in Tokyo in 2015 here.
SERDES (Serializer/Deserializer) IP is central to many modern SOC designs, providing a high-speed interface for a broad range of applications from storage to display. It’s also used in high-speed data communications, where it’s had a bad rep for pulling a huge amount of power in data centers. But Analog Bits has been revolutionizing SERDES IP by drastically cutting the power. Now, with a port to 28nm FD-SOI, they’re claiming the industry’s lowest power.
In his presentation, “A Case Study of Half Power SERDES in FDSOI”, EVP Mahesh Tirupattur described FD-SOI as a new canvas for chip design engineers. The company designs parts for multiple markets and multiple protocols. When they got a request to port from bulk to 28nm FD-SOI, they did it in record time of just a few months, getting power down to 1/3 with no extra mask steps. Plus, they found designing in FD-SOI to be cheaper and easier than FinFET, which of course implies a faster time to market. “The fabs were very helpful,” he said. “I’m pleased and honored to be part of this ecosystem.”
Listening to a presentation by Stanford professor Boris Murmann gets you a stunning 30,000 foot view of the industry through an amazing analog lens. He’s lead numerous explorations into the far reaches of analog and RF in FD-SOI, and concludes that the technology offers significant benefits toward addressing the needs of: ultra low-power “fog” computing for IoT (it’s the next big thing – see a good Forbes article on it here); densely integrated, low-power analog interfaces; universal radios; and ultra high-speed ADC. Get his symposium presentation, “Mixed-Signal Design Innovations in FD-SOI Technology” here.
So, it was a great day in San Jose for 28nm FD-SOI. Next in part 2, we’ll look at why it was also an epic day for 22nm FD-SOI. Be sure to keep checking back at the SOI Consortium website, as more presentations will become available in the days to come.
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*SER = Soft Error Rates – soft errors occur when alpha or neutron particles hit memory cells and change their state, giving an incorrect read. These particles can either come from cosmic rays, or when radioactive atoms are released into the chips as materials decay.
Registration is open for GlobalFoundries’ technical webinar, “How to Implement an ARM Cortex-A17 Processor in 22FDX 22nm FD-SOI Technology” (click here to go to the registration page). The webinar will cover the optimal steps to successfully implement ARM® Cortex®-A Series* processors using 22FDXTM 22nm FD-SOI technology.
GF Design Enablement Fellow Dr. Joerg Winkler will address:
This webinar will take place April 26, 2016 at10:00 am Pacific Time.
BTW, GF’s already done quite a few 22FDX-related webinars and videos – click here to see the current list.
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* Per ARM, “Cortex-A processors are specifically designed to execute complex functions and applications such as those required by consumer devices like smartphones and tablets. Their performance efficiency is also making them an increasingly popular choice for servers and enterprise applications where large core clusters can be combined for optimal solutions.”
The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.
To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.
08:00AM – 09:00AM – Registration
08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium
09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything
09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO
10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption
10:30AM – 10:50AM – Coffee Break
10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit
11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP
11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing
12:20PM – 1:40PM Lunch
1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division
2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO
2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP
3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division
3:30PM – 4:00PM – Coffee Break
4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager
4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering
4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”
5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D
5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse
6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium
Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:
Doubletree Hotel San Jose
2050 Gateway Place
San Jose, California 95110, USA
If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org.
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 3, we’ll talk about the ecosystem. (In part 1 we talked about technology readiness, and in part 2, we talked about design.)
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ASN: Let’s talk a little more about IP availability.
Axel Fischer: The availability of IP is key for engaging these market segments. The technology itself is ready. The gating item often is the IP element.
Kelvin Low: The IP element is broadly ready. But we’re not stopping there. We’re enhancing the IP and adding on new suppliers. Most of them we can’t name yet just because of timing. But we can confidently say that multiple new IP suppliers are coming online, and many more have started to inquire about how they can get onboard.
ASN: In terms of the ecosystem, what remains to be done?
KL: The ecosystem can never end. Enhancements will always be welcome. More support – there are so many other EDA software companies out there available. We will enable them if there is a customer behind them. IP are dictated by the standards. As long as the product requires that, we’ll continue to look for partners to develop the IP.
KL: Back to one of the strategic decisions we made. We have immediately made available what ST Micro has in terms of IP portfolio to our customers. Then continuously build this ecosystem according to the new customers that we’re acquiring. ST Micro has developed these IPs for their own internal products, and they were gracious enough to allow these IPs to be opened up to be used by all customers without restriction.
As a group, as an ecosystem, we have to be more proactive in educating the market. What we’ve seen so far, whether it’s an initiative by Leti or an initiative by the SOI Consortium, these are very helpful. Now you have so many more knobs that you can play with, for designers we have to prepare all these PVT – which is process, voltage, temperature, and timing points so they can actually use it. It’s just a matter of preparation needed from our end, working with the ecosystem. The EDA tools must be optimized to make it as seamless, as transparent as possible.
ASN: Any closing thoughts?
KL: 28FDSOI is real. Samsung is committed. The technology is qualified already. The ecosystem is ready and expanding. This is working stuff. It’s not a powerpoint technology.
This is the last installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 2 on design considerations (click here).
For this 3-part series, ASN spoke with Kelvin Low, senior director of marketing for Samsung Foundry and Axel Fischer, director of Samsung System LSI business in Europe about the company’s FD-SOI offering. Here in part 2, we’ll talk about design. (In part 1, we talked about Samsung’s technology readiness. In part 3, we’ll talk about the ecosystem.)
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ASN: Let’s start by talking about value. What do you see as the key advantages of 28nm FD-SOI?
Kelvin Low: FD-SOI is wide-ranging. What I mean by this is for the designers, there are many design knobs available that you can use to achieve either high performance or ultra low power. That’s a an extremely valuable and important proposition. The wide dynamic performance-power range is achieved with FD-SOI’s body biasing ability. Though bulk technologies allow body biasing, it has a comparatively much narrower range.
Another key benefit is the super analog gain and properties of FD-SOI. I think moving forward, we’ll probably start to see more customers that are analog-centric. Later on, we’ll see this as one of the key value propositions of FD-SOI. Today, there’s still a lot of digital customers that we’re engaged with right now. The analog customers are still not yet aggressively migrating to [[more advanced]] technology nodes, but when they come, this will be an important distinction in FD-SOI vs. bulk.
Another important distinction not related to power-performance-area is the robustness of the reliability. This is a well-proven fact that FD-SOI is much more robust for soft-error immunity as compare to bulk. So anything that needs radiation protection (for example, military, aerospace – but those are not really the high-volumes), as well as automotive products, you’ll see value of better SER immunity as compared to bulk. Not just memory SER but logic SER. There are available design techniques to overcome / account for that. For example, if you design to overcome SER, you incur overhead in area for example. With FD-SOI, this is intrinsic, so you don’t need design tricks to suppress it.
ASN: When should designers consider using 28nm FD-SOI as opposed moving to 14nm FinFET or choosing another 28nm technology?
KL: By virtue of one being 28 and the other being 14, if you do need a lot of logic feature integration, or die-size reduction, 14nm will obviously become more necessary. If you just are looking for power savings, both 14nm FinFET and 28nm FD-SOI are fully depleted in nature, so both are able to operate with a lower power supply. So those are similarities. 14nm FinFET does provide higher performance compared to 28nm by virtue of how the process is constructed. Lastly, cost, which is related to the number of double-patterning layers – at 28nm, avoiding all the expensive double-patterning layers and 14nm having double-patterning being necessary for all the area scaling – that presents itself as a real difference. The end-product cost can also determine the choice of the technology selection.
Axel Fischer: The end-product cost, plus as well the investments from the customer side: the customer has to make a certain investment to develop the chip in terms of overall cost. If you look at photomask payment, NRE* and so on – this is weighting strongly, more and more as you go forward with advanced node technologies. There’s a set of customers that are feeling very comfortable to stay on the 28nm node.
KL: There are several 28nm flavors. There’s Poly-SiON, there’s HKMG, and there’s HKMG-FD-SOI. In terms of performance, there’s really a very clear distinction. In terms of power, you see a more radical power reduction with FD-SOI. In chip area scaling, I’d say roughly the same between HKMG and FD-SOI. This is dictated not so much by the transistor but by the overall design rules of the technology. So, 14nm is the higher cost point. 28nm is a much lower cost point, so overall a given budget that a customer has can determine whether 14nm is usable or otherwise. We have to sit down with the customer and really understand their needs. It’s not just trying to push one over the other solution. Based on their needs, we’ll make the proper recommendations.
ASN: Can designers get started today?
KL: We are moving FD-SOI discussions with customers to the next phase, which is to emphasize the design ecosystem readiness. So what we’ve been working on, and we really appreciate ST Micro’s support here, is to kick-start market adoption. We have access to ST Micro’s foundation library, and some of their foundation and basic IPs. Here, Samsung is distributing and supporting customers directly. They need to only work with us, and not with ST Micro. So they have access to the IP through us. We also provide design support, and we have additional IPs coming in to serve the customers from the traditional IP providers.
Many designers are new to body biasing. Fortunately, there are a couple of design partners that can help in this area. Synapse being one of them; Verisilicon another. Already, they have put in resources and plans and additional solutions to catalyze this market. In short, the PDK is available today, and the PDK supporting multi tools – Synopsys, Cadence and Mentor – are all available for download today. Libraries are also all available for download.
There’s nothing impeding designers from starting projects now. This is why we believe that 28FDSOI is the right node, because we are enabling the market to start projects today. If we start something else down the road, like a 14nm FD-SOI, for example, or something in between, the market will just say, hey, we like your transistor, we like your slides, but I have nothing to start my project on. So that is bad, because then it becomes a vicious cycle. We believe we have to enable 28nm designs now. Enable customers to bring actual products to the market. Eventually from there you can evolve 28 to something else.
ASN: Let’s talk some more about design considerations and body biasing, how it’s used and when.
KL: Both 14nm FinFET and 28nm FD-SOI are fully depleted. One unique technology value of fully-depleted architecture is the ability to operate the device at lower power supply. So power is the product of CV²/frequency. If you can operate this chip at lower power supply, you get significant dynamic power savings. FinFET does not have a body effect, so you cannot implement body biasing – it’s just not possible.
FD-SOI, on the other hand, has this extra knob – body biasing – that you can use. With reverse body bias (RBB), you can get much lower leakage power. If you want more performance, you can activate the FBB to get the necessary speed. Again, this is not possible with FinFET. So that will be one distinction. It depends on how you’re using your chip. It all depends on the system side, or even at the architecture side, how is it being considered already. If you’re already very comfortable using body biasing, then going to FinFET is a problem, because you’ve lost a knob. Some would rather not lose this knob because they see it as a huge advantage. That doesn’t mean you can’t design around it, it’s just different.
There are already users of body biasing for bulk. For customers that already use body biasing, this is nothing new. They’re pleased to now have the wider range, as opposed to the more narrow range for bulk.
AF: And probably going to FinFET is more disruptive for them. With FinFET, you have double-patterning considerations, etc. More capacitance to deal with.
ASN: Porting – does FD-SOI change the amount of time you have to budget for your port?
KL: If a customer already has products at 28nm, and they’re now planning the next product that has higher speed or better power consumption – they’re considering FinFET as one option, and now maybe the other option available is 28nm FD-SOI. The design learnings of going to FinFET are much more. So the port time will be longer than going to 28nm FD-SOI. We see customers hugely attracted because of this fact. Now they’re trying to make a choice. If it’s just a time-to-market constraint, sometimes FinFET doesn’t allow you to achieve that. If you have to tape out production in six months, you may have to use FD-SOI.
AF: Another key point for customers deciding to work with 28FDSOI is the fact that Samsung Foundry has joined the club. A few customers really hesitated on making the move to 28nm FD-SOI ST Micro is a very really advanced company, doing its own research and development, but the fact that the production capability was very limited has people shying away. Besides the technology, the presence and the engagement of Samsung is giving another boost to the acceptance.
KL: Yes, we’re recognized as a credible, high-volume manufacturing partner. That helps a lot.
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*NRE = non-recurring engineering. In a fabless scenario, there are NRE for IP and design (engineering costs, up-front and royalty-based IP costs), NRE for masks and fabrication (mask costs, wafer prototype lots, tools costs, probe cards, loadboards and other one-time capital expenditures), and NRE for qualifications (ESD, latch-up and other industry-specific qualifications, as in automotives).
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This is the second installment in ASN’s 3-part interview with Samsung on their 28nm FD-SOI foundry offering. If you missed the other parts, you can still read part 1 about technology readiness (click here), and part 3 on the ecosystem (click here).