Tag Archive Cadence

SOI – 3D Integration – Subthreshold Microelectronics: Register now for the IEEE S3S!

(Photo credit: 2013 Hyatt Regency Monterey Hotel and Spa) Last May, we already let you know about the IEEE S3S conference, founded upon

Common Platform Technology Forum 2013: SOI Highlights

The 2013 Common Platform Technology Forum showcased “the latest technological advances being delivered to the world's leading electronics compa

Go Ahead – Take 28nm FD-SOI Out for a Test Drive

CMP is offering multi-project wafer runs of ST's 28nm FD-SOI technology on Soitec wafers with Leti models. It's the same technology that GF will

Power & Performance: GSS Sees SOI Advantages for FinFETS

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indic

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts

Bulk logic designs for mobile apps port directly to FD-SOI

Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps. Fully-depleted (FD)-SOI is a potential alternati

Program Launch: Ready for SOI Technology

The goal is to build a visible, working IP ecosystem to support SOI adoption. This spring, the SOI Industry Consortium launched its Ready for S

Jump Start SOI Training

Free webcast session now available. Click here To help IP and chip designers transition to SOI, the Ready for SOI Technology program spons

Digital implementation with SOI: go with the float

Off-the-shelf solutions eliminate SOI design-time overhead. Since the drive began to make SOI a more mainstream manufacturing process there has

What’s new

SOI: Simply Greener — The Campaign This summer, the SOI Industry Consortium launched the “SOI Simply Greener” initiative, encouraging the