CMP is offering multi-project wafer runs of ST’s 28nm FD-SOI technology on Soitec wafers with Leti models. It’s the same technology that GF will be rolling out in high-volume next year. This article details how it works, and what it includes.
What would a port to 28nm FD-SOI do for your design? A recent announcement by CMP, STMicroelectronics and Soitec invites you to find out. Specifically, ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process – which uses innovative silicon substrates from Soitec and incorporates robust, compact models from Leti – is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP (Circuits Multi Projets®). ST is releasing this process technology to third parties as it nears completion of its first commercial FD-SOI wafers. What you can get from CMP is the same process technology that will be available to all at GlobalFoundries in high-volume next year.
The CMP multi-project wafer service allows organizations to obtain small quantities of advanced ICs – typically from a few dozen (for a prototype, say) to over a hundred thousand units (for low-volume production). CMP is a non-profit, non-sponsored organization created in 1981, with a long history of offering SOI and other advanced processes. It offers industrial quality process lines – with industrial-level, stable yields. Headquartered in Grenoble, France, CMP has over 1000 clients in 70 countries.
The cost of ST’s 28nm FD-SOI CMOS process at CMP has been fixed at 18,000 €/mm2, with a minimum of 1mm2. At this point in scaling, that gets you about two million gates – about eight million transistors. So the pricing is very aggressive for an advanced technology node – and it comes down if you get more than 3mm2, and even more if you get >15mm2, Kholdoun Torki, CMP Technical Director explained to ASN.
Dr. Torki was kind enough to elaborate a bit on the particulars for us. Here’s what he says. The ST design kit contains a full-custom part, and standard-cells and I/O libraries with digital design-flows supported under Cadence Encounter and Synopsys Physical Compiler. The design-kit is from ST Front-End Manufacturing and Technology, Crolles. CMP delivers this design-kit under NDA.
Devices are supported for UTSOI (ultra-thin SOI) models, which were developed by and are the property of Leti.
The UTSOI model is available under Eldo from Mentor and Hspice from Synopsys. It is also expected to be available for Spectre (Cadence) and for Golden Gate and ADS (Agilent) within the next few months.
CMP provides the first level support (installation, and general questions on the use of the kit). Multi-Projects Wafer runs are organized at ST Crolles. For low volume production, a quote is issued on a case-by-case basis, on request.
The ST 28nm FD-SOI offering has a true 28nm BEOL metallization with .1µ metal pitch, says Dr. Torki.
CMP also has offered the Leti 20nm FD-SOI R&D process since 2010. (In fact for those looking even further ahead, Leti has predictive model cards down to 11nm.) It is expected the 20nm FD-SOI process from ST, incorporating strategic technology from Leti, will be available from CMP towards the end of next year, although the exact date has not yet been fixed.
In Multi-Project Wafer runs, costs are shared (and reduced) because the reticle area is shared across customers. CMP offers one-stop shopping, including:
Last year (2011), CMP handled 273 circuits, including prototypes, low-volume production runs and industrial applications.
For organizations like the 77 customers in 23 countries using 28nm bulk CMOS through CMP’s program, migrating from 28nm CMOS bulk to 28nm FD-SOI will be seamless, says Dr. Torki. There are no disruptions in process or design. There are the same layer numbers and names, so they can load a bulk design directly into an FD-SOI design environment. They use the common design-rules platform (ISDA alliance design-rules), and bulk devices can be co-integrated with FD-SOI devices as needed.
These are real, leading edge chips and circuits we’re talking about. Here’s what you get:
The 28nm FD-SOI standard-cells, IO cells and related IP are all from ST. The CORE cells Libraries include:
The IO cells Libraries include:
You can find more details at the CMP website, or from the paper Dr. Torki presented at the 2012 SOI Conference.
So this represents a real opportunity. Universities, often doing important research for industrial partners, have long known the value of using services like CMP’s. But with this latest ST-CMP-Soitec announcement, the fabless world can do more than kick the tires – they can take 28nm FD-SOI for a real test drive.
FD-SOI promises an extremely cost-effective, performance-enhanced, power-miser of a chip. Wouldn’t you like to give it a try?
Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere. But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.
GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks. The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones. Then they also need to provide reliable models to designers who will use them before committing chips to silicon. One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs. This covered “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”. Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project. It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
A few months later, when Chipworks published pictures of the (bulk silicon) Intel 22nm FinFETs, the folks at GSS started a series of blogs that caught the attention of major tech pubs such as EE Times, Electronics Weekly and EDN. For reference, here are the blogs and basically what they concluded:
Specifically, the July 27th blog indicated that if FinFETs are rectangular in shape, drive current would be 12-15% better. Would that be easier to do on an SOI wafer? Soitec has argued that their “fin-first” SOI-based approach to FinFET manufacturing will save both time & money while getting better results (see Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET in Semiconductor Manufacturing & Design).
The GSS blog also reminded readers that the company’s CEO and founder, Asen Asenov (an extremely heavy hitter who’s published over 550 papers), has hinted that “…SOI FinFETs with an almost ideal rectangular shape may be a better solution for future FinFET scaling”. GSS has noted previously that “FinFETs built on an SOI substrate could have significant advantages terms of simpler processing, better process control and reduced statistical variability”.
Fin shape aside, GSS said that by virtue of the layer of insulation, SOI would give another 5% boost to FinFET drive current. But perhaps more importantly, that layer of insulation in SOI-based FinFETs would deliver on average 2.5 times less leakage – which would translate into a doubling of battery-life for your cell phone.
IBM has now entered into an agreement with GSS et al on a project called StatDES, for Statistical Design and Verification of Analogue Systems – see last month’s IBM blog by IBM Research Scientist Dr. Sani Nassif, entitled “Fins on transistors change processor power and performance”.
Dr. Nassif writes, “IBM, University of Glasgow and the Scottish Funding Council are collaborating on a project to simulate 3D microprocessor transistors at a mere 14 nanometer scale (the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator (SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES, promises to keep improving microprocessor performance and energy conservation.”
The steering group also includes folks from ST, Freescale, Wolfson and Cadence, so one would guess we’ll be hearing more from this project – and others like it, to be sure – in the future, wouldn’t you think?
The goal is to build a visible, working IP ecosystem to support SOI adoption.
This spring, the SOI Industry Consortium launched its Ready for SOI Technology program, a global initiative to broaden access to energy efficient SOI technology for the electronics industry. This is an important step towards the formation of a complete ecosystem enabling designers to take full advantage of SOI.
A core project team from ARM, Cadence and IBM collaborated within the consortium to lay the foundation for an IP portal on the ChipEstimate.com website. Synopsys and Boeing also contributed key IP to the launch, with an invitation extended to other developers to add to the growing SOI IP ecosystem. Others have quickly followed suite. Read More
Free webcast session now available.
To help IP and chip designers transition to SOI, the Ready for SOI Technology program sponsored an SOI Jump Start Training event. Held in April at the Cadence auditorium, the event is now available as a recorded webcast through the SOI Consortium website.
An international audience representing 75 separate companies, research institutes and universities attended the event to learn how to leverage the benefits of SOI from ARM, Cadence, IBM and SOI Industry Consortium speakers.
Off-the-shelf solutions eliminate SOI design-time overhead.
Since the drive began to make SOI a more mainstream manufacturing process there has been concern over the cost. These considerations have overshadowed the benefits that the floating body of the SOI process brings, which includes better chip performance per watt, smaller die size, and better scalability at smaller geometries.
The concerns raised were not only regarding the cost of the manufacturing process itself — because any advance comes at a price — but also with the cost of actually implementing cell-based digital designs. The biggest concern: it would take many more man-hours of engineering time to make it through the digital design process as compared to bulk CMOS. Read More
This summer, the SOI Industry Consortium launched the “SOI Simply Greener” initiative, encouraging the electronics industry to adopt a broader application of SOI’s energy saving benefits.
Results from two studies offered by consortium members demonstrate both increased performance and reduced power consumption – the magnitude of the benefit applied to each is the designer’s choice.
Whether designers put the emphasis on increasing or maintaining performance, significant power savings (as well as area savings) were realized with a move to SOI.
The Consortium’s SOI: Simply Greener logo is freely available on the website. Members and supporters are encouraged to download it for use in their own presentations.
In support of the press announcement launching the initiative, the Consortium offered citations from industry leaders. A few follow here – you can read all of them on the SOI Consortium website.
“As we detailed in our recent report Semiconductor Technologies: The Potential to Revolutionize U.S. Energy Productivity, semiconductors already are the leading factor behind energy efficiency gains. SOI offers a major advance in the power efficiency of electronics, and with appropriate public policy, investment and usage these semiconductor technology gains can contribute to cumulative net electricity bill savings of $800 billion through 2030 for consumers and businesses in the United States alone, as well as creating an average of 500,000 new jobs per year and reducing energy-related CO2 emissions by more than 400 million metric tons annually over the period 2010 through 2030.”
John A. “Skip” Laitner, lead report author and Director, Economic and Social Analysis, American Council for an Energy-Efficient Economy (ACEEE)
“UMC has been incorporating the benefits of SOI technology across multiple semiconductor applications such as MEMS, photonics, and our 65nm high-speed process portfolio. The energy efficiency of SOI adds to the attractiveness of the technology and conforms with UMC’s green initiative to provide environmentally friendly processes for our customers. We look forward to further developing SOI to provide customers with solutions that enable more innovative applications for a better and greener planet.”
W.Y. Chen, Senior Vice President, UMC
“The ‘SOI: Simply Greener’ initiative expresses the motivation and values that connect members of the SOI Consortium and foster collaboration around this energy-efficient technology. We welcome like-minded companies to join us in this meaningful work, to bring needed improvements to our industry and quality of life. The ecosystem is ready and accessible, and there is a broad space of opportunities for innovation in all areas: process; planar and 3D device architecture and optimization; digital, analog, RF, and MEMS design; EDA; IP development and optimization; heterogeneous planar and 3D integration; and services.”
Horacio Mendez, Executive Director, SOI Consortium.
“As a leader in low power design, Cadence continues to invest heavily in new technologies and methodologies to provide maximum power efficiency, now a key consideration for all designs. We are pleased to announce our end-to-end support for the SOI process within the Cadence Low Power Design Solution, thereby offering customers an integrated and low-risk path to maximizing the potential SOI benefits on their green designs.”
Dr. Chi-Ping Hsu, Senior Vice President, R&D Implementation Group, Cadence
Honeywell has worked with the top EDA tool vendors to develop the SOI process design kits (PDKs) needed by both in-house designers and foundry customers. Rick Veres, Honeywell EDA Manager, explains.
For digital rad-hard ASIC design, we worked with Synopsys to adapt the Pilot Design Environment to our process. The environment supports their entire RTL to GDSII flow, including all their synthesis tools, place and route, insertion and so forth—the standard industry flow. Our SOI cell libraries are all radhard optimized for commercial, military or satellite applications.
Honeywell provides mixed signal/analog SOI devices and cells to support a broad range of customer’s mixed mode ASICs. The design environment maintains all the digital capabilities while supplying analog cells and SRAM for true mixed signal ASICs. The design flow and associated Design Kits are supported for Cadence mixed signal tools.
For RFIC design and simulation, Honeywell’s SOI fab processes are supported by Cadence (Tality) PDKs, including RF Spectre.
For high temperature SOI CMOS, the Cadence PDK full-custom development library supports Cadence schematic capture, simulation, layout and verification tools.
Mentor Graphics has been very instrumental in helping us develop our SOI capability in their Calibre tool. We use Calibre to verify designs before we run them in the fab. There are some nuances that a user doesn’t see, that as a developer we do. For example, we have twice as many rules we have to implement and check in SOI versus standard bulk. But the complexity is all on the developer side. The user just runs it—it’s transparent to them. Mentor Graphics has done some significant and impressive work for us.
The widening availability of tools and services is good news for designers in the fabless/foundry arena considering the move to SOI.
Leading foundries have made the investments in manufacturing on SOI. Those that have taken the final steps – finalizing electrical characterization, constructing SPICE models, integrating design tools and building libraries – are winning business.
Chartered, for example, is producing SOI-based chips for AMD, the Microsoft Xbox®360, Via, and others in partnership with IBM. TSMC, meanwhile has announced an SOI version of its Nexsys 65nm process technology for next year.
For the high-performance fabless community, IBM itself was the first to open SOI doors to its foundry customers. Ghavam Shahidi, Director of Silicon Technology, IBM Research Division, says they see the full range – from customers that do the whole thing themselves, just getting the IBM-specific SOI IP, to those who essentially hand off the whole project to the IBM services group. Asked how big a challenge the move to SOI is, he says, “It’s not a big deal – it seems scarier than it is.”
As far as those low-power customers worried about the added cost of SOI wafers, he suggests that if they were to consider the broader picture and include things like cooling, they might find it a more cost-effective solution.
Design flow involves a series of iterative steps subject to rules and constraints – many of which are different when devices are built in SOI. SOI-specific IP is needed at each step, especially:
• In support of the logic synthesis tools used to transform the high-level RTL design into a gate-level netlist (which is the collection of “standard cells” and their electrical interconnections specific to the foundry that will do the manufacturing).
• And in the placement and routing tools to layout the chip. Either the design team has to develop SOIspecific expertise (a substantial investment), or license intellectual property (IP) from a third party (the foundry or an IP vendor).
By licensing the requisite IP, designing-in SOI becomes a transparent process. As the designer generates netlists and optimizes placement and routing, the SOI IP is applied via standard EDA tools from companies like Cadence, Synopsys and Magna.
TCAD from Synopsys, for example, can model the SOI technology from the process and device simulation standpoint, so performance of SOI and bulk silicon can be compared before choosing the right technology for the design, says a company representative. Also, engineers can optimize the SOI technology by using TCAD simulation before running costly experimental wafers.
Says Francois Thomas, Europe ICD & DFM Field Marketing Director for Cadence Design Systems, “SOI uses nearly standard processes and design but with better performance. The real difference appears for cell creation, analog simulation and DRC and parasitic extraction.”
Recently three new SOI IP and design services suppliers have helped bring SOI design to a wider community.
Soisic. Working with companies that pioneered SOI, Soisic developed extensive design expertise and intellectual property (IP), which is now available to any ASIC designer. For a simple licensing fee, a design team can transparently integrate the SOI-specific design considerations into the design flow – without a special understanding of SOI (things like the history effect, for example) and the differences with bulk. No additional investment in time, training or libraries is needed
Innovative Silicon (ISi). ISi has harnessed the SOI “floating body effect” for memory cells that are twice as dense as existing DRAM and five times as dense as existing SRAM. This proprietary “Z-RAM™” (for Zero capacitor DRAM) technology uses standard SOI logic processes without new materials or extra process or masking steps. For most SoC and microprocessor ICs, this results in SOI being a lower-cost solution than bulk silicon. AMD is the first licensee.
CISSOID. As a fabless player, CISSOID designs custom analog, mixed and digital ASICs, with a specialty in SOI-based high temperature components for oil & gas, aeronautics, space and automotive applications. For low-power and RF applications, CISSOID offers design services, IP development and consulting for optimization of SOI analog and RF circuits.
For designers of mixed-signal, analog and RF devices, a growing number of major foundries have been actively promoting their SOI services.
For example, Honeywell offers RF SOI foundry services, supported by a comprehensive tool set and optional design services. The company points out that the SOI-enabled integration of mixed signal and high-voltage applications with complex control functions performed at low power on a single chip ultimately reduces cost.
Others like Atmel promote their SOIbased smart power foundry services for automotive, telecommunications and consumer electronics, noting that using SOI cuts the die-area in half compared to standard bulk technology. The X-Fab foundry service offers SOI-based analog/mixed-signal and MEMS.
All things considered, SOI is now well within the grasp of the greater chip design community.