ST Fellow Dr. Andreia Cathelin gave a terrific presentation at the recent CMP Annual Meeting. Now posted and freely available, Performance of Recent Outstanding 28nm FD-SOI Circuits Taped Out Through CMP highlighted eight examples – though she told ASN that she had easily over 50 from which to choose.
CMP is a Multi-Project Wafer (MPW) service organization in ICs, Photonic ICs and MEMS. They’ve been organizing prototyping and low volume production in cooperation with foundries for over 37 years. In partnership with ST since 1994, in the fall of 2012 they opened access to MPW runs in the 28nm FD-SOI process. More than 180 tape-outs have been fabricated since then using the process.
As Dr. Cathelin said, this lets ST show their industrial clients just how good the technology is. The chips she chose to cover in her presentation get “spectacular performance”, she said, especially for low-power or power-sensitive SoCs.
Here’s a quick recap of what she presented (some of which she co-authored), followed by some other SOI-related updates from the CMP meeting.
FD-SOI, said Dr. Cathelin, “…is unmatched for cost-sensitive markets requiring digital and Mixed Signal SoC integration and performance.” In the first dozen slides of her presentation, she gave the technical details on the advantages of FD-SOI in analog, RF/millimeter wave, Analog/Mixed-Signal and digital design. If you’re a designer, you’ll want to check those out.
Then she ran through eight great chips – all manufactured by ST on 28nm FD-SOI through CMP’s MPW services. Here they are. (You can click on the illustrations to see them in full screen.)
This chip was presented at ESSCIRC ’16 by a team from ISEN Lille, Professors Andreas Kaiser and Antoine Frappé (you can get the complete paper by I.Sourikopoulos et al on IEEE Xplore – click here.) As noted in the abstract, “Delay controllability has always been the major concern for the reliable implementation of circuits whose purpose is timing.” By leveraging body biasing in FD-SOI, this novel low-power design architecture for 60GHz receivers enables very high bandwidth together with fine-grain wide range delay flexibility, for implementing Delay Feedback Equalizer techniques in the Intermediate Frequency (IF) reception path. The results are state-of-the-art: ultra wide range, linear control, fs/mV sensitivity and energy efficient controllable delay cells.
Presented at RFIC ’17 by a team from the IMS Bordeaux lab, Professor Yann Deval and STMicroelectronics, this chip demonstrates the highest oscillation frequency attainable so far at the 28nm node, be it planar bulk or FD-SOI. (Click here to get the full paper by R. Guillaume et al from IEEE Xplore.) As noted in the abstract, solutions on silicon for mmW and sub-mmW applications have been demonstrated for high-speed wireless communications, compact medical and security imaging. The main challenges are for the signal generation at high frequencies, and this implementation demonstrates spectacular oscillation frequencies close to the transistor’s transition frequency (fT). In this chip, they used body bias tuning to optimize the phase noise, demonstrated very low on-wafer variability, and simulation methods that permit measurement prediction precision within 0.1%.
Extremely energy efficient SoCs are key for the IoT era – but SRAM gets very tricky at ultra-low voltages (ULV). Presented at ESSCIRC ’16 by B. Mohammadi et al (on IEEE Xplore here) from Professor Joachim Rodrigues’ team at the Lund University, this is a 128 kb ULV SRAM, based on a 7T bitcell. The minimum operating voltage VMIN is measured as just 240mV and the retention voltage is as low as 200mV. FD-SOI enabled them to overcome ULV performance and reliability challenges by letting the Lund U.-lead team selectively overdrive the bitline and wordline with a new single-cycle charge-pump. Plus they came up with a new scheme so it doesn’t need a sense amplifier, yet delivered 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access.
4. Matched Ultrasound Receiver in 28FDSOI
Presented at ISSCC ’17 (with an extended relative paper at JSSC ’17) by M-C Chen et al with Professor Boris Murmann’s team at Stanford, the full title of the paper about this chip is A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI. (Click here to get it on IEEE Xplore.) It’s a a proof-of-concept for a big ultrasound receiver: a “pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging.” PA is “…an emerging medical imaging modality based on optical excitation and acoustic detection.” It’s used in studying cancer progression in clinical research, for example. As noted in the paper abstract, “The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation.” One of the (many) advantages of FD-SOI in this context is for front-end signal conditioning in each pixel. This unique type of pixel pitch-matched architecture implementation is possible only in a 28nm (or less) node of an FD-SOI technology, as it is matched with the pitch sizing needed for the ultrasound transducers in order to generate signals for a 3-D reading.
5. SleepTalker – 28nm FDSOI ULV WSN Transmitter: RF-mixed signal-digital SoC
Presented at VLSI ’16 and JSSC ’17 by G. de Streel et al from Professor David Bol’s team at Université Catholique de Louvain la Neuve, the full title of the paper about this chip is SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping (get it on IEEE Xplore here). This chip tackles the IoT requirement for sensing functions that can operate in the ULV context. That means creating wireless sensor nodes (WSN) that can be powered on an energy harvesting power budget – and that’s a real challenge if you want to incorporate an RF component that can handle medium data rates (5-30 Mb/s) for vision or large distributed WSN networks. The energy efficiency has to be better than 100 pJ/b. To get there, the UCL-lead team used wide-range on-chip adaptive forward back biasing for “…threshold voltage reduction, PVT compensation, and tuning of both the carrier frequency and the output power. […] Operated at 0.55 V, it achieves a record energy efficiency of 14 pJ/b for the transmitter (TX) alone and 24 pJ/b for the complete SoC with embedded power management. The TX SoC occupies a core area of 0.93 mm2.”
This massive MIMO chip was presented at ISSCC ’17 by a team from Professors Liang Liu and Ove Edforss at the Lund University in a paper entitled 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI (H. Prabhu, et al; get it from IEEEE Xplore here). While Massive MIMO (MaMi) will be needed for next-gen communications, it can’t be achieved by just scaling MIMO – that would be too costly in terms of flexibility, area and power. As noted in the Lund U. team’s intro, “Algorithm optimizations and a highly flexible framework were evaluated on real measured channels. Extensive hardware time multiplexing lowered area cost, and leveraging on flexible FD-SOI body bias and clock gating resulted in an energy efficiency of 6.56nJ/QRD and 60pJ/b at 300Mb/s detection rate.”
7. ENVISION: A 0.26-to-10TOPS/W Subword-Parallel Dynamic-Voltage-Accuracy-Frequency-Scalable Convolutional Neural Network Processor in 28nm FDSOI
Today’s solutions for always-on visual recognition apps are an order of magnitude too power hungry for wearables. Running at 10’s to several 1OO’s of GOPS/W, they use classification algorithms called ConvNets, or Convolutional Neural Networks (CNN). The paper about this chip was presented at ISSCC ’17 by a team from professor Marian Verhelst at Katoliek Universiteit Leuven (B. Moons, et al, get it from IEEE Xplore here), and it changes everything. Leveraging FD-SOI and body-biasing, the KU Leuven team solved the power challenge with, “…the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices.”
As we learned at SOI Consortium FD-SOI Tutorial Day in SiValley last year, Professor Borivoje “Bora” Nikolic of UC Berkeley is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI!) They presented the RISC-V chip here at ESSCIRC ’16 and JSSC ’17, in a paper entitled Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC (B.Keller, et al, on IEEE Xplore here). As they noted in the intro, a major challenge for mobile and IoT devices is that their workloads are highly variable, but they operate under very tight power budgets. If you apply adaptive voltage scaling (AVS), you can improve energy efficiency by scaling the voltage to match the workload. But in the current gen of SoCs, the AVS timescales of hundreds of microseconds is too slow. The chip the Berkeley team presented brought that down to sub-microseconds by aggressively applying body-biasing throughout the chip, including to workload measurement circuits and integrated power management units. The result is “… extremely fine-grained (<1μs) adaptive voltage scaling for mobile devices.” (BTW, they expand on some of the details in another paper published in 2017.) These design techniques are now taught at UC Berkeley, as this kind of implementation is the subject of a course in SoC design (including the RF part of transceivers); a first educational chip has already been taped-out and successfully measured. (BTW, Professor Nikolic will once again join Dr. Cathelin and other luminaries in teaching at the SOI Consortium’s FD-SOI Training Day in Silicon Valley, 27 April 2018 – click here for sign-up information.)
At the meeting, CMP also made a presentation on all their MPW offerings – you can get it here. On ST’s SOI (in addition to 28nm FD-SOI, of course), that includes the new 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power (for automotive sensor interface ICs, 3D ultrasound, MEMS & micro-mirror drivers); and 130nm H9-SOI-FEM: Front-End Module (for radio receiver/transceiver, cellular, WiFi, and automotive keyless systems).
CMP also provides tutorials that are used by institutions across the globe. A new update to the tutorial, RTL to GDS Digital Design Flow in 28nm FD-SOI Process is now available – you can see the presentation they did about that here. (It now includes LVS and DRC steps with Mentor/Calibre or Cadence/PVS.) Other services, like the 2-day, hands-on THINGS2DO FD-SOI training days at the end of March are always fully booked almost immediately, but don’t hesitate to inquire, as they’ll be adding more.
For some more examples of 28nm FD-SOI chips run through CMP over the years, see their website pages on Examples of Manufactured ICs. There are also some nice examples on pages 21 and 23 of their most recent annual report.
For those in the photonics world, CMP has teamed up with Leti to offer Si-310 PHMP2M, a 200mm CMOS SOI platform. CMP is cooperating with Tyndall for the photonics packaging – see that presentation here. Training kits and tutorials will be available in Q3 of this year.
And in partnership with MEMSCAP, CMP offers Multi-User MEMS Processes (aka MUMPs) for SOI-MEMS.
So lots of terrific SOI resources for CMP – check it out!
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Note: special thanks to Andreia Cathelin of ST and Kholdoun Torki of CMP for their help on this piece.
Would you like to better understand FDSOI-based chip design? If you’re in Silicon Valley, you’re in luck. On April 14th, the SOI Consortium is organizing a full day of FDSOI tutorials for chip designers. This is not a sales day. This is a learning day.
On the agenda are FD-SOI specific design techniques for: analog and RF integration (millimeter wave to high-speed wireline), ultra-low-power memories and microprocessor architecture, and finally energy-efficient digital and analog-mixed signal processing designs.
The courses will be given by top professors at top universities (including UC Berkeley, Stanford, U. Toronto and Lund). These folks not only know FDSOI inside and out, they’ve all spent many years working closely with industry, so they truly understand the challenges designers face. They’ve helped design real (and impressive) chips, and have stories to tell. (In fact, all of the chips they’ll be presenting were included in CMP’s multiproject wafer runs – click here if you want to see and read about some of them on CMP website.)
The FD-SOI Tutorial Day, which will be held in San Jose, will begin at 8am and run until 3pm. Each professor’s course will last one hour. Click here for registration information.
(The Tutorial Day follows the day after the annual SOI Silicon Valley Symposium in Santa Clara, which will be held on April 13th.)
Here’s a sneak peak at what the professors will be addressing during the FDSOI Tutorial Day.
If you know anything about FDSOI, you know ST’s been doing it longer than pretty much than anyone. Professor Cathelin will share her deep experience in designing ground-breaking chips.
She’ll start with a short overview of basic FDSOI design techniques and models, as well as the major analog and RF technology features of 28nm FDSOI technology. Then the focus shifts to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits, considering the full advantages of wide-voltage range tuning through body biasing. For each category of circuits (analog/RF and mmW), she’ll show concrete design examples such as an analog low-pass filter and a 60GHz Power Amplifier (an FDSOI-aware evolution of the one featured on the cover of Sedra/Smith’s Microelectronics Circuits 7th edition, which is probably on your bookshelf.) These will highlight the main design features specific to FD-SOI and offer silicon-proof of the resulting performance.
Particularly well-known for his work in millimeter wave and high-speed wireline design and modeling (which are central to IoT and 5G), Professor Voinigescu has worked with SOI-based technologies for over a decade. His course will cover how to efficiently use key features of FD-SOI CMOS technology in RF, mmW and broadband fiber-optic SoCs. He’ll first give an overview at the transistor level, presenting the impact of the back-gate bias on the measured I-V, transconductance, fT and fMAX characteristics. The maximum available power gain (MAG) of FDSOI MOSFETs will be compared with planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz.
Next, he’ll provide design examples including LNA, mixer, switches, CML logic and PA circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of sub-28nm CMOS technologies. Finally, he’ll look at a 60Gb/s large swing driver in 28nm FDSOI CMOS for a large extinction-ratio 44Gb/s SiPh MZM 3D-integrated module, as a practical demonstration of the unique capabilities of FDSOI technologies that cannot be realized in FinFET or planar bulk CMOS.
Having started his career as a digital ASIC process lead in the mobile group at Ericsson, Professor Rodrigues has a deep understanding of ultra-low power requirements. His tutorial will examine two different design strategies for ultra-low voltage (ULV) memories in 28nm FD-SOI.
For small storage capacities (below 4kb), he’ll cover the design of standard-cell based memories (SCM), which is based on a custom latch. Trade-offs for area cost, leakage power, access time, and access energy will be examined using different read logic styles. He’ll show how the full custom latch is seamlessly integrated in an RTL-GDSII design flow.
Next, he’ll cover the characteristics of a 28nm FD-SOI 128 kb ULV SRAM, based on a 7T bitcell with a single bitline. He’ll explain how the overall energy efficiency is enhanced by optimizations on all abstraction levels, from bitcell to macro integration. Degraded performance and reliability due to ULV operation is recovered by selectively overdriving the bitline and wordline with a new single-cycle charge-pump. A dedicated sense-amplifierless read architecture with a new address-decoding scheme delivers 90MHz read speed at 300mV, dissipating 8.4 fJ/bit-access. All performance data is silicon-proven.
Considered by his students at Berkeley as an “awesome” teacher, Professor Nikolic’s research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. An expert in body-biasing, he’s now working on his 8th generation of energy-efficient SOCs. During the FDSOI tutorial, he’ll cover techniques specific to FDSOI design in detail, and present the design of a series of energy-efficient microprocessors. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling with high energy efficiency, the designs feature an integrated switched-capacitor DC-DC converter. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.
If you’ve ever attended a talk by Professor Murmann, you know that he’s a really compelling speaker. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces. In this course, he’ll look at how FD-SOI technology blends high integration density with outstanding analog device performance. In same-generation comparisons with bulk, he’ll review the specific advantages that FD-SOI brings to the design of mixed-signal blocks such as data converters and switched-capacitor blocks. Following the review of such general benchmarking data, he’ll show concrete design examples including an ultrasound interface circuit, a mixed-signal compute block, and a mixer-first RF front-end.
If you’re headed to DAC (June 5-9 in Austin,TX) and are interested in learning more about FD-SOI, there will be lots of opportunities. Here’s a quick rundown.
Synopsys (stands 149 & 361) and GlobalFoundries are hosting a dinner on Tuesday evening (7 June) at the Austin Hilton around the theme, What’s Important for IoT—Power, Performance or Integration… or All of the Above? They’ll be talking about how FD-SOI addresses these challenges. Panel members will discuss design techniques to push the envelope on low power, low leakage, burst performance and optimal cost to enable the design of innovative IoT-based products. Attendance is free, but registration is required and seating is limited. Click here to go to the registration site.
Samsung Foundry (stands 607 and 706) and partners will be doing a number of presentations on Samsung’s 28nm FD-SOI offering, 28FDS. They’ll be showcasing 28FDS wafers, offering multiple presentations by Samsung Foundry’s experts, and sharing solutions built on the 28FDS technology by their Foundry Ecosystem partners. As noted in ASN coverage of the recent SOI Consortium event in San Jose (read it here), Samsung is now in commercial production of 28FDS. They have a strong 28nm FD-SOI tape-out pipeline for 2016, and interest is rising fast.
IP Track: Minimizing SOC Power Consumption: A Top Down Design Methodology or Bottoms Up Starting With the Process Selection Problem? Panelists include Carlos Mazure (of the SOI Industry Consortium & Soitec) and Ron Martino (of NXP) Monday, June 6th from 4:00pm – 5:00pm in Ballroom G.
Variation-Aware Design at Advanced and Low-Power Processes. Panelists include Azeez Bhavnagarwala (ARM), Glen Wiedemeier (IBM), John Barth (Invecas) and Jeff Dyck (Solido). Monday, June 6th from 10:30am – 11:30am, Room: 9BC.
Presentation 9.1 Impact of Leakage & biasing on Power in 22FDX Process. By Krishnan Subramanian et al (Invecas) and Sankar Ramachandran – (Apache Design). Monday, June 6th, 3:30pm – 4:00pm, Ballroom G.
Presentation 50.4 Leveraging FDSOI through Body Bias Domain Partitioning and Bias Search. By Johannes M. Kuehn et al (Eberhard Karls Univ. Tubingen & Keio Univ.) Wednesday, June 8th, 1:30pm – 3:00pm, Room: 17AB. This presentation will be given at 2:15. (You can also get the paper from the ACM site here.)
101.12 Parametric Exploration for Energy Management Strategy Choice in 28nm UTBB FDSOI Technology. By Jorge Rodas et al (CEA-Leti Minatec & Univ. Grenoble Alpes) Work-in-Progress (WIP) poster session, Wednesday, June 8th, 6:00pm – 7:00pm, Room: Trinity St. Foyer
Stands & More
Cadence Theater (stand 43 – full schedule here)
Tuesday, June 7th
Wednesday, June 8th
Leti (stand 1818) – a driving force behind all things SOI, stop by to learn more about Silicon Impulse®, their FD-SOI platform for IoT & ultra-low-power (ULP) apps that helps start-ups, SMEs and large companies evaluate, design, prototype & move to volume (more here).
And finally, the opening keynote on Monday morning (at 9:15 in Ballroom A) will be given by NXP’s Lars Reger, CTO of their Automotive Business Unit. The topic is Revolution Ahead – What It Takes to Enable Securely Connected, Self-Driving Cars. When it comes to automotive, NXP is the original SOI pioneer, dating to back to 1999. NXP’s sold billions of SOI-based chips for high-voltage automotive applications – they’re used by virtually every carmaker on the planet (read about the early history here and here).
And now with the Freescale acquisition, NXP is full speed ahead with FD-SOI applications processors. If you missed it, you’ve got to read the recent ASN series by Ron Martino (NXP’s VP for i.MX Applications Processor and Advanced Technology Adoption). He explains why they chose 28nm FD-SOI, and exactly what it does for the i.MX 7 series (32-bit ARM v7-A core, targeting the general embedded, e-reader, medical, wearable and IoT markets) and i.MX 8 series (64-bit ARM v8-A series, targeting automotive applications, especially driver information systems, as well as high-performance general embedded and advanced graphics applications) Click here to read it now. NXP gave a demo of the I.MX 8 at FTF 2016 a few weeks ago – check out the video they posted on Twitter here.
If you go to DAC and you have a Twitter account, be sure to tweet #FDSOI and #53rdDAC – @followASN will be happy to pass it along!
From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
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ASN: In which areas do you see SOI giving designers an edge?
MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.
ASN: What is Leti doing moving forward?
MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….
The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.
ASN: What role does Leti play in the SOI roadmap?
MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.
Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.
ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?
MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.
ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?
MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..
In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.
We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.
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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)
From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.
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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?
Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.
Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.
ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?
MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.
ASN: How do you decide what you’re going to work on? Is it your customers?
MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.
On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.
ASN: How much Leti activity is based on SOI?
MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.
All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.
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Here’s a quick “official” summary of Leti:
As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.
Click here to read part 2 of this exclusive interview.
A video made during ST’s FD-SOI presentation at IP-SoC 2014 has now been posted by designreuse on YouTube (you can see it here). Over 40 minutes long, it details the European THINGS2DO project, which includes almost 50 partners working on the FD-SOI ecosystem. (This follows onto the PLACES2BE project, which is finishing up this year.) It underscores the point that the markets for this ecosystem are very fragmented, so it’s critical that such an undertaking be as broad as possible.
Over the summer, there have been a number of excellent posts on various sites related to FD-SOI, showing that interest is running ever higher.
But, if you’ve been fortunate enough to have had some vacation time, you might have missed some of them, so here’s a brief listing to help you catch up.
In mid-June, Samsung posted a video of their DAC presentation, Samsung 28nm technology for the next big thing on YouTube. Presented by JW Hwang, Principal Engineer for Samsung Electronics, it runs almost 14 minutes long, with the entire second half devoted to 28nm FD-SOI. Here are some key points made therein:
Samsung DAC ’14 video – process complexity vs. performance/power.
Samsung DAC ’14 video – 28nm FD-SOI is product-proven
Here at ASN, of course, there was the terrific piece by industry expert Handel Jones (IBS) entitled FD-SOI: The Best Enabler for Mobile Growth and Innovation. IBS concludes the benefits of FD-SOI are overwhelming for mobile through Q4/2017. Jones also looks for it to have a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs.
Also in ASN, we covered the SOI Papers at the 2014 VLSI Symposia. Three top SOI-based papers included one that indicates 14nm FD-SOI should match the performance of 14nm bulk FinFETs, and the two on 10nm SOI FinFETS. (In Part 2, we covered the rest of the SOI papers.)
Elsewhere, we saw high-profile, open debate, which is excellent and necessary. Semiwiki has been a great platform for discussion, with a steady flow of FD-SOI articles – many of which generate ferociously active discussions in the comments section. Here’s a round-up of what went on this summer:
Next, check out this interesting post in SemiconductorEngineering by Mary Ann White, director of product marketing for the Galaxy Design Platform at Synopsys. She gives a very informative perspective on “Power Reduction Techniques” (7 Aug. ’14) in bulk planar, FD-SOI and FinFETs. She talks about how biasing in FD-SOI is highly effective, then goes on to summarize various power-reduction techniques by process node. There’s an excellent summary in her graphic (her Figure 2):
There’s also a terrific chart in the same article based on the annual Synopsys’ Global User Survey (GUS), indicating which power techniques are used most in which applications (mobile, automotive, networking, etc.).
If talk on LinkedIn is any indication, the design community in India is very interested in FD-SOI. EE Herald published a much-shared interview with ST’s CAD/design solutions director in India (18 July ’14), entitled FDSOI; The only semiconductor tech to continue Moore’s Law down to 10nm. It gives an excellent overview of the technology, answering some of the basic questions designers are asking.
CMP recently delivered the first 28nm FD-SOI/10LM multi-project wafer run, Kholdoun Torki, Technical Director at CMP has indicated. “We received positive feedback on the test results with quite impressive device performance,” he said. The PDK is from ST, making this a success for both STMicroelectronics and CMP. In 2013, they had 32 prototypes from 15 customers over three runs. The latest run embedded 25 different projects. Delivery of that run to users will be in Q2 2014.
“We have a total of 140 institutions/companies already using the PDK. Four MPW runs are scheduled in 2014, one for each quarter,” said Dr. Torki. MPW price is 15000 Euro/mm2.
“At CMP we fully support UTSOI model cards available in the process design-kit (PDK) for the 28nm FDSOI process,” explains Dr. Torki. The simulation model itself is available for Eldo, Spectre and Hspice. Cadence, Mentor and Synopsys make this model available as a standard feature thanks to a Leti-ST licensing agreement.
Look for news about availability of Leti’s new UTSOI2 model (click here for more information on the model) for 14nm FD-SOI in Q2.
FD-SOI with back-biasing* (BB – also referred to as body-biasing) is an immensely powerful tool, especially for getting great performance at very low voltages with extremely low leakage.
Implemented on a smartphone processor, it’s what would give you that extra day of battery life or get you to 3GHz. But what does it mean for the SOC designer?
Back-biasing has been the subject of a lively discussion on the new LinkedIn FDSOI Design Community group. There are some very heavy hitters here from a wide range of companies – if you’re looking for expert advice, it’s an excellent place to go. Of course, people there are speaking for themselves, not necessarily for their companies. Here are brief summaries and excerpts of some of the comments.
Back biasing, they agree, can be fairly basic (e.g., with a common bias for the whole chip) or more sophisticated (with, for example, a separate bias for each block). Its implementation requires efforts comparable to other design techniques commonly used in modern low-power chips; however, with FD-SOI, its efficiency is really impressive – perhaps giving you as much as the equivalent of about a process node’s worth of improvement. At the system level, (dynamic) back-biasing is very similar to what designers have been doing for years in planar bulk low-power designs with “dynamic voltage and frequency scaling” (aka DVFS), so using back-bias as a power management technique is not overly complex if you’ve already implemented DVFS – which, by the way, is suffering from diminishing returns in bulk at the latest nodes.
One of the group’s experts notes that, “…adaptive back-biasing and Vdd control (per-chip based on speed, but not time-varying) is not significantly more complex than just per-chip Vdd control—actually, could be easier if it reduces Vdd range—but is more effective at reducing power, especially at high temperature and with process variation taken into account.”
Incidentally, you get can ST’s 28nm FD-SOI PDK from CMP (click here for details—CMP’s already had over 110 requests for it). With this platform, designers benefit from the fact that back-bias support is “built-in” – but how they exploit it in their design is still their choice, of course.
Whether you use ST’s PDK or go it alone, as one participant notes, “…using back biasing to reduce the effect of process and temperature variation can make the designers life much easier by greatly reducing the spread of performance that they have to close timing over. It also reduces power consumption by allowing operation at consistently lower (and more constant) supply voltages, which in turn eases the electromigration and power density problems which are becoming increasingly severe in each new node and are taking more and more time and effort to fix.”
So in the end, these folks agree, back-biasing in FD-SOI applies to all applications and makes design easier, not harder.
*What is back-biasing (BB)?
As explained last year in a white paper by ST & Soitec, in FD-SOI:
Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage (Vt), to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.
The prototyping services organization CMP has already received over 110 requests for the 28nm FD-SOI PDK from ST. The requests are coming from major companies as well as R&D organizations and universities. The CMP offering was detailed in ASN last year – click here for details. Designers are now asking CMP for ST’s 14nm FD-SOI PDK, which is expected to be available shortly.