Tag Archive conference

ByAdele Hars

SOI Consortium & Members at Samsung Foundry Forum (14 May, Santa Clara, CA)

For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you’ll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem.

There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners.

SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.

Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.

ByAdele Hars

FD-SOI for Near-Threshold-Voltage Design? It’s a Good Knob, Say #55DAC Expert Panelists

That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a  #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point.

Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings.

The original goal of the panel was “…to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet ‘always-on’ market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.”

(Update 2 August 2018:  a complete video of this panel is now available on YouTube — click here to view it.)

#55 DAC Expert Panel: How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? Left to right: Brian Fuller, Arm (moderator); Scott Hanson, Ambiq Micro; Lauri Koskinen, Minima Processor; Mahbub Rashed, GlobalFoundries; Paul Wells, sureCore. (Organized by Jan Willis of Calibre Consulting)

The panelists included:

  • Scott Hanson – Ambiq Micro
  • Mahbub Rashed – GLOBALFOUNDRIES
  • Lauri Koskinen – Minima Processor
  • Paul Wells – sureCore Ltd., Sheffield

Brian Fuller of Arm served as moderator.

Panel organizer Jan Willis, Calibre Consulting

Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on!

#55DAC Expert Panel on Near-Threshold Voltage Sees Growing Opportunity Despite Challenges

First published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships & Marketing Executive

Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25.

Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what’s not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It’s required innovating throughout the design process including test where Scott said they had create their own “secret sauce” to make it work. Later on in the panel, Scott described designers in near-threshold as “picojoule fanatics” to overcome the limitations in design tools which are geared towards achieving performance goals.

Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design.

Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield.

Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor’s note: sureCore‘s CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.]

Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it’s gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there’s been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future.

~ ~ ~

This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original.

* As explained by Rich Collins of Synopsys in the TechDesign Forum: “Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. […] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on.  Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. […] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.

ByAdele Hars

RFSOI Short Course – Great Line-Up! (EuroSOI, March 2018)

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.

The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.

The talks, which are being given by a stellar line-up of experts, include:

  • RF SOI, fabrication, materials and eco-system – Ionut Radu Director of Advanced R&D, Soitec
  • Fundamentals of RF SOI technology – Jean-Pierre Raskin, Professor, UCL
  • 22nm FDSOI Technology optimized for RF/mmWave Applications – David L. Harame, RF CTO Development and Enablement, GlobalFoundries
  • RF SOI technology and components for 5G connectivity – Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti
  • Analog and RF design on SOI – Barend van Liempd, Senior Researcher, imec
  • Techniques and tricks for RF measurements on SOI – Andrej Rumiantsev, Director RF Technologies, MPI Corporation
  • FOSS TCAD/EDA tools for advanced SOI-device modeling – Wladek Grabinski, R&D CM Manager, MOS-AK
  • RF design flow for SOI – Ian Dennison, Design Systems Senior Group Director, Cadence

The course is being organized by SOI Consortium members Incize and Soitec.

BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs.

EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.

 

 

 

ByAdele Hars

China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth

The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.

These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.

Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Sciences in Shanghai giving a keynote address at the 5th Shanghai FD-SOI Forum. (Photo courtesy: Simgui and the SOI Consortium)

Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:

(Photo credit: Adele Hars)

Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.

The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.

The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.

FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.

RF-SOI coverage included pieces in leading publications such as China IC, EETimes China, EDN China, EEFocus and SemiInsights.

ByAdele Hars

EuroSOI 2017 – 3-5 April in Athens

The 2017 Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (ULIS) will be held April 3-5 in Athens, Greece. Although EuroSOI has been ongoing for many years, this marks the third year it joins forces with the ULIS conference. Sponsored by the IEEE and EDS, the goal is to create an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. As such, a key objective is to promote collaboration and partnership between different academia, research and industry players in the field. For more information, visit the EuroSOI-ULIS ’17 website.

ByAdministrator

Impressive! Soitec FD-SOI Press Conference in China = >150 Articles

FD-SOI makes sense for China. That was the key message SOI wafer leader Soitec made in a press conference on FD-SOI for a select group of journalists just before Semicon China this spring. News then quickly spread, and resulted in over 150 FD-SOI articles in the top China technology and business press.

Soitec also put together a super FD-SOI resource page, with lots of information in Chinese (you can see it here).

Soitec execs Thomas Piliszczuk, SVP of Marketing & Biz Dev and Christophe Maleville, SVP of the Digital Electronics BU joined forces with the CEO of the Chinese wafer company Simgui and the VP of the National Silicon Industry Group (NSIG). They made the case that FinFETs, bulk and FD-SOI will co-exist, FD-SOI is an excellent technology for China on two fronts:

  • for designers: who can create high-performance, low-power chips that can be manufactured for half the cost of FinFETs
  • for foundries: China fabs can take a bigger share of worldwide markets faster than they could with FinFETs

FDSOIecosystem

At its Semicon China ’16 press conference, Soitec highlighted the growing FD-SOI ecosystem (Courtesy: Soitec)

It was a powerful set of messages and clearly resonated throughout the press. Here’s a quick look (with a little help from Google Translate…) at what some of the top publications had to say.

ChinaByte

The ChinaByte article was one of many that reported on the key points that the Soitec folks made at their press conference, leading with the headline that FD-SOI can help the China innovation blueprint. Other points included:

  • fabs in China will use all the leading technologies, including FinFETs, but FD-SOI will provide a competitive edge for time-to-market and cost
  • FD-SOI is the best choice for chips that demand both high performance and energy efficiency
  • the ecosystem is growing fast, and Soitec is joining hands with companies in China to establish a strong local ecosystem
  • the FD-SOI wafer suppliers have achieved high-yield mass production

 CCINET

With a daily page views of over 1.7 million, CCINET is an influential site. The headline they ran was about how Soitec has promoted the ecosystem of FD-SOI and shares its innovate engineered substrates in China (link here). The thrust was that FD-SOI represents an opportunity for China. It covered the basics of FD-SOI, Soitec’s role as the leading global engineered substrate expert and partnerships in China with Simgui and Sitri, and FD-SOI’s strong ecosystem.

EETimes-China

EETimesChinaFDSOIimage001

(Courtesy: EETimes-China)

In a long and detailed piece, EETimes-China documented Soitec’s decade-long history in China, explained the special role of Soitec’s Smart CutTM technology in manufacturing the ultra-thin wafers for FD-SOI, then covered the scope of the ecosystem and the value propositions. There was also a follow-up piece by International Editor Junko Yoshida in the global edition of EETimes (see here).

And more!

Many publications focused on how Soitec and FD-SOI supports China’s innovation plan. They include: Power System Design; ECCN; Electronic Products China; 21ic; Electronic Engineering & Product World; EC.HC360; Microwave Journal; and China Electronic Market

EEFocusSoitecFDSOI

(Courtesy: EEFocus)

China Electronic News noted how FD-SOI supports “Made in China 2025”. The headline of the China Business Journal article (which got a lot of WeChat attention) positioned FD-SOI as a new choice for the semiconductor industry, and a chance for China become an industry leader. EEWorld cited Simgui’s and NSIG’s affirmation that FD-SOI adoption is moving fast and will have a bright future in China. EEFocus looked at how FD-SOI compares with FinFETs (very well!), and cites Soitec’s Maleville as saying FD-SOI represents a 6 million wafer/year opportunity in China by 2020.

SST/China called FD-SOI the best choice for mobile and IoT. Of course we can’t cover all the other articles here, but with the Soitec press conference having generated over 150 pieces in the China tech and biz press, that message is now clearly out there.

 

ByAdministrator

Silicon Valley FD-SOI Symposium Promises Best Ecosystem Line-Up Ever: ARM, Foundries, EDA, Designers, Experts & Users (13 April – free and open to all who sign up)

The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.

To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.

FDSOI_SanJose13Apr16It’s really a terrific agenda – check it out:

08:00AM – 09:00AM – Registration

08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium

09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything

09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO

10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption

10:30AM – 10:50AM – Coffee Break

10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit

11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP

11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing

12:20PM – 1:40PM Lunch

1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division

2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO

2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP

3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division

 

3:30PM – 4:00PM – Coffee Break

4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager

4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering

4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”

5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D

5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse

6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium

Seriously – this good. Plus during breaks you’ll want to check out the poster sessions with GSS, sureCore, Soitec, SEH and the SOI Consortium.

Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:

Doubletree Hotel San Jose

2050 Gateway Place

San Jose, California 95110, USA

If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org. logo_soiconsortium

ByGianni PRATA

Reminder re: top SOI Conference – IEEE S3S ’16 (SOI/3D/SubVt) CFP deadline April 15th. Keynotes: NXP, Skyworks, Qualcomm

S3SconflogoDon’t forget to get your paper submitted to the top conference with a major focus on the SOI ecosystem: the IEEE S3S (SOI/3D/SubVt). The Call For Papers (CFP) deadline is April 15, 2016. As we noted for you in ASN back in December, the theme of the conference, which will take place October 10th – 13th in San Francisco, is “Energy Efficient Technology for the Internet of Things”.

As of this writing, the following keynote speakers have been confirmed:

  • Ron Martino, NXP : “Advanced Innovation and Requirements for Future Smart, Secure and Connected Applications”
  • Peter Gammel, Skyworks : “RF front end requirements and roadmaps for the IoT”
  • Nick Yu, Qualcomm : topic TBAieee_logo_mb_tagline

Invited speakers include:

  • Jamie Schaffer, GlobalFoundries : topic TBA
  • Philippe Flatresse, ST Microelectronics : “Body bias and FDSOI for Automotive”
  • Akram Salman, Texas Instruments : “ESD for advanced digital and analog technologies”
  • Xavier Garros, CEA-Leti : “Reliability of FDSOI”

As always, there will be a Best Paper Award and a Best Student Paper Award. But students take note: the recipient of the Best Student Paper will also receive $1000 from Qualcomm.

Papers related to technology, devices, circuits and applications (more details here) in the following areas are requested :

  • SOI
  • 3D Integration
  • Subthreshold MicroelectronicsEDS-Logo-Reflex-Blue-e1435737971222

For current information on the conference visit the S3S website at: http://s3sconference.org/

LinkedIn users will also want to join the conference group at IEEE SOI-3D-Subthreshold Microelectronics Technology (S3S) Unified Conference.

ByGianni PRATA

China Design Conference (April 2016) Adds RF-SOI Design Track

EdiCon16EDI CON China 2016, taking place April 19-21 in Beijing at the China National Convention Center (CNCC) will feature a keynote talk by GlobalFoundries‘ Peter Rabbeni, Sr. Director, RF BU Business Development & Product Marketing. The talk, entitled, “RF SOI: Revolutionizing Radio Design Today and Driving Innovation for Tomorrow”, will kick off the newly added RF-SOI Technology Track. The SOI Track will also feature talks and workshops from Peregrine Semiconductor, TowerJazz, Simgui, AnalogSmith and Shanghai Jiao Tong University. The talks will cover substrate engineering, design enablement, CMOS power amplifier design techniques and highly integrated control devices.

Mr. Rabbeni’s keynote talk will cover how there has been dramatic growth in RF SOI over the last several years in its continued march in driving performance improvement, cost reduction and architecture innovation between the transceiver and the antenna in mobile radios. No other radio technology in recent memory has had the impact that RF SOI has had in this respect. With standards becoming increasingly more challenging and the pending introduction of 5G, RF SOI is expected to continue to play an important role in the development of innovative architectures. His presentation will explore where we have been, why and where we may be headed with this technology. Substrate engineering and SOI device technology is reviewed in detail in Microwave Journal’s October 2015 cover story at http://www.microwavejournal.com/articles/25255.

More information is available at www.ediconchina.com.

ByGianni PRATA

Call for submissions to FD-SOI IP Workshops (prizes!): Dresden (March), Bangalore (April), Shanghai (Sept), Grenoble (Dec)

 

Design & Reuse, in partnership with GlobalFoundries, ST, Soitec and Leti, is sponsoring a series of FD-SOI IP Workshops around the globe. (Click here for more information.) These working days aim at sharing information about IP that’s currently available or is being designed for FD-SOI technology.

The first conference will take place during DATE in Dresden on 14 March 2016. Following that, conferences will also be held in Bangalore in April, Shanghai in September, and Grenoble in December.

Short summary submissions are now being solicited from designers offering IPs that are either currently in validation, are already silicon-proven, or are in production. The deadline for submissions to the Dresden event is 15 February. A prize will be awarded to the most innovative IP.

FD-SOI specific design flow or module presentations are also welcome.

The organizers are all members of the European Things2Do program (read about that here), which includes about 50 partners working on the FD-SOI ecosystem.