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ESSDERC/ESSCIRC 2009

14-18 September 2009 – Athens, Greece

www.essderc2009.org

The European Solid-State Device Research Conference (ESSDERC) and the European Solid-State Circuits Conference (ESSCIRC) provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.  It encourages deeper interaction among technologists, device experts, and circuit and system designers.

ESSDERC papers:

  • Migrating from Planar to FinFET for Further CMOS Scaling: SOI or Bulk?
    T. Chiarella, et al. (IMEC, Qimonda)
  • Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI Devices for 32nm Node and Below
    C. Fenouillet-Beranger, et al. (CEA-Leti, ST, IMEP, Soitec)
  • An Experimental Study of Temperature Influence on Electrical Characteristics of Ferroelectric P(VDF-TrFE) FETs on SOI
    G. Salvatore, et al. (Polytechnique Lausanne)
  • Analog, RF and Nonlinear Behaviors of Submicron Graded Channel Partially Depleted SOI MOSFETs
    M. Emam, et al. (UC Louvain, FEI Brazil, IEMN)
  • Electrothermal Simulation and Measurements of SOI for Smart Power Transistors for Short Pulses
    Jurgen Teichmann, et al. (Atmel, Telefunken)
  • A Simple and Efficient Concept for Setting Up Multi-VT Devices in Thin BOx Fully-Depleted SOI Technology
    JP Noel, et al. (Leti, SEP)
  • Drain / Substrate Coupling Impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with Undoped Channel
    S. Burignat, et al. (Microware Laboratory, UC Louvain, Leti)
  • Impact of Work Function Design on the Stability and Performance of Ultra-Thin-Body SOI Subthreshold SRAM
    V PH Hu, et al. (National Chiao Tung U.)
  • High-Frequency Performance of Dopant-Segregated NiSi S/D SOI SB- MOSFETs
    C. Urban, et al. (IBN, JARA, UC Louvain)
  • Comparison Between 65nm Bulk and PD-SOI MOSFETs: Si/BOX Interface Effect on Point Defects and Doping Profiles
    EM Bazizia, et al. (ST, LAAS/CNRS, CEMES/CNRS, Fraunhofer)
  • Electron Magnetoresistance Mobility in Silicon on Insulator Layers Using Kelvin’s Technique
    J. Antoszewski, et al. (U. Western Australia, Soitec, IMEP-INP)
  • The Influence of Orientation and Strain on the Transport Properties of SOI Trigate nMOSFETs
    Tienda-Luna, et al. (U. Granada)
  • Width and Orientation Effects in Strained FDSOI MOSFETs: Strain and Device Characterization
    S. Baudot, et al. (INAC, Leti)
  • Power Transistor Design Guidelines and RF Load-Pull Characterization of a 0.13-?m SOI CMOS Technology
    F. Carrara, et al. (U. Catania, ST)
  • Simulation of gate leakage currents in UTB MOSFETs and Nanowires
    A. Schenk  (ETH-Zentrum)
  • Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET
    Arrays

    D. Sacchetto, et al. (Ecole Polytechnique Fédérale de Lausanne)
  • High-Performance Si Nanowire FET with a Semi Gate-Around Structure Suitable for Integration
    S. Sato, et al. (Tokyo Institute of Technology, Waseda U.)
  • Hot carrier (HC) and Bias-Temperature-Instability (BTI) degradation of MuGFETs on silicon
    oxide and silicon nitride buried layers

    C.-W. Lee, et al. (Tyndall, Texas Instruments, George Mason U.)

ESSCIRC papers:

  • A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with on-Chip Tunable Matching Network for Enhanced Efficiency in Back-Off
    F. Carrara, et al. (U. Catania)
  • A 60GHz Power Amplifier with 14.5dBm Saturation Power and 25% Peak PAE in CMOS 65nm SOI
    A. Siligaris, et al. (Leti, ST, NEC, IEMN)
  • FinFET RF Receiver Building Blocks Operating Above 10 GHz
    D. Siprak, et al. (Infineon, IMEC, Vrije U.)

Breakthroughs at the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More

Less Than Ever

Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation.

In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research Laboratory demonstrated that the planar FDSOI devices fabricated on SOTB have the smallest Vth variability among planar CMOS due to low-dose channel and back bias control. Read More