IC makers need both local and global strained SOI to win the GHz race.
At the device level, the switching speed of MOS logic transistors (gate delay) is limited by two factors:
1. The times required to charge and discharge the parasitic capacitances that exist between electrodes and the body substrate.
2. The transit time of charge carriers through the channel, which is dependant on transconductance gm = µ Cox (W/L), where µ is the carrier mobility (µe, µh) and Cox is the gate oxide capacitance. Read More
Freescale and Soitec Group announced the results of their joint development effort to optimize CMOS device performance at the sub-65-nm nodes using strained silicon-on-insulator (sSOI) engineered substrates. With device results revealing an approximate 70-percent increase in electron mobility, as well as high compatibility with existing SOI CMOS processes, the collaborative effort demonstrated that 45-nm CMOS devices built using strained SOI substrates can effectively take device performance to the next level— ultimately enabling Freescale to bring faster, more power-efficient next-generation chips to market. • Read More
STMicroelectronics recently delivered a 65-nm CMOS SoC design platform for development of next-generation products for low-power, wireless, networking, consumer, and high-speed applications. SOI extensions are at an advanced stage of development and will be available soon, the company said.
When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management.
The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves significantly the high- frequency behavior of the chip: first, because the buried insulating layer reduces part of the electromagnetic field propagation; second, because bonded SOI technology enables the use of a highly resistive (intrinsic silicon) handle wafer, dramatically reducing both resistive losses and crosstalk. Read More
SOI CMOS processes using partially-depleted transistors, most commonly used in current advanced SOI processes (90nm and 65nm nodes), have already proven their performance advantage in CPU applications.
When compared with bulk CMOS at same power-supply voltage (Vdd) and same leakage current, SOI delivers a higher speed thanks to:
• the combination of a lower junction capacitance,
• an increased drive current during transition of the gates due to dynamic capacitive coupling
• and an improved drivability of gates using stacked transistors (NAND, NOR, etc.). Read More