Tag Archive DSP

FD-SOI, Body-Biasing Shine in 10x Faster DSP With Ultra-Wide Voltage Range

Body-biasing design techniques, uniquely available in FD-SOI, have allowed STMicroelectronics and CEA-Leti to demonstrate a DSP that runs 10x faster than anything the industry’s seen before at ultra-low voltages (read press release here).

In the mobile world (not to mention the IoT), the role of DSPs is becoming ever more important. All those things you do with your phone – snapping pictures, listening to music, watching video, oh yeah, even talking and listening –  involve the DSP’s number-crunching prowess. It takes real-world analog information that describes sound, pressure, light, and temperature and mathematically optimizes and processes them in real-time, so the data can be displayed, analyzed, compressed, enhanced, or converted. The DSP’s raison d’etre is to maximize work-per-clock-cycle.

When product designers talk about “user engagement” with their portable device, chances are there’s a DSP involved. And the better the DSP does its job, the cleaner your sound, the clearer your picture, the faster your download, and the more easily you can converse. But all this processing comes at a price – an energy price.  Chip designers are always looking for better ways to improve the power-performance trade-off, so that we as users get all this great performance without running out of batteries.

Power is directly proportional to clock frequency (MHz, GHz) and the square of the voltage that’s supplying the device. So, if you have a device that operates at higher frequencies with lower supply voltages, you’ve got a big edge on saving power – and of course, the less power you pull from your battery, the longer your battery will keep you snapping, listening, watching, and conversing.

That’s what’s at play here with this Leti/ST news. They’ve demonstrated a DSP that can hit 500 MHz while pulling just 460mV – that’s ten times better than anything the industry’s seen so far.

In fact, Fabien Clermidy, head of Digital Design and Architecture at Leti told ASN that this could mean extending your battery life by about another 30% for typical usages.

Leti and ST showed the FD-SOI DSP at ISSCC – the IEEE’s International Solid-State Circuits Conference (February 2014), which is widely considered the premier forum for presenting advances in solid-state circuits and SOCs.


Ultra-Wide Voltage Range

Specifically, at ISSCC Leti and ST presented the successful demonstration of an ultra-wide-voltage range (UWVR) DSP, based on 28nm ultra-thin body buried-oxide (UTBB = ST and Leti’s flavor of) FD-SOI technology.

This may be the first you’ve heard of Leti/ST’s UWVR, but it’s been making the conference rounds over the last year. Leti/ST presented it at the DATE Conference in 2013. (You can get the paper on the IEEEXplore site – click here.) In that paper, Leti and ST engineers demonstrated the technology on an ARM A9, where they showed performance boosted by 40% to 200% without added energy cost. Conversely, when saving power is more important than boosting performance (which turns out to be about 90% of the time!), FD-SOI reduced leakage power by a factor of 10 using Reverse Body Biasing.

Leti and ST also presented FD-SOI in the memories section at ESSCIRC ’13, where they applied it to a 28nm FD-SOI SRAM bitcell array, noting “…over 10x energy gain is achieved from 1.2V down to 0.35V range while measuring high speed at nominal voltage.” (This paper is also available from the IEEEXplore site – click here.)

In the case of the demonstrator DSP presented at ISSCC, the demonstrator was  produced by ST in their 28nm UTBB FD-SOI process technology. The UTBB FD-SOI allows:

  • body-bias-voltage scaling from 0V to +2V,
  • decreased minimum circuit operating voltage,
  • and clock-frequency operation of 460MHz at 400mV.

To the UWVR innovation, ST and Leti have added optimized standard-cell libraries they had developed to cover the 0.275V to 1.3V range. They then were able to leverage the voltage scaling they get with FD-SOI with system clocking techniques in the optimized cells, including:

  • non-overlapping pulses;
  • fast pulse-triggered flip-flop devices designed for variability tolerance at low voltage;
  • monitoring on-chip timing-margins to dynamically adjust the clock frequency to a few percent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology.

As a result, even at 0.4V, the DSP exhibits 10x better operating frequency than the previous state-of-the-art.


(Courtesy: ISSCC, STMicroelectronics, CEA-Leti)

Clermidy also adds that their innovative design techniques reduced design margins, thus avoiding over-design. Again, doing this in FD-SOI rather than bulk was key, since FD-SOI really reduced variability issues.

The Leti/ST ISSCC paper, which is entitled, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented on Feb. 12, during Session 27, “Energy-Efficient Digital Circuits..  A demonstration kit was shown to attendees. As of this writing, it’s not yet been posted on the IEEEXplore site, but it should be in the weeks to come.

Leti, ST Demo Order-of-Magnitude-Faster, Ultra-Low Power DSP on 28nm FD-SOI

CEA-Leti and STMicroelectronics presented an order-of-magnitude-faster FD-SOI Ultra-Wide-Voltage Range (UWVR) DSP at ISSCC ’14. The device was produced by ST in 28nm UTBB FD-SOI. It allows body-bias-voltage scaling from 0V to +2V, decreases minimum circuit operating voltage and supports clock-frequency operation of 460MHz at 400mV.

“This demonstration DSP shows that FD-SOI is blazing the trail for better portable and battery-powered products, using more efficient semiconductor chips, all the way down to the 10nm node,” said Philippe Magarshack, Executive Vice President, Design Enablement Services, STMicroelectronics.

The Leti/ST paper, entitled, “A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, Embedding Fmax Tracking,” was presented during Session 27, “Energy-Efficient Digital Circuits”.  A demonstration kit was shown to ISSCC attendees. ISSCC – the International Solid-State Circuits Conference – is the flagship conference of the Solid-State Circuits Society. It is widely considered the premier forum for presenting advances in solid-state circuits and systems-on-a-chip.

Freescale’s 45nm SOI products continue making news

Freescale‘s 45nm SOI products continue making news:

• The DSP lineup grows with the new MSC8157 and MSC8158, based on Freescale’s SC3850 core running at 1.2 Ghz — which recently earned the highest BDTIsimMark2000™ fixed-point performance score of any DSP architecture tested to date by independent signal-processing firm Berkley Design Technology, Inc (BDTI).

• Yet another in a series of key DSP design win – this with ZTE for wireless 3G/4G base stations.

• The new QorIQ P1014 is an energy-efficient processor for digital video recorders, storage products and other cost-sensitive “end-of-the-network” applications.

• At the heart of a new, comprehensive silicon/software solution multi-service business gateway (MSBG) equipment (combining data, security, voice and fax), the QorIQ P1020 processor enables simplified, fanless thermal design for higher reliability and low system-cost end products.

New SOI-based products from Freescale

New SOI-based products from Freescale:
• the MSC825x family of programmable DSPs delivers the optimal blend of low cost and the industry’s highest performing core for a broad range of medical, aerospace/defense and test/measurement applications.
• the QorIQ P1012/P1021 for communications equipment applications – the first processors based on its QorIQ communications platform that also incorporate QUICC Engine multiprotocol technology.

Freescale’s SOI-related news includes

Freescale’s SOI-related news includes:
– The company has joined the IBM technology alliance, covering SOI technologies as well as advanced semiconductor research and design enablement transitioning at the 45nm generation. Freescale is the first partner in the alliance to participate in both low-power and high-performance technology research and development.
– The latest in its 85xx line of SOI-based PowerQUICC III processors: the MPC8544E. Freescale says it’s one of the industry’s lowest power-consumption SoCs to deliver gigabit performance, consuming only 3.75 W typical core power and greatly reducing the challenges of thermal management in performance-driven, fanless embedded applications.
– Q2 2007 sampling of its line of MSC8144 quad-core DSPs. Based on Freescale’s 90-nm SOI, the devices embed four StarCore SC3400 DSP cores each running at up to 1GHz, generating equivalent performance to a 4GHz single core DSP.

Freescale’s newly introduced Quad-Core MSC8144

Freescale’s newly introduced Quad-Core MSC8144 is built on 90 nm SOI technology. Based on next-generation StarCore™ Technology, it is billed as the industry’s highest-performance fully programmable DSP, delivering performance equivalent to a 4 GHz single-core DSP.