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FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.


FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.


FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)


The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.


Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.


FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.

Samsung & ST 28nm FD-SOI Is Major Opportunity, Says IBS (EETimes)

In an EETimes blog, Handel Jones of IBS says that the Samsung-ST FD-SOI announcement represents a major opportunity. (Read full blog here.) “Samsung Electronics has a major opportunity with its large wafer capacity to support low-leakage products with its 28 nm FD-SOI process,” he wrote. “Cadence Design Systems, Synopsys, and Mentor Graphics are all supporting the FD-SOI ecosystem, and the transition from 28 nm bulk HKMG to FD-SOI should be inexpensive.” He goes on to say, “It is also important to be able to transition the smartphone vendor base to China and meet the aggressive pricing structures of the China market, which can be done with FD-SOI. Adopting FD-SOI gives a high probability of having a cost-competitive and low-power option for high-volume mobile platforms.”

Interview: Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain

Interview with : Christophe Maleville (Soitec) on Wafers in the FD-SOI Supply Chain

With FD-SOI entering the mainstream, fabless designers have been asking about the wafer supply chain. ASN spoke about it with Christophe Maleville, Sr. VP of the Microelectronics business unit at Soitec, the world’s leading SOI wafer producer.

MalevilleChristophe Maleville has been Senior Vice President of Soitec’s Microelectronics BU since 2010. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production, and managed customer certifications. He also served as Vice President, SOI Products Platform at Soitec, working closely with key customers worldwide. He has authored or co-authored more than 30 papers and also holds some 30 patents. He has a PhD in microelectronics from the Grenoble Institute of Technology and obtained an Executive MBA from INSEAD.


Advanced Substrate News (ASN): With the recent news that Samsung has joined the ranks of foundries offering high-volume 28nm FD-SOI, can you tell us why customers are turning to FD-SOI?

Christophe Maleville (CM):   The short answer is that they consider FD-SOI provides a much better combination of power consumption, performance and cost than any alternative for the technology node they target.

At 28nm, FD-SOI gets them an unprecedented combination of performance and power consumption for a cost comparable to that of standard low-power 28nm technology, making 28FD an extremely attractive alternative to any flavor of bulk CMOS at this node. And for some products at least, using this enhanced 28nm is actually a better choice than going to the next node.

Then 20nm FD-SOI (also called 14FD) will provide the kind of performance and energy efficiency promised by 16nm/14nm FinFET, at a lower cost than even 20nm planar bulk CMOS.

ASN: Who are the wafer suppliers and what kind of capacity is there?

CM:  There are three major suppliers serving the FD-SOI market:  Soitec, Shin-Etsu Handotai (SEH) and SunEdison (formerly MEMC).  SEH is the world’s biggest producer of silicon wafers. Soitec is the world leader in SOI wafer manufacturing. SunEdison has been supplying SOI wafers for over a decade.  SEH and Soitec use Soitec’s Smart CutTM manufacturing technology.  However, each company fine-tunes the technology to meet to its customers’ specifications.

For our part, I can add that Soitec has two distinct production sites. We source the raw bulk base and donor wafers (from which the FD-SOI wafers are fabricated under our FD-2D product name) from a diverse group of suppliers, which enables us to optimize the quality of our wafers, combining the best wafers for donor and handle. We are converting capacity at our plants in France and Singapore to meet expected FD-SOI demand.

The industry’s current installed capacity is in the range of one million 300mm SOI wafers/year. However, the wafer suppliers are ready to expand capacity to meet market demand, so we could easily reach two million in well under a year, and continue ramping rapidly from there. It’s perhaps worth understanding that the equipment and materials needed to manufacture SOI wafers are standard industry hardware and materials – there are no exotic parts to the manufacturing equipment nor rare materials that could cause bottlenecks in the processes we use to manufacture the SOI wafers.


ASN:  FD-SOI wafers are known to have very stringent requirements. Can you review those here?

CM: SOI wafers are subject to many of the same criteria as other advanced wafers, such as flatness and defectivity.  The additional parameters for FD-SOI wafers, which require tight control, are:

  • the top silicon thickness,
  • the top silicon uniformity,
  • and the BOX (Buried OXide – the insulating layer).

The thickness of the top silicon of the SOI wafers (denoted as TSOI) we provide ranges from 10 to 16nm, depending on customer requirements and node. The top silicon essentially “pre-defines” the channel. But, it’s important to remember that the starting thickness of the top silicon in the wafer has to be a little thicker than you’ll find in the processed device, as a few nanometers of top silicon is etched away during device processing.  So in a TEM of a 28nm FD-SOI transistor, you might see TSOI of 7nm, but the wafer that it started on would have had top silicon of 12nm, to accommodate the 5nm that would be etched away during processing.


In FD-SOI, the BOX layer is actively leveraged in back biasing, wherein you’re essentially creating a second (“back”) gate. This makes the parameters of the BOX layer especially important for ultra-low power operation.


ASN:  Why do the wafers have to be so uniform?

CM: With respect to the top silicon uniformity, uniform thickness is crucial to controlling transistor threshold voltage (Vt) variability. The top silicon uniformity of Soitec’s FD2D wafers is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. For the BOX thickness, we can offer thicknesses ranging from 10nm to 25nm, again depending on the customer’s approach.  Technology’s like ST’s UTBB (ultra-thin body and Box) leverage very thin BOX for body biasing, which gives them a big edge in performance and low-power.


ASN: Are suppliers really ready to produce these wafers in high volumes?



CM:   Yes, at Soitec we announced that we were ready for FD-SOI wafer volume back in 2012. Having met the specifications, we focused on offering good yields to our customers. In fact, the yield for Soitec’s FD-2D substrates is already reaching the yields we have for our wafers for partially-depleted SOI, which we’ve been selling for over a decade. This was critical to our clients, in order for them to have a fully-qualified 28nm FD-SOI process using wafers from Soitec and other suppliers. The results that customers have demonstrated in terms of variability (especially for Vt distribution, which is closely linked to wafer uniformity) and the electrical results show the wafers fully meet their production requirements. Smart CutTM technology enables us to manufacture according to these stringent requirements, and our years of experience let us move into high-yield, high-volume FD-SOI wafers at the right cost and at the right time for the market.


ASN: Can wafer suppliers adapt to the fluctuations in demand seen in very high-volume markets?

CM:  The SOI ecosystem is already familiar with the mobile market, which in terms of volumes is currently the world’s biggest market – and certainly is volatile. SOI wafers are widely used in RF, particularly in RF switches, where over 70% of the devices for smartphones are built on SOI.  While wafers for RF have some specific parameters, generally speaking the FD-SOI wafers are produced using similar technology, flow and logistics as our SOI wafers for RF – so for us, it’s just another segment of the mobile market.


ASN: Some say that managing buffer wafer stocks would be too complicated for the foundries – is that true? Can you explain briefly how the wafer supply contracts are typically structured?

CM: The SOI supply chain is no different than the bulk supply chain. As such, the structure of the wafer supply model is similar to supply chains in other industries. The foundries don’t have to fully own and manage a costly buffer stock of wafers. In the case of large customers, they typically negotiate a supplier-managed inventory dedicated to their needs, and they only pay when they actually consume parts from this stock.  This kind of buffer also helps smooth out possible rapid fluctuations of the demand.


ASN:  For its latest report (which found that FD-SOI is the most cost effective approach for the 28nm an 14nm nodes), IBS uses the figure of $500/wafer. Is that realistic?

CM: While of course pricing depends on commercial negotiations, 500USD in volume for 28nm FD-SOI wafers is definitely a sensible budgetary price: conservative and achievable. And starting at the 28nm node, as IBS points out, using SOI wafers results in similar cost for processed wafer when compared to typical 28nm bulk reference – a phenomenon that gets even better with scaling to 14nm. And although the specifications for the 14nm wafers are more exigent, we confirmed that substrate cost increase will not exceed 10%.


ASN: What about the future – will the wafers be able to meet the specs for the 10nm market? What about the move to 450mm wafers?

CM: ST has indicated a 3-node FD-SOI roadmap: 28nm-14nm-10nm. Working with our partners, we’ve shown that from the perspective of the wafer specs, we can fully comply with the parameters required to support this. For example, we have engineered strained silicon that meets the 10nm node specifications for boosting mobility – there are no show stoppers here. In terms of 450mm, while it seems unlikely that the move is imminent within the next few nodes, we are full participants in the industry’s R&D efforts, and have demonstrated that with our Smart Cut technology using the standard toolset found in CMOS FEOL, we can produce 450mm versions of our FD2D wafers, when and if the need arises. We’re ready whenever the industry is.

SemiWiki: FD-SOI’s the Technology to Continue Moore’s Law

A new SemiWiki post by Dr. Eric Esteve of IPnest entitled, The Technology to Continue Moore’s Law… (click here to read it) argues that FD-SOI is the right choice.  He explores cost and manufacturing considerations, and looks at the design issues in logic, memories and analog.  A highly recommended read.

ST Article in EETimes Details How FD-SOI Supports Moore’s Law



A powerful, detailed article in EETimes-Asia details how FD-SOI Supports Moore’s Law (click here to read it).  Written by Laurent Remont, ST’s VP and GM for Technology and Product Strategy, Embedded Processing Solutions, it explores FD-SOI’s advantages in terms of price, power and performance versus planar bulk CMOS and FinFETs and 28nm and 14nm.

Remont explains how structurally it is the most cost-effective sub-30nm process technology because FD-SOI is much simpler. In an interesting twist, he goes on to describe how forward body biasing (FBB) allows for dynamic power / leakage / frequency tuning linked to datacenter load. “With this, energy use would be proportional to workload and FD-SOI could reduce global data center power by up to 50 per cent,” he says.

In terms of performance, he says, “…the switch from 28nm Bulk CMOS to 28nm FD-SOI can improve circuit speed by as much as 35%. Even with this performance, FD-SOI transistors run cooler, because of lower leakage, wider voltage scaling and FBB all leading to higher power efficiency.

He concludes that FD-SOI will enable the industry to validate Moore’s Law down to 10nm. A highly recommended read.

Why Migration to FD-SOI is a Better Approach Than Bulk CMOS and FinFETs at 20nm and 14/16nm for Price-Sensitive Markets

By Handel Jones

IBS has recently issued a new white paper entitled Why Migration to 20nm Bulk CMOS and 16/14nm FinFETs Is Not the Best Approach for the Semiconductor Industry.  The focus of the analysis is on technology options that can be used to give lower cost per gate and lower cost per transistor within the next 24 to 60 months, covering the 28nm, 20nm and 14/16nm nodes.

We conclude that:

  • at 28nm and 20nm, the lower power consumption and higher performance of FD-SOI compared to planar bulk CMOS gives major competitive advantages to FD-SOI in high volume portable applications.
  • the lower cost of FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI for high volume applications at this technology node.

Here is a brief summary of our findings.



High volume applications need lower cost per transistor in order to use the new generation of process technologies. It is, consequently, appropriate to evaluate the options for continuing the pattern of lower cost per gate, with the analysis of different technology options.

After the 28nm node, the decreasing cost-per-gate trend with reduction in feature dimensions for bulk CMOS is reversed: at 20nm, cost-per-gate starts to increase rather than decrease.

Cost Per Gate Reduction Trends

(Source: IBS)


The impact of not reducing cost per gate is one of the most serious challenges that the semiconductor industry has faced within the last 20 to 30 years. It is, consequently, appropriate to evaluate whether other options are available that can allow scaling to 20nm and smaller feature dimensions to be effective in cost and power consumption because of the large financial impact on the semiconductor industry of not continuing with Moore’s Law.


Wafer Cost Analysis

 Our analysis considers depreciation, equipment maintenance, direct/indirect labor, facilities, wafer cost, consumables, monitor wafers and line yield.

 Already at 28nm, the wafer cost is lower for FD-SOI than for bulk HKMG CMOS, although with a relatively small difference. The key reason for the lower cost of FD-SOI is the smaller number of mask and processing steps.

 The cost analysis is based on eight-layer metal and 3Vt levels. The following graph is built from the more detailed analysis in our report.


Furthermore, while the difference in total yielded wafer cost at 28nm and 20nm is not very large, it is very important to remember that the FD-SOI technology has the added advantage of providing significantly lower leakage and higher performance than the bulk CMOS.

The reality is that performance of 28nm FD-SOI is 15% better than 20nm bulk CMOS and extends the lifetime of the 28nm technology node. Lower cost, lower power consumption, higher performance, the conclusions are clear.

The situation is even more compelling at 14/16nm.

The wafer cost for 14nm FD-SOI is 18.4% lower than 16nm FinFET.  A key factor contributing to the high cost of FinFET wafers is that of the extensive inspection steps required to ensure high yield and high reliability. A number of wafer processing steps need to be tightly controlled and monitored with the processing of FinFET structures. The result is that depreciation cost per wafer for FinFET structures is significantly higher than for FD-SOI.

Note: the generation we call 20nm FD-SOI in our report is called “14FD” by ST Microelectronics, as they also position it as a competitor to 14/16nm FinFET.


Die Cost

While wafer cost is an important factor, die cost is a more vital factor for most companies. Our analysis includes yielded wafer cost, gross die/wafer and yield. 


At 28nm, FD-SOI has higher yield, slightly lower die cost (3%) and 30% lower power consumption than bulk CMOS. At 20nm, FD-SOI die cost is 13% lower than bulk CMOS, has higher yield, and is expected to provide 40% lower power consumption.

At 14nm/16nm, the FD-SOI die cost for a 100mm2 die is 28.2% lower than the bulk FinFET die cost and has higher yield. The leakage of FD-SOI devices is projected to be comparable to that of FinFET devices.

The lower cost of the FD-SOI die compared to 16nm FinFET die provides an overwhelming advantage to utilizing FD-SOI at this technology node.

However, despite the fact that FD-SOI is clearly more cost effective, large investments are being made by the pure-play foundries in 14/16nm FinFET wafer processes, and while FinFETs will be needed in the future, the issue is timing. It is clearly in the interest of the fabless industry to pay lower die prices, and collaboration with the foundry vendors is needed in this arena. The power structure in the industry has moved too much in favor of the provider rather than the user.

For the fabless industry, the key requirement for FD-SOI is to establish supply chains that can support the participation in high-volume end markets. The fabless companies need to be much more active in ensuring that their needs are being satisfied.

Strategic Considerations Within the FD-SOI Supply Chain

Strategic considerations within the FD-SOI supply chain include the following:

  • Complex, working products with FD-SOI at 28nm have been demonstrated by STMicroelectronics with significant performance and power consumption advantages compared to bulk CMOS.
  • The supply chain for FD-SOI starting (i.e., raw) wafers is in place (by Soitec, SunEdison, and Shin-Etsu Handotai (SEH)) and can be expanded rapidly to provide the required wafer capacity if a demand environment is established.
  • The use of body biasing provides significant performance and power consumption advantages for FD-SOI. Body-biasing methodologies for FD-SOI can use EDA tools that have been developed for bulk CMOS technology.  Also, design flows for FD-SOI are effectively identical to those for bulk CMOS. However, it is important for the EDA vendors to become more proactive regarding the potential opportunities for FD-SOI.
  • Libraries and basic IP developed for bulk CMOS can be easily modified for FD-SOI. The cost of modification between bulk CMOS and FD-SOI is approximately 10% of that required to migrate to a new technology node for bulk CMOS at 20nm.

An ecosystem needs to be set up for FD-SOI, and it is important for the electronics industry that this ecosystem is established.


There are many advantages for FD-SOI to be widely adopted for high volume, low cost, and lower power applications in the future. It is important for the semiconductor industry to be willing to make investments to provide optimum solutions to its customers rather than follow the roadmap of a specific company. The fabless companies need to be proactive in supporting the supply chain within an FD-SOI ecosystem.

Timing of the migration to 20nm, 14nm, and 10nm technology nodes need to be based on cost, power consumption, and performance metrics that can be easily verified. Being short-term focused and not willing to adopt new concepts can have large cost penalties within the foundry-fabless environment.

FD-SOI technology can be viable in many applications for the next ten years. The semiconductor industry needs to be willing to make the investments for the future rather than responding to short-term pressures.

Cost penalties resulting from very high design costs and long time-to-market can have a serious impact on the competitiveness of semiconductor vendors that select the FinFET approach at 14/16nm. Semiconductor companies that are participating in fast-moving markets cannot tolerate the additional costs of design and long time-to-market associated with trying to fine-tune technologies that are inherently high cost.

While migration to FinFETs may be required beyond the 10nm node, until then FD-SOI represents the best approach for many of the high volume segments of the semiconductor industry.

The reality is that the foundry vendors will not invest unless they have a high probability of getting customers. This means that the customers need to provide the leadership and accept that the present roadmaps in the industry will not provide them with the best financial returns.

FD-SOI Keeps Moore’s Law on Track

Take a look at this graph – it’s obvious, isn’t it? FD-SOI is significantly cheaper, outdoes planar bulk and matches bulk FinFET in the performance/power ratio, and keeps the industry on track with Moore’s Law.

Sans titre

This was part of a presentation by ST’s Joël Hartmann (EVP of Manufacturing and Process R&D, Embedded Processing Solutions) during Semi’s recent ISS Europe Symposium.

If you’re a designer, and you want faster-cheaper-cooler, you’ll go with FD-SOI, right? You can leverage existing designs, it’s an easy port of IP, and you get terrific power-performance benefits from back biasing.

Which leads to the question: is FD-SOI really what’s best for the industry, too? From the designers’ and fabless perspective, it’s a clear “yes!”

Of course, the pure-play foundries clearly need the volumes to make FD-SOI worth their while. We all remember last year when this GloFo slide made the rounds (it was shown at the SOI Consortium workshop in Kyoto, Japan last summer – see the full ASN article here):


When I spoke to Subi Kengeri, GloFo’s VP Advanced Technology Architecture at a developers event this past fall, he said that GloFo was enthusiastic about the prospects for FD-SOI. But the foundry giant was still considering its options, while comparing FD-SOI to (bulk) FinFETs. While FD-SOI comes out a winner when leakage is the primary issue, he said, GloFo potentially sees a bigger opportunity in FinFETs.

This was last fall, remember, and he said that some customers had expressed reservations about the difficulty of back-biasing in FD-SOI. Now surely with all we’ve heard about the amazing things you can do with back-biasing in FD-SOI (click here if you need a refresher), nobody really thinks it’s hard anymore, do they?

So why should the fabless world swallow a major and very costly veer off the trend line of Moore’s Law just to do FinFETs at this point?

Subi told me, “We are a foundry and are here to serve our fabless customers.” He said if there is serious high-volume customer interest in FD-SOI, they can make it happen.

ST’s now indicated that a big foundry announcement will be made shortly, which is very exciting. (Read about that here if you missed it before.)

So, the foundries can make it happen.  And they will. Because maintaining cost-efficiencies is what makes this industry tick.  Ultimately, the best interests of the industry will always prevail. Just ask!

EU report: SOI-based technologies should play important role in capturing new markets

“High performing low power digital technology based on SOI” is an important part of the detailed plan submitted February 14th by the Electronics Leaders’ Group (ELG) to European Commission Vice-President Neelie Kroes.  (Press release here.) The group recommends the EU focus on:

  • Areas were Europe is strong – automotive, energy, industrial automation and security. The target is to double current production in the next 10 years.
  • New high growth areas, in particular Internet of Things (IoT) and the development of ‘Smart-X’ markets (e.g. smart homes, smart grids etc.).

The electronics industry CEOs said that Europe can capture up to 60% of new electronics markets, and double the economic value of semiconductor component production in Europe within the next 10 years.  “Advanced materials provide a path for breakthroughs and strong differentiation in silicon applications (Si-based, SOI, strain Si),” the report stated.

(It is worth noting that SOI is already well-represented in the areas cited for existing European strengths, with companies like NXP and ST producing enormous numbers of SOI-based chips for these markets.)

SOI Reliability Key to SiTime MEMS Lifetime Warranty


(Courtesy: SiTime)

The extreme reliability of SiTime’s MEMS devices, using SOI technology, has enabled the company to cover all its MEMS oscillators and clock generators with a lifetime warranty (press release here).

SiTime contributed an excellent article to ASN a few years ago (click here to read it), explaining how their radical SOI-based approach put the company at the top of the fast-growing silicon-based timing market.

Now, SOI plus excellent design, quality, manufacturability and reliability, has enabled the company to cover all its MEMS oscillators and clock generators with a lifetime warranty. The devices are setting new standards in quality and reliability, Piyush Sevalia,
Executive VP, Marketing at SiTime told ASN. The company has ascertained historic evidence of extremely low return failure rates (0.5 DPPM) with their SOI-based product lines.

FD-SOI could be “tipping point” for SOI, says supply chain expert

FD-SOI could be the “tipping point” for SOI, supply chain expert Bill Kohnen indicated in a presentation at the Semiconductor Technical Purchasing Conference last fall. (See his ppt here.) He suggested, “Purchasing and Supply Chain Organizations at Foundries and Device Manufacturers that need SOI wafers need to closely monitor the supply chain as demand resulting from FD-SOI applications may be the tipping point for capacity issues.”  He concludes that the industry consortiums will be helpful in avoiding a “bullwhip effect”.