Tag Archive EDA

Cadence Announces IP Availability for 28nm FD-SOI

Cadence has announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics. (See Cadence press release here.) On this new process node, the Cadence® Denali™ DDR4 IP supports up to 2667Mbps performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. In addition, the ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, which the company says is an ideal solution for inter-chip USB applications. Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process

ST adopts Synopsys IC Compiler for FD-SOI CPU/GPU implementations

Synopsys has announced that STMicroelectronics has standardized on Synopsys’ IC Compiler™ place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization.  As noted in the press release (read here) ST has a unique processor architecture made possible through their FD-SOI process technology.  An FD-SOI device can operate at significantly higher frequencies than an equivalent, traditional, bulk CMOS device. It can also run very fast at low voltages, providing much higher energy efficiency. The close collaboration between the ST design teams and Synopsys has led to a compelling implementation solution that fully exploits the performance and power promise of FD-SOI technology and provides the throughput needed to meet tight time to market windows.

“…you may hear more companies than just STMicro are doing a lot of designs on FDSOI, because in addition to cost equivalents, they get significant power savings and speed up,” Herb Reiter, founder and president of eda2asic told EDA Cafe in a recent interview.

“…you may hear more companies than just STMicro are doing a lot of designs on FDSOI, because
in addition to cost equivalents, they get significant power savings and speed up,” Herb Reiter,
founder and president of eda2asic told EDA Cafe in a recent interview. Adding that “…FDSOI […]
design requirements are just like bulk silicon and are almost totally transparent to the designers,” he
concludes, “…consider the savings in the fab, where you have fewer process steps and less
processing time. Also, remember that with each step in manufacturing, the yield decreases – the
bottom line is that FDSOI is becoming really cost competitive for most apps.”

Bulk logic designs for mobile apps port directly to FD-SOI

Bulk logic designs can be ported directly to FD-SOI for high-performing, low-power mobile apps.

Fully-depleted (FD)-SOI is a potential alternative to BULK 20nm. But what sort of the impact will that have on the design flow? The short answer is: very little.

Designs for low-power mobile applications in 28nm bulk benefit significantly in terms of increased performance and decreased power when ported to 20/22nm fully-depleted (FD)-SOI. From the designer’s perspective, the port is essentially direct – really no different from any standard port to a smaller geometry.

Interconnects, routing and RC parasitics are identical. Logic, memories, low- and high-voltage I/O and analog parts are handle in the same way as on bulk. Where there are differences, they are more at the device/process level, and do not pose any particular challenges to the designer at this point. This includes SPICE models, antenna effect, ESD protection, I/O and analog, and back-gate bias.

Synopsys Cadence Magma
Synthesis Design Compiler RTL Compiler Talus Design
Place & route IC Compiler SoCE Nanoroute Talus
Timing analysis PrimeTime (NLDM, CCS) ETS (NLDM, ECSM) Talus (NLDM, CCS)
Power analysis PTPX, PrimeRail (NLDM, CCS) EPS, VoltageStorm Talus
Signal integrity PTSI CeltIC Talus
DFT Tetramax
Verification Formality Conformal

ARM uses standard packages from the leading EDA vendors in SOI ASIC design

20nm FD-SOI v. 28nm Bulk

To get some clear figures on power and performance, ARM recently ported a Cortex-M0 from 28nm bulk to 20nm FD-SOI.  We used the Cortex M0 implementation flow that was proven in 22nm SOI. This included:

  • synthesis, place and route, and the same reduced set of standard cells for 20nm FDSOI and 28nm bulk
  • parasitics extraction for interconnects from the routed 22nm SOI M0 core (22nm SOI Back-End Of Line (BEOL) is considered to be the most representative of current bulk/FD-SOI 20nm BEOL)
  • characterization of 20nm FDSOI and 28nm bulk standard cells (typical process corner and room temperature)
  • different voltages to create the corresponding .lib files that would be used for timing and power analysis of the M0 core: 0.7, 0.8, 0.9 and 1V
  • timings and power were compared for the routed M0 core based on 20nm FD-SOI and 28nm bulk characterizations (.lib).
ARM, 2011 IEEE SOI Conference

Source: ARM, 2011 IEEE SOI Conference

In any next-node port, you typically expect to get a 25% improvement in performance, but in porting from 28nm bulk to 20nm FD-SOI, FD-SOI boosted the improvement far beyond the expected 25%. At a Vdd (supply voltage) of 1.0V, we saw a 40% improvement in performance. At 0.9V, we saw 66%. For Vdd of 0.8, we saw an 80% improvement. And for Vdd of 0.7, we saw an improvement of 125%.

Power is consistently reduced by 30%, and leakage holds steady.

Remember, this is a straight port, which gives us a baseline figure. There are several powerful process and design optimization techniques that can boost those numbers even higher without significantly increasing the complication factor.

Existing design, tremendous results

The conclusions we have drawn are that:

  • a standard bulk ASIC design flow can be used for FDSOI – don’t expect any change
  • an existing bulk logic design can be directly ported to FDSOI
  • you just need to check the timing closure – there is no timing variability (this is not PD-SOI)

FD-SOI should give tremendous advantages in terms of both power and performance. These low-voltage, high-performance chips are perfect for low-power applications, with the undoped channel in the low voltage SRAM resulting in higher margins. For some applications, RF features will also be improved if designers choose high-resistivity substrates.

FD-SOI is all a designer needs for high-performing, low-power mobile applications. And happily from the designer’s point of view, FD-SOI is as simple as designing in bulk.

———-

This article was adapted from “FDSOI Design Portability from BULK at 20nm Node”, which was presented at the 2011 IEEE SOI Conference.

CEA-Leti and EDA specialist InfiniScale are collaborating on process-variability management in SOI sub-28nm devices

CEA-Leti and EDA specialist InfiniScale are collaborating on process-variability management in SOI sub-28nm devices.  The goals are to offer the design community access to Leti’s FD SOI technology,  and to validate InfiniScale tools with measurements on silicon.