Tag Archive edge computing

ByAdele Hars

SOI Consortium at Key China Events in May: World Semiconductor Congress (Nanjing) and SOI Academy/FD-SOI Training (Shanghai)

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)

QR code for WCS, Nanjing ’19

At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.

Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.

QR code for SOI Academy and FD-SOI Training, Shanghaid 2019

The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.

We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.

ByAdele Hars

SOI Consortium & Members at Samsung Foundry Forum (14 May, Santa Clara, CA)

For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you’ll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem.

There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners.

SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.

Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.

ByAdele Hars

Part 2: Silicon Valley SOI Symposium Takeaways. FD-SOI, Smarter Edge, Goldilocks & More.

Key takeaway #2: If you need a Goldilocks process node – where you’ll get just the right balance between active power, unit cost and investment – look to FD-SOI. And, btw, the IP landscape has improved dramatically. Those were just some of the great points made by Huibert Verhoeven (shown above), GM/SVP of Synaptics’ IoT Division in his talk at the recent SOI Symposium in Silicon Valley.

BTW, if you missed part 1 of our coverage —Silicon Valley SOI Symposium a Huge Success. Key Takeaways (Part 1) Here. – you’ll want to be sure to read it, too. Almost all of the presentations are now posted on our website – click here to access them.

In this post here, we’ll cover presentations by Synaptics, GlobalFoundries, STMicroelectronics, Anokiwave and Dolphin Integration. It was a really full, day, so be sure to stay turned for Part 3 of our coverage to follow shortly: it will highlight the remaining presentations and panel discussions.

Synaptics: Smart Home at the Edge

Synaptics’ Verhoeven’s presentation Revolutionizing User Experience Through Secure Neural Network Acceleration at the Edge was about Smart Home and using SOI. Synaptics is a human interface (HMI) company that’s been doing neural networks since 1986. They’ve always been on the leading edge, from their first shipment of PC touchpads to becoming a dominant force in all things HMI today: they now ship over a billion units annually.

Synaptics slides 15 & 16 from the SOI Symposium, Silicon Valley 2019.

They currently have SOI products shipping with dedicated neural networks for voice, he said. European [privacy] regulations have played a part in driving their use of SOI, as have challenges regarding power and heat. Things are getting smarter at the edge. For example, not only do users want their coffee machine to offer the usual morning espresso, Synaptics says that the next step is for your coffee machine to recognize you’re looking extra tired and ask if you might want a double?!

For them Smart Home and multi-modal applications are the primary area of interest, as well as some automotive. Although their biggest customers have resources, others need guidance. Voice is a critical component, but now you also need video and display.

Why SOI? Their HMI vision requires low power, significant computation and dedicated neural network hardware, explained Verhoeven, so FD-SOI with RF meets their needs. “22nm SOI is a Goldilocks IoT Process Node,” he proclaimed. It gets the combination of active power, unit cost and investment just right. What’s more, he said, “The IP landscape has improved dramatically. Our choice of SOI was not an accident.” Be on the lookout for more products leveraging FD-SOI over the next six months, he concluded.

At this point on SOI, they’ve got 1 TOPS products with dedicated NPU for speakers, soundbars, Wi-Fi mesh, appliances, STBs and smart displays. These products have voice and sensor real-time (RT) AI. Next up is >4 TOPS on SOI with dedicated NPU, targeting STBs and smart displays with voice, video, imaging and RT AI.

GF: World-Changing Opps

GlobalFoundries slides 6 & 7 from the SOI Symposium 2019, Silicon Valley.

“Our clients are at the forefront of changing the world,” declared Mark Granger, VP of the Automotive Product Line at GlobalFoundries. His presentation, Capturing High Growth Market Opportunities with SOI, detailed how mobility, automotive and IoT are the growth markets for SOI. So not unsurprisingly, GF’s 22nm FD-SOI technology, 22FDX, is seeing particular traction in mobile, edge, wearables and automotive.

They’ve got twice as many tape-outs this year as they did a year ago, he noted. GF’s SOI portfolio includes 22FDX®, 45RFSOI and 8SW/7SW RF SOI for 5G/mobility; 22FDX for automotive (fully qualified for automotive Grade 2, with Grade 1 on the way); and 22FDX, 130RFSOI and 8SW/7SW RF SOI for IoT.

GF has announced a stream of good news recently:

  • with Dolphin Integration they’re delivering differentiated FD-SOI Adaptive Body Bias Solutions for 5G, IoT and automotive applications;
  • they’ve crossed the billion-dollar design win threshold with 8SW RF SOI technology;
  • they’ve collaborated with Synopsys to develop the industry’s first Automotive Grade 1 IP for their 22FDX process;
  • and they worked with Rambus on the delivery of High-Speed SerDes on 22FDX® for communications and 5G applications.

You might have heard about the Dolphin Integration news, as we covered it recently here at ASN (if not, be sure to read it here). Dolphin’s IP and methodology solutions address energy efficiency challenges. Automated transistor body biasing adjustment can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs. At the Silicon Valley event, Dolphin Integration CEO Philippe Berger provided additional information in his talk, FD-SOI IP Platform for Energy-Efficient IoT SoC.

Dolphin Integration slides 5 & 6 from the SOI Symposium 2019, Silicon Valley.

In another GF-related talk, Nitin Jain, the CTO of longtime GF RF-SOI customer Anokiwave presented Unleashing the mmWave Phase Array Using SOI for 5G & Satcom. Anokiwave is a fabless semi IC company (you’ll find a good technical discussion of mmWave phase array written by their Chief Architect here). They do active antennas (aka phased array), something the military’s done for a long time, but now Anokiwave is bringing it to new markets and applications including radar, satcom and 5G. What they’ve been able to do is planarize the active antennas. They use GF’s 45RFSOI process technology for phased array systems because of the cost, performance, scalability and system enhancements it enables. 45RFSOI, he explained, is ideal for beam-forming FEMs (including the switches, LNAs and PAs). The move to 5G/mmWave is going to require a lot of antennas, so these Anokiwave ICs are headed to high volumes, concluded Jain.

Stellar by ST

As Roger Forchhammer, Director of Business Development at STMicroelectronics pointed out in his presentation, Automotive FD-SOI Microcontrollers with Embedded PCM, ST pioneered FD-SOI (and that was almost a decade ago, btw). Then in February 2019, they announced a world first: they’d begun sampling 28nm FD-SOI microcontrollers (MCUs) with embedded non-volatile memory (eNVM) based on embedded Phase-Change Memory (ePCM) to 10 alpha customers. These MCUs target powertrain systems, advanced and secure gateways, safety/ADAS applications, and vehicle electrification.

STMicroelectronics slides 9 & 10 from the SOI Symposium 2019, Silicon Valley.

(In case you want technical details, the breakthrough ePCM eNVM was first presented at IEDM in December 2018 – you can get the presentation that accompanied the paper, Truly Innovative 28nm FDSOI Technology for Automotive Microcontroller Applications embedding 16MB Phase Change Memory, from the ST website.)

In his Silicon Valley presentation, Forchhammer said they’re now doing Stellar, a whole family of automotive products on FD-SOI. To do it, they’d taken an existing device and moved it to 28nm FD-SOI with ePCM, which they manufacture at their fab in Crolles, France. A major advantage for automotive he cites is that in software updates it’s bit-level programmable. “ST is fully behind FD-SOI,” he concluded, adding that we’re see more automotive as well as IoT products coming soon.

Well folks, that’s all for this post. We’ll finish up our coverage of the SOI Consortium’s 2019 Silicon Valley Symposium in the next ASN post (there was so much to cover!). So please stay tuned.

ByAdele Hars

FD-SOI for Near-Threshold-Voltage Design? It’s a Good Knob, Say #55DAC Expert Panelists

That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a  #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point.

Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings.

The original goal of the panel was “…to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet ‘always-on’ market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.”

(Update 2 August 2018:  a complete video of this panel is now available on YouTube — click here to view it.)

#55 DAC Expert Panel: How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? Left to right: Brian Fuller, Arm (moderator); Scott Hanson, Ambiq Micro; Lauri Koskinen, Minima Processor; Mahbub Rashed, GlobalFoundries; Paul Wells, sureCore. (Organized by Jan Willis of Calibre Consulting)

The panelists included:

  • Scott Hanson – Ambiq Micro
  • Mahbub Rashed – GLOBALFOUNDRIES
  • Lauri Koskinen – Minima Processor
  • Paul Wells – sureCore Ltd., Sheffield

Brian Fuller of Arm served as moderator.

Panel organizer Jan Willis, Calibre Consulting

Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on!

#55DAC Expert Panel on Near-Threshold Voltage Sees Growing Opportunity Despite Challenges

First published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships & Marketing Executive

Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25.

Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what’s not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It’s required innovating throughout the design process including test where Scott said they had create their own “secret sauce” to make it work. Later on in the panel, Scott described designers in near-threshold as “picojoule fanatics” to overcome the limitations in design tools which are geared towards achieving performance goals.

Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design.

Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield.

Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor’s note: sureCore‘s CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.]

Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it’s gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there’s been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future.

~ ~ ~

This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original.

* As explained by Rich Collins of Synopsys in the TechDesign Forum: “Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. […] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on.  Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. […] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.

ByAdele Hars

Cool New FD-SOI Products Rolling Out – Highlights from the Silicon Valley SOI Symposium (Part 1)

“The ecosystem is ready. The focus is now on applications and products.” And with those words, SOI Consortium Executive Director Carlos Mazure opened the annual Silicon Valley SOI Symposium. As promised, the day was packed with presentations about products on FD-SOI – some from big players like NXP and Sony, some from names new to the FD-SOI ecosystem like Audi and Airbus, and some from start-ups just getting into the game.

The event got excellent coverage in EETimes/EDN – including in their editions across the globe in China, Japan, Taiwan, India and more. Samsung, GF Ramp FD-SOI, heralded the headlines.

It was a full day of excellent presentations. In this post, I’ll chronicle the morning presentations.  The next post(s) will cover the afternoon session.  Note that as of this writing, the ppts are not yet posted on the SOI Consortium website, but many will be. Keep checking back under the Events tab, and look under “past Events”.

Andes Technology

As semiwiki noted a few years back, Andes Technology is “…the biggest microprocessor IP company you’ve never heard of.” Based in Taiwan, Mediatek is one of their big customers; they’ve got a strong client base across Asia/Pacific, and are now making inroads into North America. Last year they announced with GF their 32-bit CPU IP cores had been implemented on GF’s 22FDX® FD-SOI technology.

In his symposium keynote, CEO Frankwell Lin said that in the test chip they’re doing with GF and Invecus, they’re seeing a 70% power savings compared with what they’d gotten in 28ULP. Their newest products are the N25 32bit and NX25 64bit RISC-V based cores, and in July they’ll announce a core that runs on Linux.

NXP

“With FD-SOI we’re enabling the future of embedded processing,” the always-quotable (and keynote speaker) NXP VP/GM Ron Martino told us. NXP’s i.MX7ULP, i.MX8, i.MX8X and i.MXRT are all FD-SOI based. They all share fundamental building blocks, so NXP can build platforms, scale and re-use IP. “It’s better than any technology I’ve worked on in my 30 years in the industry,” he said.

They’re seeing much higher performance with on-chip flash. And the RT “crossover” processor boasts 3x higher computing performance than today’s competing MCUs. This is going to be critical for edge computing going forward, to which end NXP is working very closely with foundry partner Samsung.

FD-SOI is not just helpful for the logic part of these chips – memory technologies also share in the benefits. They get much higher performance with on-chip flash. Leakage is cut by a factor of ten with biasing techniques, and the enhancements mean that memory can operate at very low voltages.

NXP is increasingly sophisticated with how they use body biasing, applying high-granularity techniques to independent domains in different parts of the chips. Getting sub-0.6 Vmin delivers value at multiple levels: on battery life, on total system cost, and on system enablement. Invest in body biasing if you want to get leadership results, advised Martino.

Edge computing – including machine learning and neural networks for things like image classification – is a big target, he continued. At the last CES they did a proof-of-concept “foodnet” where two appliances talked to each other without having to go to the cloud. In that case it was an i.MX8 in a fridge and an i.MXRT in a microwave, but he explained that the same concept can be applied to a car for driver awareness, where you don’t want to take the extra time for or don’t have a connection to the cloud.

iMX and FD-SOI enable scalable solutions, he concluded.

Audi

What’s a metal-bending company doing talking about electrons? asked Audi Project Manager Dr. Andre Blum. And why SOI? Well, for Audi, he said, SOI stands for Solutions, Opportunities and Innovation.

Audi Project Manager Andre Blum says SOI stands for Solutions, Opportunities and Innovation — at the 2018 SOI Symposium in Silicon Valley.

Audi is working on the various levels of autonomous driving, and they want it to be without design limitations. That means being able to hide sensors wherever they’re needed. They’ll create a cocoon around the car for the best driver experience. He showed a fun video Audi’s made to illustrate their concept – it’s the Invisible Man video, which you can check out on YouTube.

But those new architectures can’t up the power budget (think heat): rather they need to cut power drastically while increasing performance. And with FD-SOI, they see an opportunity to do just that, he said, while integrating the sensors.

Audi is one of 25 partners in a heavily funded (>100 million Euros) brand new EU Horizon 2020 program called Ocean12 (lead by Soitec). The launch was only May 1st 2018 (so as of today it doesn’t even have a website yet), and it will run for about 4 years. It is described by ECSEL (a public-private entity that puts together the big EU research projects) as an “opportunity to carry European autonomous driving further with FDSOI technology up to 12nm node”. One to watch!

Airbus

For Airbus, it’s all about increased connectivity and communications that are trusted and secure, said company expert Olivier Notebaert. Since their chip runs are low, NRE – non-recurring engineering costs – are very important; and they need flexible systems.

SOI has a long history in aerospace – in fact that’s originally where it got its start, since it can handle radiation and is immune to latch-up. Notebaert says that even for Airbus, IoT is their future. The developments they pioneer will be part of it.

Airbus is a partner in the EU Horizon 2020 DAHLIA project – which stands for Deep sub-micron microprocessor for spAce rad-Hard appLIcation Asic. The project is, “…developing a Very High Performance microprocessor System on Chip (SoC) based on STMicroelectonics European 28nm FDSOI technology with multi-core ARM processors for real-time applications, eFPGA for flexibility and key European IPs, enabling faster and cost-efficient development of products for multiple space application domains. The performance is expected to be 20 to 40 times the performance of the existing SoC for space.”

According to another recent presentation, DAHLIA is prototyping an FPGA this year that will be in production in 2019.

Sony

For Sony GM Kenichi Nakano, FD-SOI has big potential for low-power products. And he should know. Sony has been an FD-SOI pioneer, using it as the basis for GPS chips that are now in a growing number of cool products, especially watches. They’re getting good feedback from the market and see good opportunities across a diversified global customer base, he said. Their CXD5603, for example, is the lowest power GNSS (GPS) chip worldwide. In mass production since 2015, it is now dominating world wearable markets like trackers — such the popular Amazfit line.

Running through their various FD-SOI based GPS offerings, he noted that the GPS is a pretty simple chip. But now customers are asking for more, like for it to work in the water (where a GPS typically doesn’t). So Sony has partnered with triathalon teams and are seeing good results.

With success, of course, comes greater demands: for greater accuracy, for more precise positioning in motion, for increased height accuracy, for even lower power – and Sony is meeting these demands with FD-SOI, in solutions like the new CXD5602. The CXD5602 product configuration covers audio/video/communications: key factors in IoT.  A camera version is releasing this summer, as are main and extension boards. An LTE module will be released at the end of 2018.

And now they’re using those FD-SOI chips in audio applications. You’ll find it in the Xperia™ Ear Duo, he said. The MWC press release noted that Xperia Ear Duo “… is driven by Sony’s ultra-low power consuming “CXD5602” chip and a sophisticated multi-sensor platform, the “Daily Assist” feature will recognize time, location and activities to offer relevant information throughout the day – reminding you what time your next meeting is when you reach the office or narrating the latest news headlines.”

Also in that PR, Hiroshi Ito,Deputy Head of Smart Product Business Group at Sony Mobile Communications, said, “Ear Duo is the first wireless headset to deliver a breakthrough Dual Listening experience – the ability to hear music and notifications simultaneously with sounds from the world around you.” The highly anticipated wireless “open-ear” stereo headset started rolling out to select markets in Spring 2018. There’s a great info page with video here.

So that’s what we heard in the morning. My next post (or posts?) will cover the afternoon. That includes Dan Hutcheson’s excellent talk updating his FD-SOI survey, presentations from Samsung, Globalfoundries and Simgui, plus some from very cool start-ups, and the final panel presentation.