The new IEEE S3S conference promised rich content, as it merged both The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
The result was an excellent conference, with outstanding presentations from key players in each of the three topics covered. This quality was reflected in the increased attendance: almost 50% more than at the SOI conference last year.
The new triptych at the heart of the conference was well illustrated by the plenary session, which combined a presentation on ST’s FD-SOI technology by Laurent LePailleur (STMicroelectronics), one on Low Power Design, by Bob Bordersen (UC Berkeley), and one on monolithic integration by Zvi Or-Bach (MonolithIC 3D™).
Professor Bordersen’s presentation dealt with power efficiency, explaining how developing dedicated units with a high level of parallelism and a low frequency can boost the number of operations performed for 1nJ of expanded power. He illustrated his point by showing how an 802.11a Dedicated Design for Computational Photography can reach 50,000 OP/nJ while an advanced quadcore microprocessor will not even reach 1 OP/nJ. Such is the price of flexibility….but the speaker claims this can be overcome by using reconfigurable interconnects.
The “Best SOI Paper” award went to a GlobalFoundries/IBM paper entitled “FinWidth Scaling for Improved Short Channel Control and Performance in Aggressively Scaled Channel Length SOI FinFETs.” The presenter, Abhijeet Paul (GF) explained how narrower Fins can be used to improve short channel effects while actually giving more effective current without degrading the on-resistance. (See the DIBL and SS improvement on the chart.)
The”Best SOI Student Paper” award went to H. Niebojewski for a detailed theoretical investigation of the technical requirements enabling introduction of self-aligned contacts at the 10nm node without additional circuit delay. This work by ST, CEA-Leti and IEMN was presented during the extensive session on planar FD-SOI that started with Laurent Grenouillet’s (CEA-Leti) invited talk. Laurent first updated us on 14nm FD-SOI performance: Impressive static performance has been reported at 0.9V as well as ROs running at 11.5ps/stage at the very low IOFF=5nA/µm (0.9V & FO3). Then he presented potential boosters to reach the 10nm node targets (+20% speed or -25% power @ same speed). Those boosters include BOX thinning, possibly combined with dual STI integration, to improve electrostatics and take full advantage of back-biasing as well as strain introduction in the N channel (in-plane stressors or sSOI) combined with P-channel germanidation.
sSOI (strained SOI) was also the topic of Ali Khakifirooz’ (IBM) late news paper, who showed how this material enables more than 20% drive current enhancement in FinFETs scaled at a gate pitch of 64nm (at this pitch, conventional stressors usually become mostly inefficient).
An impressive hot topics session was dedicated to RF CMOS.
J. Young (Skyworks) explained the power management challenges as data rates increase (5x/3 years). Peak power to average power ratio has moved from 2:1 to 7:1 while going from 3G to LTE. Advanced power management techniques such as Envelope Tracking can be used to boost your system’s efficiency from 31% to 41% when transferring data (compared to Average Power Tracking techniques), thus saving battery life.
Paul Hurwitz (TowerJazz) showed how SOI has become the dominant RF switch technology, and is still on the rise, with predictions of close to 70% of market share in 2014.
The conference also had a strong educational track this year, with 2 short courses (SOI and 3DI) and 2 fundamentals classes (SOI and Sub-Vt).
The SOI short course was actually not SOI-restricted, since it was addressing the challenges of designing for a new device technology. P. Flatresse (ST) and T. Bednar (IBM) covered the SOI technology parts (FD-SOI and SOI FinFETs for ASICs respectively), while D. Somasekhar (Intel) gave concrete examples of how the change of N/P performance balance, the improvement of gate control or the introduction of Mandrels has affected design. Other aspects were also covered: Design for Manufacturing (PDF), IP librairies (ARM) and design tools (Cadence) for the 14nm node, to make this short course very comprehensive.
The rump session hosted a friendly discussion about expectations for the 7nm node. It was argued that future scaling could come from 3DI, either through the use of monolithic 3D integration or stacking and TSVs because traditional scaling is facing too many challenges. Of course, 3DI may not yet be economically viable for most applications, and since it is compatible with traditional scaling, we might well see both developed in parallel.
3D integration was also the topic of another joint hot topics session covering various fields of investigation, like co-integration of InGaAs and Ge devices (AIST), or 3D cache architectures (CEA-Leti & List). A nice example was given by P. Batra (IBM) of two stacked eDRAM cache cores, where the 16Mb cache on one layer is controlled by the BIST on the other layer and vice-versa with the same efficiency as in the 2D operation.
The first edition of this new conference was very successful, with a good attendance, two sessions running in parallel, extensive educational tracks, a large poster session and a lot of very high quality content. The two hot topics sessions generated a lot of enthusiasm in the audience.
Similar sessions will be repeated at the conference’s next edition, in the San Francisco area. It promises to offer outstanding content once more, and we already urge you to plan to submit papers and attend it.
Last May, we already let you know about the IEEE S3S conference, founded upon the co-location of The IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference, completed by an additional track on 3D Integration.
Today, we would like let you know that the advance program is available, and to attract your attention on the incredibly rich content proposed within and around this conference.
The conference revolves around an appropriate mix of high level contributed talks from leading industries and research groups, and invited talks from world-renowned experts.
The complete list of posters and presentations can be seen in the technical program.
This year some additional features have been added, including a joint session about RF CMOS as well as one about 3D integration. Check the list of participants on those links, and you will see that major players in the field are joining us!
Our usual rump session will let us debate what the 7 nm node and beyond will look like, based on the vision presented by our high profile panelists.
There will be 2 short courses this year, and 2 fundamentals classes. Those educational tracks are available to you even if you do not register for the full conference.
On Monday October 7th, you can attend the short course on “14nm Node Design and Methodology for Migration to a New Transistor Technology“, that covers specificities of 14nm design stemming from the migration of classical bulk to bulk to FinFET/FDSOI technologies..
Alternatively, on the same day you can attend the “3D IC Technology” short course, introducing the fundamentals of 3D integrated circuit technology, system design for 3D, and stress effects due to the Through Silicon Via (TSV).
On the afternoon of Wednesday October 9th, you can opt to follow the Sub Vt Fundamentals Class on “Robust subthreshold ultra-low-voltage design of digital and analog/RF circuits” or the SOI Fundamentals Class “Beyond SOI CMOS: Devices, Circuits, and Materials “.
You could also prefer to take the opportunity to visit the Monterey area.
The conference has always encouraged friendly interactions between the participants, and because it covers the complete chain, from materials to circuits, you are sure to meet someone from a field of interest. The usual social events, welcome reception, banquet and cookout dinner, will provide you with more openings for networking, contemplating new project opportunities or getting into technical discussions that could shed new light on your research.
To take full advantage of this outstanding event, register now!
Please visit our Hotel Registration Information page to benefit from our special discounted room rates at the conference venue, The Hyatt Regency Monterey Hotel and Spa.
The latest conference updates are available on the S3S website (http://S3Sconference.org).
PCMag’s Michael Miller called IBM’s 22nm SOI Power8 “the most fascinating” of the high-end processors. Reporting on this year’s Hot Chips conference, presented there. He noted that the chip “will have 12 cores, each capable of running up to eight threads, with 512KB of SRAM Level 2 cache per core (6MB total L2) and 96MB of shared embedded DRAM as a Level 3 cache.” He cites the eDRAM, which ASN readers first learned about in an ’06 article by Subi Iyer, the IBM father of eDRAM – when he explained, “The complexity adder is about half in SOI compared to bulk for deep trench based eDRAMs.”
Miller also says, “Compared with the previous generation Power 7+, which was manufactured on a 32nm SOI process, Power8 should have more than twice the memory bandwidth at 230GBps. IBM says each core should have 1.6 times the performance of Power7 on single-threaded applications and twice the SMT (symmetric multi-threaded) performance.”
IBM will produce Micron‘s Hybrid Memory Cube (HMC) in the debut of the first commercial, 3D chip-making. HMC parts will be manufactured at IBM’s advanced semiconductor fab in East Fishkill, N.Y., using the company’s 32nm SOI HKMG process technology.
The IEEE is once again giving two of its most prestigious awards to some of the SOI and advanced substrate industry’s leading figures.
There are few greater honors in engineering than the IEEE Technical Field Awards (TFAs). And once again, people who work in advanced substrates are among the recipients of two major awards: the Andrew S. Grove award and the Daniel E. Noble Award for Emerging Technologies.
The TFAs are awarded for contributions or leadership in specific fields of interest of the IEEE. The awards consist of a bronze medal, certificate, and honorarium. They are typically announced each summer, but the actual ceremonies take place over a year later, giving the recipients time to arrange their schedules to be there.
This explains why in the summer of 2011, the 2012 award winners were announced, while the ceremonies for the 2011 winners announced in the summer of 2010 are just being held now.
The IEEE Andrew S. Grove Award honors its namesake’s lifetime achievements. It is sponsored by the IEEE Electron Devices Society, and presented to an individual for outstanding contributions to solid-state devices and technology.
As announced last year, the co-recipients of the 2011 IEEE Andrew S. Grove Award are Judy Hoyt and Eugene Fitzgerald. Professor Hoyt is with the MIT Department of Materials Science. Eugene Fitzgerald is the Merton C. Flemings-SMA Professor of Materials Science and Engineering and head of The Fitzgerald Group at MIT.
Hoyt and Fitzgerald are cited for “seminal contributions to the demonstration of Si/Ge lattice mismatch strain engineering for enhanced carrier transport properties in MOSFET devices.” Their work on “strained” silicon and its application to SOI wafers is well-known in the advanced substrates community. (Professor Fitzgerald wrote about this work in ASN5, Summer 2006.)
The 2011 Grove Award will be presented at the 2011 IEEE International Electron Devices Meeting (IEDM), which takes place in December 2011 in Washington D.C., USA.
The IEEE has also announced that 2012 Grove award will feature another SOI luminary: Jean-Pierre Colinge, Head of the Microelectronics Centre, Tyndall National Institute, Cork, Ireland. The award recognizes Dr. Colinge “For contributions to silicon-on-insulator devices and technology.” He is heralded in the industry for his seminal and continued work in multigate FETS. This paved the way for FinFET and TriGate architectures. The actual ceremony will take place at the end of 2012. Dr. Colinge and his work have been featured in many editions of ASN.
Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).
The IEEE Daniel E. Noble Award for Emerging Technologies honors Dr. Daniel E. Noble, Executive Vice Chairman of the Board emeritus of Motorola. It is given for outstanding contributions to emerging technologies recognized within recent years.
The 2011 Noble Award was given to Mark L. Burgener and Ronald E. Reedy for “basic research and development of silicon on sapphire technology culminating in high-yield, commercially viable integrated circuits”. Dr. Burgener is vice president of advanced research and Dr. Reedy is the chief operating officer at Peregrine Semiconductor Corporation, San Diego, California.
In particular, the award recognizes their persistence and contributions in making silicon-on-sapphire (SOS) commercially viable for producing integrated circuits with improved speed, lower power consumption and more isolation compared to bulk silicon circuits.
The ceremony for the 2011 Noble Award took place during the IEEE/MTT-S International Microwave Symposium (MTT 2011) in June 2011 in Baltimore, MD, USA.
This summer, the IEEE also announced the winner of the 2012 Noble award: Subramanian S. Iyer, for “the development and implementation of embedded DRAM technologies.” Dr. Iyer is Distinguished Engineer & Chief Technologist, Semiconductor Research & Development Center, IBM Systems & Technology Group. He wrote about therole of SOI in “eDRAM” technology in ASN6 (December 2006). The technology is now at the heart of IBM’s latest offerings.