Tag Archive ESD

ByGianni PRATA

Bulk to SOI Porting Analysis

One of the key projects currently underway within the SOI Consortium is to understand and provide guidance on the advantages and obstacles of porting SoC designs from Bulk to FD-SOI. This project represents a strategic opportunity to help drive the profile of FD SOI and participate in the emergence of this important technology.

Objective: Analyze details of a design migration from 20LPM to 20ET

Current participants: IBM, Qualcomm (limited), Soitec, ARM, GlobalFoundries

Deliverables: Provide a comprehensive and credible answer to the question, “What will it take to port a SoC design from Bulk to FD-SOI CMOS in the most straight-forward way?” The output will be a short manual or white paper describing the design porting steps.

Key Focus areas:

  • ESD
  • Back-bias implementation, which includes substrate ties and bitcells stability
  • Analog implementation
  • Reliability, which includes soft error rate.

Timescale (tentative): Final release is currently slated to be ready in time for the DAC conference (June 5th).


ESD Protection for Advanced SOI

Deeply scaled PD- and FD-SOI require new approaches to ESD protection.  Recent work from Stanford and GlobalFoundries on gate controlled FEDs shows great promise.

Technology scaling unfavorably affects the electrostatic discharge (ESD) protection of integrated circuits mainly by reducing MOSFET oxide and junction breakdown voltage, diode current shunting capability, and by increasing the interconnect resistivity. The I/O data-rate increasingly limits the capacitive budget, exacerbating the shrinkage of ESD design space.

It is important to find ESD solutions that minimize parasitic loading while achieving superior robustness.

Silicon-on-insulator (SOI) technology presents some distinctive challenges to ESD design. The buried oxide (BOX) layer makes vertical and deep body ESD structures infeasible. The lateral SOI diode based (“rail-based”) protection approach is becoming less effective in the high-current Charged Device Model (CDM) domain, owing to excessive voltage build-up along the ESD path involving power buses, power-clamps (Pclamp), and diodes.

Figure 1: Pad-based local clamping scheme. Red arrows represent the pad-to-Vss ESD current path, which does not include the upper diode or the power buses (crossed-out). The double-triangle symbol represents a local clamping device, such as the double well field effect diode (DWFED).

The pad-based “local clamping” scheme (Figure 1) is a promising option. By connecting an ESD device directly between the pad and Vss, it allows the ESD current to flow from the pad to ground without going through the resistive path (shown as crossed out in Figure 1) and the Pclamp. This way, the pad voltage is considerably reduced, immediately expanding the design space.

New devices

For local clamping ESD devices, it is vital to engineer their turn-on voltage in order to avoid accidental turn-on during normal operation and to minimize leakage current. Low capacitance and resistance are also required. Furthermore, an important CDM specific requirement is that the device should turn on faster than the CDM event to start shunting current before charge accumulation raises the pad voltage.

To meet these requirements, devices such as the double well field effect diode (DWFED) and FED have been developed. Figure 2 shows the example structure of DWFED and the triggering mechanism. During normal operations, the inverter pulls the DWFED’s gate voltage to low, helping to preserve the DWFED’s intrinsic PNPN state.

Figure 2: (a): The DWFED structure. (b): Behavior during normal operations. Device in “PNPN” mode, minimizing the leakage current. (c): Triggering behavior during ESD. Device in “PN” mode, shunting large ESD current.

This is similar to a silicon-controlled rectifier’s (SCR) OFF mode. In an ESD event, the Vdd is pulled low by the de-coupling capacitance and the power clamp between Vdd and ground, turning on the PMOS in the inverter. The DWFED gate is now pulled high, creating an inversion layer in the P-well (for positive ESD at the pad). This inversion layer connects the NW and N+ regions, collapsing the junctions in between. The device converts to a P-N diode ON mode between P+ and NW.

Deeply Scaled PD, FD-SOI and FinFETs

In our recent work, various types of field effect devices have been experimentally shown in PD-SOI to be suitable for local clamping. Both FED and DWFED exhibit capacitance below 0.35 fF/μm, which is a significant improvement over the SCR. Their turn-on speed under CDM is controlled to below 0.5 ns.

The device design has been guided by Technology CAD (TCAD) modeling. Design tradeoffs are evaluated with different well dopings to highlight the important parameters. The field effect devices are likely to be advantageous in ESD applications in ultra thin body SOI (also known as planar FD-SOI) and FinFET due to their reduced sensitivity to the scaling of silicon film dimensions.



S. Cao, A. A. Salman, J.-H. Chun, S. G. Beebe, M. M. Pelella and R. W. Dutton, “Design and Characterization of ESD Protection Devices for High Speed I/O in Advanced SOI Technology,” IEEE Transactions on Electron Devices (TED), vol. 57, no. 3, pp. 644-653, March 2010.

S. Cao, J.-H. Chun, S. G. Beebe and R. W. Dutton, “ESD Design Strategies for High-speed Digital and RF Circuits in Deeply-scaled Silicon Technologies,” IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 57, no. 9, pp. 2301-2311, Sept. 2010.

A. Salman, S. Beebe, M. Pelella, and G. Gilfeather, “SOI lateral diode optimization for ESD protection in 130 nm and 90 nm technologies,” in Proceedings of International EOS/ESD Symposium, 2005, pp. 421–427.

S. Cao, J.-H. Chun, A. A. Salman, S. G. Beebe, and R. W. Dutton, “Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology,” Microelectronics Reliability, vol. 51, no. 4, pp. 756-764, April 2011.

ByGianni PRATA

SOI at IEDM 2010

The 2010 IEEE International Electron Devices Meeting (IEDM) was held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies.

Here are summaries of key papers referencing work on SOI or other advanced substrates.

(Note: at the time of this posting, the papers are not yet available from the  IEEE Xplore website.  However, many are available from the Advanced Silicon Device and Process Lab at the National Taiwan University.)

Paper #1.2: Energy Efficiency Enabled by Power Electronics
Arunjai Mittal (Infineon)

In particular, see section 4, where the author addresses the huge energy savings that can be realized using variable speed motors. Infineon’s driver ICs (which take a logic signal output from a microcontroller chip in the control system, and provide the appropriate current and voltage to turn power devices on and off) are built on SOI. (See Infineon’s article in ASN7. Infineon and LS Industrial Systems started a JV in 2009 called the LS Power Semitech Co., which leverages this technology.)

#2.6: Engineered Substrates and 3D Integration Technology Based on Direct Bonding for Future More Moore and More than Moore Integrated Devices (Invited)

L. Clavelier, C. Deguet, L. Di Cioccio, E. Augendre, A. Brugere, P. Gueguen, Y Le Tiec, H. Moriceau, M. Rabarot, T. Signamarcheix, J. Widiez, O. Faynot, F. Andrieu, O. Weber, C. Le Royer, P. Batude, L. Hutin, J.F. Damlencourt, S. Deleonibus, E. Defaÿ, (CEA/LETI Minatec)

This paper deals with new generations of substrates and 3D integration techniques, based on direct bonding techniques, enabling future devices in the More Moore and in the More than Moore areas.

#3.2 : Planar Fully Depleted SOI Technology: A Powerful Architecture for the 20nm Node and Beyond (Invited)

O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brévard, C. Tabone, P. Gaud, S. Barraud, T. Ernst and S. Deleonibus (CEA/LETI Minatec)

The authors of this paper say that for 20nm node and below, they have proven that planar undoped channel Fully Depleted SOI devices are easier to integrate than bulk, non planar devices like FinFET. The paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed.

#3.3:  Anomalous Electron Mobility in Extremely-Thin SOI (ETSOI) Diffusion Layers with SOI Thickness of Less Than 10 nm and High Doping Concentration of Greater Than 1x1018cm-3

N. Kadotani,T. Takahashi, K. Chen,T. Kodera, S. Oda, K. Uchida*  (Tokyo Institute of Technology, *also with PRESTO)

This paper is the first to report carrier transport in heavily doped ETSOI diffusion layers. The authors found that electron mobility in the heavily doped ETSOI diffusion layer is totally different from electron mobility in heavily doped bulk Si. In other words, electron mobility is enhanced in thinner ETSOI diffusion layers (Tsoi>5nm), whereas electron mobility is degraded as dopant concentration increases when Tsoi is 2nm. The authors conclude that this information will be indispensable for the design of aggressively scaled ETSOI devices as well as 3D FETs.

#3.4:  Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX

O. Weber, F. Andrieu, J. Mazurier, M. Cassé, X. Garros, C. Leroux, F. Martin, P. Perreau, C. Fenouillet-Béranger, S. Barnola, R. Gassilloud, C. Arvet*, O. Thomas, J-P. Noel, O. Rozeau, M-A. Jaud, T. Poiroux, D. Lafond, A. Toffoli, F. Allain, C. Tabone, L. Tosti, L. Brévard, P. Lehnen #, U. Weber#, P.K. Baumann#, O. Boissiere#, W. Schwarzenbach+, K. Bourdelle+, B-Y Nguyen+, F. Boeuf*, T. Skotnicki*, and O. Faynot (CEA-LETI Minatec, *STMicroelectronics, #AIXTRON AG, +SOITEC)

For the first time, the authors demonstrate low-VT (VTlin ~± 0.32) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm ION and 245μA/μm IEFF at 2nA/μm IOFF and VDD=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different VT from 0.32V to 0.6V for both nMOS and pMOS.

#8.1: Compact Modeling and Analysis of Coupling Noise Induced by Through-Silicon Vias in 3-D ICs

C. Xu, R. Suaya*, K. Banerjee (UC Santa Barbara, *Mentor Graphics)

This work presents compact models for cases without and with the high conductivity buried layer in dual-well bulk CMOS, which can be employed for keep away radius estimation. A comparative analysis of the coupling noise due to TSV in both dual-well bulk CMOS and PD-SOI is presented. The noise coupling for PD-SOI is much smaller than that of bulk CMOS due to the significantly shorter TSV height compared to that in bulk CMOS.

#8.2:  Large Signal Substrate Modeling in RF SOI Technologies

S. Parthasarathy, B. Swaminathan, A. Sundaram, R.A. Groves, R.L. Wolf, F.G. Anderson (IBM SRDC)

This paper describes a large signal high resistivity (HR) SOI substrate modeling methodology for high power circuit applications such as RF switches.  The authors show that using a varactor to model the BOX capacitor improves the harmonic distortion predictions from simulations for circuits in RF/Analog applications.

#8.5: MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation and Stress

N. Xu, X. Sun, W. Xiong*, C. R. Cleavelin, T.-J. King Liu (UC Berkeley, *Texas Instruments)

The authors made a detailed study of the impacts of fin aspect ratio and crystalline orientation and process-induced channel stress on the performance of multi-gate transistors. The MuGFETs studied in this work were fabricated on (100) SOI substrates, with either <100> or <110> fin orientation.  They found that CESL-induced stress provides for the greatest enhancement in carrier mobility and ballistic velocity, for n- and p-channel FinFETs and Tri-Gate FET structures. Extracted carrier velocity values in short-channel FinFETs still largely depend on carrier mobility.

#11.1:  Dual Strained Channel Co-Integration into CMOS, RO and SRAM Cells on FDSOI Down to 17nm Gate Length

L. Hutin, C. Le Royer, F. Andrieu, O. Weber, M. Cassé, J.-M. Hartmann, D. Cooper, A. Béché*, L. Brevard, L. Brunet, J. Cluzel, P. Batude, M. Vinet, O. Faynot (CEA LETI Minatec, CEA-INAC)

The authors presented the first successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGeOI pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells.  Strained SiGe channels were found to present up to 92% long channel mobility improvement (Eeff=0.6MV/cm); the asset of effective mass reduction is highlighted for short channel pFETs. Moreover, the co-integration with sSOI nFETs leads to well-adjusted Vth,n and Vth,p with a single mid-gap gate for high performance applications, as shown by a 39% improvement of the ring oscillators propagation delay compared to the SOI reference.

#11.2: A Solution for an Ideal Planar Multi-Gates Process for Ultimate CMOS?

S. Monfray, J.-L. Huguenin, M. Martin*, M.-P. Samson, C. Borowiak, C. Arvet, JF. Dalemcourt*, P. Perreau*, S. Barnola*, G. Bidal, S. Denorme, Y. Campidelli, K. Benotmane*, F. Leverd, P. Gouraud, B. Le-Gratiet, C. De-Butet*, L. Pinzelli, R. Beneyton, T. Morel, R.Wacquez*, J. Bustos, B. Icard*, L. Pain*, S. Barraud*, T. Ernst*, F. Boeuf, O. Faynot*, T. Skotnicki (STMicroelectronics, *CEA LETI Minatec)

The authors demonstrate for the first time high-performant planar multi-gates devices integrated on an SOI substrate, with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm. They also demonstrate an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.

#12.1: 32nm High-density High-speed T-RAM Embedded Memory Technology

R. Gupta, F. Nemati, S. Robins, K. Yang, V. Gopalakrishnan, J.J. Sundarraj, R. Chopra, R. Roy, H.-J. Cho*, W.P. Maszara*, N.R. Mohapatra*, J. Wuu**, D. Weiss**, S. Nakib (T-RAM Semiconductor, *GLOBALFOUNDRIES, **AMD)

The authors present Thyristor Random Access Memory (T-RAM) as an ideal candidate for embedded memory due to its substantially better density-performance and logic process compatibility.  T-RAM technology with substantially better density-performance tradeoff  was previously reported was previously reported at the 130nm technology node. This paper is the first to report implementation details in a 32nm HKMG SOI CMOS logic process, with read and write times of 1ns and bit fail rate under 0.5ppm.

#12.3:  A Novel Low-Voltage Biasing Scheme for Double Gate FBC Achieving 5s Retention and 1016 Endurance at 85ºC

Z. Lu, N. Collaert, M. Aoulaiche, B. De Wachter, A. De Keersgieter, W. Schwarzenbach*, O. Bonnin*, K. K. Bourdelle*, B.-Y. Nguyen**, C. Mazure*, L. Altimime, M. Jurczak (IMEC, *SOITEC, **SOITEC-USA)

A novel low-voltage biasing scheme on ultra-thin BOX FDSOI floating body cell is experimentally demonstrated. The new biasing scheme enhances the positive feedback loop. Therefore, the required VDS can be reduced to 1.5V while 5 seconds retention time can still be achieved at 85oC. Endurance up to 1016 cycles is shown.

#16.6: Realizing Super-Steep Subthreshold Slope with Conventional FDSOI CMOS at Low-Bias Voltages (Late News)

Z. Lu*#, N. Collaert*, M. Aoulaiche*, B. De Wachter*, A. De Keersgieter*, J. Fossum#, L. Altimime*, M. Jurczak* (*IMEC, #U. Florida/Gainesville)

The authors report the first experimental demonstration of a super-steep subthreshold slope (the smallest ever reported experimentally) with ultra-thin BOX FDSOI standard CMOS transistors. This work addresses the scaling challenge of continuing to reduce power consumption by lowering operation voltage.  Record steep SS of 72μV/dec for Lg=25nm and 58μV/dec for Lg=55nm are achieved with low voltages. The device also exhibits high ION (~100μA/μm), large ION/IOFF ratio of 108 with 0.5V gate swing for Lg=55nm MOSFETs and excellent reliability.

#18.3: Prospects for MEM Logic Switch Technology (Invited), T.-J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott*, E. Alon (UC Berkeley, *Institute of Microelectronics/Singapore)

This paper provides an overview of recent progress in device design, materials/process integration and technology scaling toward achieving micro-electro-mechanical  (MEM) switches suitable for ultra-low-power digital IC applications.

#27.5: A 0.039um2 High Performance eDRAM Cell Based on 32nm High-K/Metal SOI Technology

N. Butt, K. Mcstay, A. Cestero, H. Ho, W. Kong, S. Fang, R. Krishnan, B. Khan, A. Tessier, W. Davies, S. Lee, Y. Zhang, J. Johnson, S. Rombawa, R. Takalkar, A. Blauberg, K.V. Hawkins, J. Liu, S. Rosenblatt, P. Goyal, S. Gupta, J. Ervin, Z. Li, S. Galis, J. Barth, M. Yin, T. Weaver, J. H. Li, S. Narasimha, P. Parries, W.K. Henson, N. Robson, T. Kirahata, M. Chudzik, E. Maciejewski, P. Agnello, S. Stiffler, and S.S. Iyer (IBM SRDC)

The authors present the industry’s smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate SOI based logic technology. With aggressive cell scaling, High-K/Metal trench lowers parasitic resistance while maximizing capacitance. Fully-integrated 32Mb product prototypes demonstrate state-of-the-art sub 1.5ns latency with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.

#34.2:  Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI

I. Ok, K. Akarvardar*, S. Lin**, M. Baykan^, C.D. Young, P.Y. Hung, M.P. Rodgers^^, S. Bennett^^, H.O. Stamper^^, D.L. Franca^^, J. Yum#, J.P. Nadeau##, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy (SEMATECH, *GLOBALFOUNDRIES, **UMC, ^U.Florida, ^^CNSE, #U. Texas/ Austin, ##FEI)

The authors have demonstrated high performance p-channel Si/SiGe stacked FinFETs with salient features including 1) high intrinsic mobility; 2) good interface quality without the need for a Si cap between SiGe and High-k; 3) low series resistance; 4) process-induced strain additivity; and 5) a convenient threshold voltage for high performance logic using a midgap metal gate. They also demonstrate a dual channel scheme for high mobility CMOS FinFETs.

#34.3: Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement

M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida*, and T. Numata (Toshiba Corp., *Tokyo Institute of Technology)

The authors found that short-channel mobility in SOI nanowire transistors (NW Tr.) is dominated by the strain induced in the NW channel. They enhanced NW strain by the stress memorization technique (SMT). In <110> NW nFETs, Ion on the same DIBL largely increases by SMT thanks to mobility increase and parasitic resistance reduction.  They conclude that stress engineering is highly effective for the performance improvement of scaled NW Tr.

#34.5:  Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape

P. Hashemi, J.T. Teherani, J.L. Hoyt (MIT Microsystems Technology Laboratories)

The authors present a detailed study of hole mobility for gate-all-around Si NW p-MOSFETs with conformal high-k/MG and various hydrogen annealing processes. The devices are fabricated along the <110> direction on (100) thin body SOI.  Increasing hole mobility is observed with decreasing NW width down to 12 nm. A 33% hole mobility enhancement is achieved relative to universal (100) at high Ninv.

#35.4:  A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices

D.Sarkar, S. Thijs*, D. Linten*, C. Russ**, H. Gossner**, K. Banerjee, (UC Santa Barbara, *IMEC, **Infineon Technologies)

The authors investigated the impact of strain on different ESD protection devices. It is shown for the first time that the ESD sensitivity to strain can vary substantially depending on whether the devices stressed are bulk or SOI and on the mode in which they are stressed.  investigated. SOI NMOS exhibits about 20% improvement in ESD robustness in GG mode. The authors conclude that strain will play an important role in optimization of ESD device robustness of advanced CMOS technologies.


SOI’s seven ESD design advantages

SOI technology has some natural advantages in electrostatic discharge (ESD) design. At first glance, many engineers believe that it is a disadvantage to provide ESD design on SOI compared to bulk silicon technology. But, after working with SOI , there are many advantages.

Dr. Voldman’s latest book, ESD: Failure Mechanisms and Models (©2009), is the fifth in his series on ESD-related design issues. (Courtesy: John Wiley & Sons)

1 – A first advantage is elimination of parasitic elements that can lead to ESD failure mechanisms. One of the difficulties in bulk CMOS design is the parasitic “turn-on” of lateral npn devices formed between n+ diffusion, wells, and guard rings; in SOI, parasitic elements are not present. Read More

ByGianni PRATA

New Book Highlights SOI for ESD Protection

IEEE Fellow Dr. Steven H. Voldman has written another book in his electrostatic discharge (ESD) series, published by Wiley Press. As Dr. Voldman told ASN, “The new book, which has just been released, “ESD: Failure Mechanisms and Models”, addresses SOI failure mechanisms from a device, circuit and full chip integration perspective as well as including all the recent work on SOI FinFETs to 22nm. It tabulates the SOI failure mechanisms for failure analysis, circuit, and semiconductor engineers and will serve as a valuable reference text for the SOI industry.”

ByGianni PRATA

Renesas is licensing Sarnoff’s TakeCharge®

• Renesas is licensing Sarnoff’s TakeCharge® ESD technology to help accelerate the development of advanced system LSI devices applying SOI processes.