Tag Archive ETSOI

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SOI-3D-SubVt (S3S): three central technologies for tomorrow’s mainstream applications

ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.

We learned all this and much more during the very successful 2014 IEEE S3S Conference.

The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.

 S3S14banner

 

Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.

(Photo credit: Justin Lloyd)

S3S Conference Poster & reception session. (Photo credit: Justin Lloyd)

 The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.

 The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.

 

Sub-Threshold Microelectronics

The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.

3D Integration

The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).

Key Fully-Depleted SOI Technical results

Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.

STMicroelectronics and CEA-Leti gave us a wealth of information on:

  • From "Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology" in the S3S '14 "Energy Efficiency" short course by P. Flatresse (Source: STMicroelectronics)

    From “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the S3S ’14 “Energy Efficiency” short course by P. Flatresse (Source: STMicroelectronics)

    How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).

  •  How to use FMAX tracking to maintain optimal Vdd, VBB values during operation. This shows how you can take advantage of both Vdd and VBB dynamic modulation to maintain your circuit’s best performance when external conditions (e.g. temperature, supply voltage…) vary. (E. Beigné, “FDSOI Circuit Design for a Better Energy Efficiency”).

The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).

In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.

More than An Order of Magnitude Energy Improvement of

From S3S 2014 Best Paper, “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains” (AIST)

The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.

On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

Experimental SOI vs. Bulk FinFET comparison showing 50% higher VT variability on bulk (grey dots on top graph) as well as mobility difference (lower graphs).

FinFET_SOI_IBM_S3S14_Mobility_1

Join the conference in 2015!

Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.

The organizing committee is looking forward to seeing you there!

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Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory.  He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT.  Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices.  Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.

Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors.  He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999.  As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials.  As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes.  He has authored or co-authored over 50 papers and holds over 10 patents.

 

 

*RO = ring oscillator

 

 

ByAdministrator

ST’s Cesana Further Explains FD-SOI Biasing & More in On-line Discussions and LinkedIn Groups

The YouTube video Introduction to FD-SOI by STMicroelectronics and ST-Ericsson has generated enormous coverage in the press as well as in-depth discussions across various user groups in LinkedIn.  In its first two weeks, it had over 3000 YouTube views, and LinkedIn postings of it generated over 50 Likes and Comments in a single group.

Introduction to FD-SOIAs you no doubt know by now, at CES a few weeks ago, ST-Ericsson showed the new NovaThor L8580, which integrates an eQuad 2.5GHz processor based on the ARM Cortex-A9, an Imagination PowerVR™ SGX544 GPU running at 600Mhz and an advanced multimode LTE modem on a single 28nm FD-SOI die. Process technology and manufacturing credit goes to ST.  In a live video from the show, the chip reached 2.8GHz in a high-performance demo, and in a low-power demo hit 1GHz using just 0.636V (which would take 1.1V on bulk).

Since then, Giorgio Cesana, Director of Technology Marketing at STMicroelectronics, has been everywhere, responding to questions from readers and correcting misunderstandings as they arise.

One of the top things people want to know more about is biasing in FD-SOI, which can provide a big performance boost or huge power savings.

LinkedIn In case you missed it, here’s what Giorgio had to say to questions posed in the big LinkedIn Semiconductor Professional’s Group:

Thank you all for this interesting discussion and for giving me the opportunity to provide more details about the ST 28nm FD-SOI technology. I hope this clarifies any misunderstandings.” 


Body bias, or more properly back bias (because biasing is done on the back face of the transistor) is a way to electrically control the Vt of the device by controlling of the polarization of the wells. 


Conceptually, it is like having the planar transistor controlled by two gates: the real “classical” gate, we build with a HKMG, gate-first manufacturing approach, and a virtual gate (represented in the video with a transparent gate below the transistor) that represents the capability to control the transistor through biasing. 


The back gate is the “virtual” one. It does not require any extra manufacturing steps to be fabricated. It is created simply by polarizing the well. 


The particular FD-SOI technology that ST is using, called UTTB (Ultra Thin Body and Box), benefits from a extremely thin (25nm) Buried Oxide (BOX) which enables extremely efficient control of the transistor threshold voltage through the biasing, up to 80mV/V. In addition, because of the insulator in FD-SOI, biasing is not limited to 300mV like in bulk technologies, allowing an extremely wide dynamic control of the transistor Vt. 


In terms of biasing efficiency, this past Dec 10th we published some figures for 600mV forward body bias in 28nm, showing up to 45% speed increase when running cores at 0.6V. 

That said, exploiting body biasing is a matter of making a design that provides an independent supply to the wells, managed through the power supply controller, to optimize the Vt to reach proper energy efficiency, balancing the static and dynamic part of the power consumption. Of course biasing conditions should be considered at design optimization and sign-off phase. 


Finally body/back biasing in FinFETs simply does not work, because the transistor channel is vertical and the gate controls 3 sides of the channel. The 4th side (the one sitting on the substrate) is too narrow to be influenced through body biasing. Body biasing is simply not an option with FinFETs. 


Someone at one of the big programmable device companies then asked a follow-up question on the implementation. Giorgio responded:

In 28nm FD-SOI, threshold-voltage centering is a function of the gate work function, where the Vt is controlled by implanting a ground plane (GP) below the BOX (Buried Oxide). Depending on its type (N or P), Vt can be raised by more than 50mV, allowing the manufacturer to offer two device flavors: regular Vt and low Vt. 


Threshold voltage is also statically controlled by modulating the gate length. ST’s multi-channel standard-cell library allows us to modulate the gate length up to +16nm, offering a static leakage control of up to 50x for a single Vt design, almost twice the leakage control offered by dual-Vt designs plus multi-channel libraries of competing bulk planar technologies. 


Body bias is just one way to modulate the threshold voltage, and the dynamic nature of the control allows new and innovative design solutions to be implemented for extremely energy efficient designs.

I should note that body-bias usage is not mandatory in FD-SOI: we can make devices without using it and which still benefit from a good speed/power balance, low Vmin memories, better device variability, and all the other benefits FD-SOI processing offer. Chip architects can also decide to limit body-bias adoption only to some critical blocks/IPs in the SoC for the best trade-off between optimal energy efficiency and implementation simplicity. 

For further reference, you may read F. Arnaud, “Switching Energy Efficiency Optimization for Advanced CPU thanks to UTBB Technology,” IEDM 2012.

To reader questions posted in the comments sections of SST and EETimes articles, Giorgio cleared up some other misunderstandings. Here is a summary of some of the things he said:

FD-SOI vs. PD-SOIUltra-Thin Body and Buried Oxide (UTBB) FD-SOI technology is very different from Partially-Depleted technologies manufactured before. Those partially-depleted technologies were affected by floating-body effects where the body was subject to an uncontrolled charging/discharging that led transistor behavior to depend on the previous transitions –i.e. making them suffer from a kind of memory effect.

In UTBB FD-SOI technology, hybridation lets us contact the body, so it is not left floating, overcoming the problems with PD-SOI technologies.

Self-heating: Self-heating is also a problem that exists with Partially-Depleted SOI technologies, where the Buried Oxide thickness (~150nm) was thermally isolating transistors from the substrate, leading to self-heating effects.

UTBB FD-SOI technology offers two advantages to overcome this self-heating:

– The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;

– The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them.

Wafer thickness: The ST process specification is for wafers with 12nm thick silicon (+/- 5A). Process manufacturing then “uses” part of the silicon film for the manufacturing of the transistors, leading to a final 7nm film below the transistors.

We are moving from a raw 12nm thick silicon film (=120A, +/- 5A) to a final film of 7nm (=70A) under the transistors. This is a perfectly repeatable process and is already qualified for production at ST.

Wafer costs: UTBB FD-SOI technology manufacturing uses up to 15% fewer steps vs. our bulk planar 28LP HKMG gate-first technology. This process simplification, by itself, is capable of totally compensating for the current substrate cost difference. Then, we expect in high volume production, UTBB FD-SOI die costs should be even better than bulk planar, with substrate-cost erosion and with UTBB FD-SOI improving electrical yield over bulk planar.

Manufacturability: to prove manufacturability, the recent announcement from ST-Ericsson about their NovaThor L8580 product, which was demonstrated at CES, is capable of running its eQuad ARM cores up to 2.8GHz, while still fitting a mobile smartphone thermal footprint and proving (if needed) the potential and the maturity of FD-SOI technology.

Additional recommended reading:

– O. Faynot et al, “Planar Fully Depleted SOI Technology: a powerful architecture for the 20nm node and beyond”, International Electron Device Meeting Technical Digest, 2010
– Advantages of UTBB FD-SOI:  A. Khakifirooz at al., “Extremely thin SOI for system-on-chip applications”, CICC 2012*, written by authors from IBM, STMicroelectronics, LETI, Renesas, and GLOBALFOUNDRIES.

*Editor’s note: ETSOI is what IBM calls its flavor of FD-SOI.

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To keep up-to-date on the latest in SOI-related news, please join us at the Advanced Substrate News LinkedIn group.

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FDSOI Processes are Cost Competitive with Bulk

A new study compares processes for the 20/22nm generation at a typical foundry.

Silicon On Insulator (SOI) has been in use for state-of-the-art integrated circuit (IC) manufacturing since IBM first championed the technology in the mid-nineties. SOI offers process technologists the option of reducing power or improving performance for a given process node.

As process technology has continued to advance it has become practical to manufacture SOI wafers with silicon layers that are thin enough for  Fully Depleted SOI (FDSOI).  Also referred to as Extremely Thin SOI (ETSOI), FDSOI processes offer process technologists the opportunity to significantly simplify the process of manufacturing an IC.

IC Knowledge, the world leader in IC cost and economics was retained by Soitec, the world leader in SOI wafer manufacturing, to compare the cost of a FDSOI process versus a Bulk process for 22nm/20nm foundry logic processes.

Threshold voltages

One of the challenges of state-of-the-art foundry processes is providing the multiple threshold voltages required for power management and performance. At a minimum an additional threshold voltage requires two threshold adjust masks and associated implants.

As process geometries have shrunk additional threshold voltages may also require tailoring of source/drain (S/D) extension and halo implants and even S/D contact implants (both extension/halo and contacts each require multiple implants to fabricate).

The result is a single threshold voltage can require up to five masks and fifteen implants.

FDSOI on the other hand can provide multiple threshold voltages by alternative means (including the option to shift the threshold voltage by actively controlling the biasing of the back gate),  eliminating the need for threshold adjust masks and implants entirely.

Process simplification

An FDSOI foundry process with eight metal levels and three threshold voltages can be fabricated with up to fifteen less masking steps and forty-eight fewer implants than a similar bulk process. The resulting process simplification was found to more than offset the higher cost of the starting SOI substrate and result in a cost competitive process versus bulk with better performance.

As processes scale down to 22nm/20nm and beyond standard bulk process transistors can no longer be scaled down without exhibiting unacceptable leakage properties. Techniques such as FDSOI offer better control of the transistor channel and far lower leakage making them a viable technical solution to leakage problems. As has been shown in this study FDSOI also offers an economically viable solution.

In conclusion FDSOI processes offer sufficient process simplification to offset the additional cost of the starting SOI substrate and be cost competitive with bulk processes.

Note: the full FD-SOI cost report is available as a free download from IC Knowledge.

ByGianni PRATA

SOI at IEDM 2010

The 2010 IEEE International Electron Devices Meeting (IEDM) was held December 6-8, 2010 in San Francisco. The IEDM continues to be the world’s premier venue for presenting the latest breakthroughs and the broadest and best technical information in electronic device technologies.

Here are summaries of key papers referencing work on SOI or other advanced substrates.

(Note: at the time of this posting, the papers are not yet available from the  IEEE Xplore website.  However, many are available from the Advanced Silicon Device and Process Lab at the National Taiwan University.)


Paper #1.2: Energy Efficiency Enabled by Power Electronics
Arunjai Mittal (Infineon)

In particular, see section 4, where the author addresses the huge energy savings that can be realized using variable speed motors. Infineon’s driver ICs (which take a logic signal output from a microcontroller chip in the control system, and provide the appropriate current and voltage to turn power devices on and off) are built on SOI. (See Infineon’s article in ASN7. Infineon and LS Industrial Systems started a JV in 2009 called the LS Power Semitech Co., which leverages this technology.)


#2.6: Engineered Substrates and 3D Integration Technology Based on Direct Bonding for Future More Moore and More than Moore Integrated Devices (Invited)

L. Clavelier, C. Deguet, L. Di Cioccio, E. Augendre, A. Brugere, P. Gueguen, Y Le Tiec, H. Moriceau, M. Rabarot, T. Signamarcheix, J. Widiez, O. Faynot, F. Andrieu, O. Weber, C. Le Royer, P. Batude, L. Hutin, J.F. Damlencourt, S. Deleonibus, E. Defaÿ, (CEA/LETI Minatec)

This paper deals with new generations of substrates and 3D integration techniques, based on direct bonding techniques, enabling future devices in the More Moore and in the More than Moore areas.


#3.2 : Planar Fully Depleted SOI Technology: A Powerful Architecture for the 20nm Node and Beyond (Invited)

O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brévard, C. Tabone, P. Gaud, S. Barraud, T. Ernst and S. Deleonibus (CEA/LETI Minatec)

The authors of this paper say that for 20nm node and below, they have proven that planar undoped channel Fully Depleted SOI devices are easier to integrate than bulk, non planar devices like FinFET. The paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed.


#3.3:  Anomalous Electron Mobility in Extremely-Thin SOI (ETSOI) Diffusion Layers with SOI Thickness of Less Than 10 nm and High Doping Concentration of Greater Than 1x1018cm-3

N. Kadotani,T. Takahashi, K. Chen,T. Kodera, S. Oda, K. Uchida*  (Tokyo Institute of Technology, *also with PRESTO)

This paper is the first to report carrier transport in heavily doped ETSOI diffusion layers. The authors found that electron mobility in the heavily doped ETSOI diffusion layer is totally different from electron mobility in heavily doped bulk Si. In other words, electron mobility is enhanced in thinner ETSOI diffusion layers (Tsoi>5nm), whereas electron mobility is degraded as dopant concentration increases when Tsoi is 2nm. The authors conclude that this information will be indispensable for the design of aggressively scaled ETSOI devices as well as 3D FETs.


#3.4:  Work-function Engineering in Gate First Technology for Multi-VT Dual-Gate FDSOI CMOS on UTBOX

O. Weber, F. Andrieu, J. Mazurier, M. Cassé, X. Garros, C. Leroux, F. Martin, P. Perreau, C. Fenouillet-Béranger, S. Barnola, R. Gassilloud, C. Arvet*, O. Thomas, J-P. Noel, O. Rozeau, M-A. Jaud, T. Poiroux, D. Lafond, A. Toffoli, F. Allain, C. Tabone, L. Tosti, L. Brévard, P. Lehnen #, U. Weber#, P.K. Baumann#, O. Boissiere#, W. Schwarzenbach+, K. Bourdelle+, B-Y Nguyen+, F. Boeuf*, T. Skotnicki*, and O. Faynot (CEA-LETI Minatec, *STMicroelectronics, #AIXTRON AG, +SOITEC)

For the first time, the authors demonstrate low-VT (VTlin ~± 0.32) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-VT pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm ION and 245μA/μm IEFF at 2nA/μm IOFF and VDD=0.9V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different VT from 0.32V to 0.6V for both nMOS and pMOS.


#8.1: Compact Modeling and Analysis of Coupling Noise Induced by Through-Silicon Vias in 3-D ICs

C. Xu, R. Suaya*, K. Banerjee (UC Santa Barbara, *Mentor Graphics)

This work presents compact models for cases without and with the high conductivity buried layer in dual-well bulk CMOS, which can be employed for keep away radius estimation. A comparative analysis of the coupling noise due to TSV in both dual-well bulk CMOS and PD-SOI is presented. The noise coupling for PD-SOI is much smaller than that of bulk CMOS due to the significantly shorter TSV height compared to that in bulk CMOS.


#8.2:  Large Signal Substrate Modeling in RF SOI Technologies

S. Parthasarathy, B. Swaminathan, A. Sundaram, R.A. Groves, R.L. Wolf, F.G. Anderson (IBM SRDC)

This paper describes a large signal high resistivity (HR) SOI substrate modeling methodology for high power circuit applications such as RF switches.  The authors show that using a varactor to model the BOX capacitor improves the harmonic distortion predictions from simulations for circuits in RF/Analog applications.


#8.5: MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation and Stress

N. Xu, X. Sun, W. Xiong*, C. R. Cleavelin, T.-J. King Liu (UC Berkeley, *Texas Instruments)

The authors made a detailed study of the impacts of fin aspect ratio and crystalline orientation and process-induced channel stress on the performance of multi-gate transistors. The MuGFETs studied in this work were fabricated on (100) SOI substrates, with either <100> or <110> fin orientation.  They found that CESL-induced stress provides for the greatest enhancement in carrier mobility and ballistic velocity, for n- and p-channel FinFETs and Tri-Gate FET structures. Extracted carrier velocity values in short-channel FinFETs still largely depend on carrier mobility.


#11.1:  Dual Strained Channel Co-Integration into CMOS, RO and SRAM Cells on FDSOI Down to 17nm Gate Length

L. Hutin, C. Le Royer, F. Andrieu, O. Weber, M. Cassé, J.-M. Hartmann, D. Cooper, A. Béché*, L. Brevard, L. Brunet, J. Cluzel, P. Batude, M. Vinet, O. Faynot (CEA LETI Minatec, CEA-INAC)

The authors presented the first successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGeOI pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells.  Strained SiGe channels were found to present up to 92% long channel mobility improvement (Eeff=0.6MV/cm); the asset of effective mass reduction is highlighted for short channel pFETs. Moreover, the co-integration with sSOI nFETs leads to well-adjusted Vth,n and Vth,p with a single mid-gap gate for high performance applications, as shown by a 39% improvement of the ring oscillators propagation delay compared to the SOI reference.


#11.2: A Solution for an Ideal Planar Multi-Gates Process for Ultimate CMOS?

S. Monfray, J.-L. Huguenin, M. Martin*, M.-P. Samson, C. Borowiak, C. Arvet, JF. Dalemcourt*, P. Perreau*, S. Barnola*, G. Bidal, S. Denorme, Y. Campidelli, K. Benotmane*, F. Leverd, P. Gouraud, B. Le-Gratiet, C. De-Butet*, L. Pinzelli, R. Beneyton, T. Morel, R.Wacquez*, J. Bustos, B. Icard*, L. Pain*, S. Barraud*, T. Ernst*, F. Boeuf, O. Faynot*, T. Skotnicki (STMicroelectronics, *CEA LETI Minatec)

The authors demonstrate for the first time high-performant planar multi-gates devices integrated on an SOI substrate, with Si-conduction channel of 4nm, allowing drive current up to 1350μA/μm @Ioff=0.4nA/μm. They also demonstrate an ideal planar self-aligned solution, based on the direct exposure of a HSQ layer through a 5nm Si-channel. This opens the way to an easy planar multi-gate process for ultimate CMOS (11nm node & below), fully co-integrable with conventional devices.


#12.1: 32nm High-density High-speed T-RAM Embedded Memory Technology

R. Gupta, F. Nemati, S. Robins, K. Yang, V. Gopalakrishnan, J.J. Sundarraj, R. Chopra, R. Roy, H.-J. Cho*, W.P. Maszara*, N.R. Mohapatra*, J. Wuu**, D. Weiss**, S. Nakib (T-RAM Semiconductor, *GLOBALFOUNDRIES, **AMD)

The authors present Thyristor Random Access Memory (T-RAM) as an ideal candidate for embedded memory due to its substantially better density-performance and logic process compatibility.  T-RAM technology with substantially better density-performance tradeoff  was previously reported was previously reported at the 130nm technology node. This paper is the first to report implementation details in a 32nm HKMG SOI CMOS logic process, with read and write times of 1ns and bit fail rate under 0.5ppm.


#12.3:  A Novel Low-Voltage Biasing Scheme for Double Gate FBC Achieving 5s Retention and 1016 Endurance at 85ºC

Z. Lu, N. Collaert, M. Aoulaiche, B. De Wachter, A. De Keersgieter, W. Schwarzenbach*, O. Bonnin*, K. K. Bourdelle*, B.-Y. Nguyen**, C. Mazure*, L. Altimime, M. Jurczak (IMEC, *SOITEC, **SOITEC-USA)

A novel low-voltage biasing scheme on ultra-thin BOX FDSOI floating body cell is experimentally demonstrated. The new biasing scheme enhances the positive feedback loop. Therefore, the required VDS can be reduced to 1.5V while 5 seconds retention time can still be achieved at 85oC. Endurance up to 1016 cycles is shown.


#16.6: Realizing Super-Steep Subthreshold Slope with Conventional FDSOI CMOS at Low-Bias Voltages (Late News)

Z. Lu*#, N. Collaert*, M. Aoulaiche*, B. De Wachter*, A. De Keersgieter*, J. Fossum#, L. Altimime*, M. Jurczak* (*IMEC, #U. Florida/Gainesville)

The authors report the first experimental demonstration of a super-steep subthreshold slope (the smallest ever reported experimentally) with ultra-thin BOX FDSOI standard CMOS transistors. This work addresses the scaling challenge of continuing to reduce power consumption by lowering operation voltage.  Record steep SS of 72μV/dec for Lg=25nm and 58μV/dec for Lg=55nm are achieved with low voltages. The device also exhibits high ION (~100μA/μm), large ION/IOFF ratio of 108 with 0.5V gate swing for Lg=55nm MOSFETs and excellent reliability.


#18.3: Prospects for MEM Logic Switch Technology (Invited), T.-J. King Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott*, E. Alon (UC Berkeley, *Institute of Microelectronics/Singapore)

This paper provides an overview of recent progress in device design, materials/process integration and technology scaling toward achieving micro-electro-mechanical  (MEM) switches suitable for ultra-low-power digital IC applications.


#27.5: A 0.039um2 High Performance eDRAM Cell Based on 32nm High-K/Metal SOI Technology

N. Butt, K. Mcstay, A. Cestero, H. Ho, W. Kong, S. Fang, R. Krishnan, B. Khan, A. Tessier, W. Davies, S. Lee, Y. Zhang, J. Johnson, S. Rombawa, R. Takalkar, A. Blauberg, K.V. Hawkins, J. Liu, S. Rosenblatt, P. Goyal, S. Gupta, J. Ervin, Z. Li, S. Galis, J. Barth, M. Yin, T. Weaver, J. H. Li, S. Narasimha, P. Parries, W.K. Henson, N. Robson, T. Kirahata, M. Chudzik, E. Maciejewski, P. Agnello, S. Stiffler, and S.S. Iyer (IBM SRDC)

The authors present the industry’s smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate SOI based logic technology. With aggressive cell scaling, High-K/Metal trench lowers parasitic resistance while maximizing capacitance. Fully-integrated 32Mb product prototypes demonstrate state-of-the-art sub 1.5ns latency with excellent retention and yield characteristics. The sub 1.5ns latency and 2ns cycle time have been verified with preliminary testing whereas even better performance is expected with further characterization. In addition, the trench capacitors set the industry benchmark for the most efficient decoupling in any 32nm technology.


#34.2:  Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI

I. Ok, K. Akarvardar*, S. Lin**, M. Baykan^, C.D. Young, P.Y. Hung, M.P. Rodgers^^, S. Bennett^^, H.O. Stamper^^, D.L. Franca^^, J. Yum#, J.P. Nadeau##, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy (SEMATECH, *GLOBALFOUNDRIES, **UMC, ^U.Florida, ^^CNSE, #U. Texas/ Austin, ##FEI)

The authors have demonstrated high performance p-channel Si/SiGe stacked FinFETs with salient features including 1) high intrinsic mobility; 2) good interface quality without the need for a Si cap between SiGe and High-k; 3) low series resistance; 4) process-induced strain additivity; and 5) a convenient threshold voltage for high performance logic using a midgap metal gate. They also demonstrate a dual channel scheme for high mobility CMOS FinFETs.


#34.3: Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement

M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida*, and T. Numata (Toshiba Corp., *Tokyo Institute of Technology)

The authors found that short-channel mobility in SOI nanowire transistors (NW Tr.) is dominated by the strain induced in the NW channel. They enhanced NW strain by the stress memorization technique (SMT). In <110> NW nFETs, Ion on the same DIBL largely increases by SMT thanks to mobility increase and parasitic resistance reduction.  They conclude that stress engineering is highly effective for the performance improvement of scaled NW Tr.


#34.5:  Investigation of Hole Mobility in Gate-All-Around Si Nanowire p-MOSFETs with High-k/Metal-Gate: Effects of Hydrogen Thermal Annealing and Nanowire Shape

P. Hashemi, J.T. Teherani, J.L. Hoyt (MIT Microsystems Technology Laboratories)

The authors present a detailed study of hole mobility for gate-all-around Si NW p-MOSFETs with conformal high-k/MG and various hydrogen annealing processes. The devices are fabricated along the <110> direction on (100) thin body SOI.  Increasing hole mobility is observed with decreasing NW width down to 12 nm. A 33% hole mobility enhancement is achieved relative to universal (100) at high Ninv.


#35.4:  A Quantitative Inquisition into ESD Sensitivity to Strain in Nanoscale CMOS Protection Devices

D.Sarkar, S. Thijs*, D. Linten*, C. Russ**, H. Gossner**, K. Banerjee, (UC Santa Barbara, *IMEC, **Infineon Technologies)

The authors investigated the impact of strain on different ESD protection devices. It is shown for the first time that the ESD sensitivity to strain can vary substantially depending on whether the devices stressed are bulk or SOI and on the mode in which they are stressed.  investigated. SOI NMOS exhibits about 20% improvement in ESD robustness in GG mode. The authors conclude that strain will play an important role in optimization of ESD device robustness of advanced CMOS technologies.

ByFanny Rodriguez

ETSOI Substrates: What We Needi

IBM’s roadmap to ETSOI – Extremely Thin Silicon on Insulator – calls for very thin, very flat SOI substrates. Here’s why.

ETSOI transistors are thin-channel planar devices. Halo implantation is used to control electrostatics in conventional transistors. Although the halo controls the short channel effects, it also causes large random doping fluctuations and increases junction leakage and GILD, which are critical to low power platforms.
Electrostatics for ETSOI devices on the other hand, are controlled by the thin silicon on insulator (SOI) channel. One critical challenge is that threshold voltage variation for ETSOI is largely determined by silicon thickness variations. While ETSOI offers the promise of improved device characteristics, when billions or more of these transistors are integrated to create large scale circuits, the circuit performance will depend to a large extent on the flatness of the starting SOI wafer. Read More