Tag Archive FD-SOI


Substrate strategies for high-performance and low-power applications at 45 nm

Two distinct technical strategies for advanced substrates will mark the 45nm node. One will be focused on high performance, the other driven by system-on-chip (SOC) applications, including low power, portable RF applications.

The high performance path will drive the most advanced substrates and material innovations. Engineered substrate solutions include ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques, as well as improved thermal dissipation to reduce the impact of hot spot impact. While device architectures are likely to remain planar, Read More

ByGianni PRATA

EDS Honors SOI Pioneer

SOI pioneer Jerry G. Fossum has received the most recent J.J. Ebers award, “For outstanding contributions to the advancement of SOI CMOS devices and circuits through modeling.”

He thereby joins such industry luminaries as Andrew Grove and Bernard Meyerson in receiving one of the Electron Devices Society’s (EDS) and IEEE’s highest honors. Read More

ByGianni PRATA

45nm Multi-Gated FET (MuGFET) Devices and Test Circuits on SOI

The reticle used for this wafer is a 45nm technology test vehicle. Lithography was done using a 193nm wavelength scanner. Devices are made on a Soitec™ UNIBOND™ SOI wafer (88nm Si thickness / 145nm BOx thickness).

Courtesy of Texas Instruments, Infineon and Advanced Technology Development Facility (ATDF, a subsidiary of SEMATECH)

The reticle was designed to print fins down to 30nm fin width and it incorporated various capacitors, NMOS/PMOS/CMOS transistors (planar & non-planar), ESD structures, Kelvin structures and various test circuits (Ring Oscillators, loaded gates, Current Mirrors, OP-AMPs, SRAM cells, and reliability test sites). Read More