IEEE S3S Conference
10-13 October 2016
Hyatt Regency San Francisco Airport
IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference
Theme: Energy Efficient Technology for the Internet of Things
Late News submissions open and Advance Program available
The IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.
This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.
We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.
Our Keynote speakers are decision-makers from major industries:
Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.
Applications will be illustrated in our session dedicated to SOI circuit implementations.
You can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.
And you still have time to actively participate by submitting a late news paper before August 31st.
The conference has a long tradition of allying technical and social activities.
This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.
With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.
Deadline for Late News submissions is
August 31st, 2016
For further information, please visit our website at s3sconference.org or contact the conference manager:
Joyce Lloyd • 6930 De Celis Pl., #36
Van Nuys, CA 91406
T 818.795.3768 • F 818.855.8392 • E email@example.com
Design & Reuse, in partnership with GlobalFoundries, ST, Soitec and Leti, is sponsoring a series of FD-SOI IP Workshops around the globe. (Click here for more information.) These working days aim at sharing information about IP that’s currently available or is being designed for FD-SOI technology.
The first conference will take place during DATE in Dresden on 14 March 2016. Following that, conferences will also be held in Bangalore in April, Shanghai in September, and Grenoble in December.
Short summary submissions are now being solicited from designers offering IPs that are either currently in validation, are already silicon-proven, or are in production. The deadline for submissions to the Dresden event is 15 February. A prize will be awarded to the most innovative IP.
FD-SOI specific design flow or module presentations are also welcome.
The organizers are all members of the European Things2Do program (read about that here), which includes about 50 partners working on the FD-SOI ecosystem.
A recent NewElectronics article entitled ST’s FD-SOI transistor is set to give analogue designers a new knob to tune parameters, explores the many reasons that FD-SOI makes designers happy – even the analog folks. Editor Graham Pitcher talked to analog designer Andreia Cathelin, a senior member of STMicroelectronics’ technical staff. Among plenty of other things, she noted that with FD-SOI, “…transistors can offer the same analogue gain as they did at 130nm, but with the advantages of a 28nm channel.”(Read the full article here.)
It also helps simplify tuning in that you can change one parameter (linearity, noise, power consumption) without the change affecting the other parameters, she notes. For digital, she especially likes that FD-SOI can be biased up to +2V, compared to about 0.3V for bulk.
She concludes, ” “Analogue designers are happier; the transistor is back to offering good intrinsic performance and there is a ‘knob’ outside of the signal path. But if designers want to get the most out of FD-SOI, they will need to think about what they can do with that ‘knob’.”
A recommended read.
Soitec, the world’s SOI wafer leader, announced that the Board of Directors has named André-Jacques Auberton-Hervé as Chairman Emeritus (he founded Soitec together with Jean-Michel Lamure in 1992).
CEO Paul Boudre has been appointed Chairman of Soitec’s Board of Directors.
(Read the press release here.)
FD-SOI champion STMicroelectronics has unveiled the company’s first System-on-Chip (SoC) products on FD-SOI. Two multi-core ARM SoC offerings – both for set-top boxes – have been announced. ST credits the 28nm FD-SOI silicon technology with providing highly-efficient RF and analog integration as well as outstanding power efficiency so that set-top box makers can now design very small fan-less systems. The announcements include:
Both are currently sampling to lead customers.
An excellent article in SST details Leti’s monolithic 3D (M3D) technology, as presented at the SemiconWest 2014 Leti Day (read the full article here). Written by Brian Cronquest, MonolithIC 3D’s VP Technology & IP, the piece covers a presentation given by Olivier Faynot, Leti’s Device Department Director, about “monolithic 3D technology as the ‘solution for scaling’.” Cronquest puts the big picture in perspective, while providing plenty of technical information. He ends by reminding readers that this and other key work will be further detailed at the IEEE S3S Conference (S3S = SOI + 3D + Subthreshold Microelectronics) October 6-9, 2014 at the Westin San Francisco Airport (see the conference website here).
ST has signed a new foundry for 28nm FD-SOI manufacturing, but isn’t yet saying who it is.
In a press release issued with the STMicroelectronics’ 2014 First Quarter Financial Results (read press release here), Jean-Marc Chery, Executive Vice President and General Manager, Embedded Processing Solutions, said, “We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assures the industry of high-volume production of ST’s FD-SOI based IC solutions for faster, cooler, and simpler devices and strengthens the business and financial prospects of the Embedded Processing Solutions Segment.”
During the subsequent call with analysts (transcript on Seeking Alpha here), CEO Carlo Bozotti added that, “ST’s unique FD-SOI technology is well on its way to become a significant revenue generator for 2015 and beyond….”
By Ali Khakifirooz (Spansion)
One of the unique features of the FD-SOI technology is the ability of using a wide range of body bias to modulate the transistor VT. Unlike bulk planar technology, where the maximum body bias is limited by p-n junction leakage and potential latch-up, in FD-SOI technology the full range of forward body bias (FBB) is available owing to oxide isolation and the use of flip-well structure .
While designers are familiar with the concept of body biasing and have been using it in different forms for many years in bulk CMOS technology, concerns are occasionally raised – often from non-designers – about the complexity and effectiveness of body biasing in advanced nodes.
Body biasing has been known for many years  and was in fact identified as a key technology enabler in sub-0.1µm era by industry leaders . Although ironically the recent move to the FinFET structure removed this gadget from the designers’ toolbox, the need for body biasing is still echoed .
Early studies demonstrated the effectiveness of body biasing in reducing leakage, improving performance, and reducing variability and thereby worst-case power consumption in complex circuits [5-7]. It was, however, pointed out that due to the competing effect of other leakage mechanisms, such as band-to-band tunneling, the effectiveness of reverse body bias (RBB) in managing leakage diminishes with technology scaling . Nonetheless Intel continued using body biasing at least down to 45nm node .
Static Body Biasing
Device variability is one of the key detractors of product yield. Historically, the desktop-driven semiconductor industry used product binning to turn this natural performance variability into profit. However, it is known that changes in market demand or process may lead to significant imbalance between the demand and inventory . Moreover, with the emergence of mobile applications as the dominant technology driver  and strict power requirements, binning is not effective anymore. With the desire to reduce VDD below 0.8V in order to reduce active power, managing the device variability becomes increasingly important.
Body biasing has been long considered as an effective and relatively easy way to compensate for some of the process variations. Not only does it lead to a tighter performance distribution and better yield, but also by mitigating the guardband requirements for process corners and temperature variation, it leads to better performance and faster design cycle.
For example, in a media processor design in 65nm technology a 20% reduction in the worst-case delay was achieved by using an embedded FBB circuit . While most body biasing designs are geared toward keeping VT constant, it has been shown that a combination of VT and drive current control leads to significantly tighter distribution (an 85% reduction in variation) and 25% reduction in total power . These numbers are well comparable to the power saving expected from scaling the design by one technology node. Given the concerns about the saturation of cost scaling beyond 28nm, an FD-SOI design with a wide range of body biasing is thus very appealing.
Dynamic Body Biasing
For applications with varied workload, a more elaborate use of body bias is to adjust the transistor performance based on the workload. This can be, of course, combined with other known low-power techniques such as dynamic voltage and frequency scaling (DVFS), sleep transistors, power gating, etc. In particular, when combined with DVFS, the optimum VT for each VDD can be used to minimize total power .
Design Complexity and Area Overhead
Potentially added design complexity and area overhead due to body bias generation circuits and routing is sometimes voiced as a concern. Static body biasing is relatively easy to implement. Depending on the level of sophistication it requires some sensing circuits (leakage, delay, skew, temperature, etc.), charge pump circuits to generate the body bias, and a network to distribute it across the chip. In typical designs, this does not impose more than 1-2% area overhead. The design complexity is actually reduced as less resources are needed to meet target performance across process and temperature corners. Notable bulk CMOS designs that used body bias to reduce variability include Samsung’s ExynosTM SoC in both 32nm and 28nm node [13-14], and Oracle’s SPARC processors in 40nm .
Dynamic body biasing, on the other hand, needs additional system and software development. However, we do not expect this to be more complex than implementing any other low-power technique such as dynamic voltage scaling. An example is TI’s 45nm OMAP SoC that used body bias as a part of their SmartReflex technology (Figure 1) .
Figure 1. Example of combined dynamic body bias and voltage scaling in TI’s 45nm SoC . Proper VDD and body bias is selected based on the power mode and process corner. (Courtesy: ISSCC, TI)
No Body Effect?
While many bulk CMOS designs used body bias in some form, on the other end of the spectrum are the designs that used PD-SOI technology, where majority of the devices do not have a body contact. The lack of body effect in PD-SOI devices was claimed to help stacked transistors and passgates, leading to 15-25% speed improvement . For designers that prefer a zero-body-effect style, the move to FinFET or a thick BOX FD-SOI structure seems more natural. However, for mainstream applications where power and parametric yield are the main drivers, thin BOX FD-SOI and use of body bias is more sensible.
– – –
 D. Jacquet, et al., “A 3 GHz dual core processor ARM CortexTM-A9 in 28 nm UTBB FD-SOI CMOS with ultra-wide voltage range and energy efficiency optimization,” IEEE JSSC, p. 812, 2014.
 M. Kube, R. Hori, O. Minato, and K. Sato, “A threshold voltage controlling circuit for short channel MOS integrated circuits,” ISSCC, p. 54, 1976.
 S. Thompson, I. Young, J. Greason, and M. Bohr, “Dual threshold voltage and substrate bias: Keys to high performance, low power, 0.1 µm logic designs,” Symp. VLSI Tech., p. 69, 1997.
 G. Yeap, “Smart mobile SoCs driving the semiconductor industry: technology trend, challenges and opportunities,” IEDM Tech. Dig., p. 1.3.1, 2013.
 M. Miyazaki, et al., “A 1000-MIPS/W microprocessor using speed adaptive threshold-voltage CMOS with forward bias,” ISSCC, p. 420, 2000.
 S. Narendra, et al., “1.1V 1GHz communication router with on-chip body bias in 150nm CMOS,” ISSCC, p. 218, 2002.
 J. Tchanz, et al., “Adaptive body bias for reducing impact of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” ISSCC, p. 422, 2002.
 A. Keshavarzi, et al., “Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC’s,” ISLPED, p. 252, 1999.
 F. Hamzaoglu, et al., A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm high-k metal-gate CMOS technology,” ISSCC, p. 376, 2008.
 J.Y. Chen, “GPU technology trends and future requirements,” IEDM Tech. Dig., p. 3, 2009.
 S. Nomura, et al., “A 9.7mW AAC-decoding, 620mW H.264 720p 60fps decoding, 8-core media processor with embedded forward-body-biasing and power-gating circuit in 65nm CMOS technology,” ISSCC, p. 262, 2008.
 M. Sumita, et al., “Mixed body-bias technique with fixed Vt and Ids generation circuits,” ISSCC, p. 158, 2004.
 S.-H. Yang, et al., “A 32nm high-k metal gate application processor with GHz multi-core CPU,” ISSCC, p. 214, 2012.
 Y. Shin, et al., “28nm high-k metal-gate heterogeneous quad-core CPUs for high-performance and energy efficient mobile application processor,” ISSCC, p. 154, 2013.
 J.L. Shin, et al., “A 40nm 16-core 128-thread CMT SPARC SoC processor,” ISSCC, p. 98, 2010.
 G. Gammie, et al., “A 45nm 3.5G baseband-and-multimedia application processor sing adaptive body-bias and ultra-low-power techniques, ISSCC, p. 258, 2008.
 M. Canada, et al., “A 580MHz RISC microprocessor in SOI,” ISSCC, p. 430, 1999.
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At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor.
Here are some of the highlights (the complete presentations are all available from the CMP website).
Presented by Philippe Magarshack, Technology R&D Group Vice-President and Central CAD GM at STMicroelectronics – Download pdf
Presented by Jean-Marc Talbot, Senior Director of Engineering Analog & Mixed Signal at Mentor Graphics Grenoble R&D Center – Download pdf
The advantages of back-biasing increase as you shrink the SOI layers, so it will get even better with each node!
A few other notables from the DATE conference:
Two important FD-SOI wins for STMicroelectronics have just been announced:
The Energy Technology Award was presented at a ceremony for the 2013 Annual Creativity in Electronics (ACE) Awards. It is given by EETimes and EDN, two of the most prominent trade-media sources in electronics. The ACE Awards honor the people and companies behind the technologies and products that are changing the world of electronics and shaping the way we work, live, and play.
Why the energy category? ST attribututes it to FD-SOI’s ability to reduce energy consumption and carbon emissions in two important ways. First, manufacturing FD-SOI is simpler and requires 15% fewer process steps than equivalent traditional silicon technologies and far less than complex alternatives to achieve similar performance, thereby using less energy per wafer produced. Moreover, products manufactured using FD-SOI technology show energy savings between 20 and 50%, making end-user devices run cooler and last longer.
Commenting on the award, Executive Vice President of Front-End Manufacturing & Process R&D, Digital Sector Joel Hartmann said, “The Energy Technology Award confirms that FD-SOI is a game-changing technology that addresses the low-power and high-performance needs of the market. It also empowers chipmakers to deliver products meeting the dual benchmark of industry-beating “performance per watt” and “performance per watt per dollar.”
And of course, ST’s FD-SOI is ready for manufacturing now: it’s a faster, simpler and cooler upgrade to traditional semiconductor manufacturing at process nodes of 28nm and below.
Which is why we’re now starting to hear about customers! Here’s what they had to say at their Q1 2013 Results – Earnings Call (the transcript was just posted on Seeking Alpha).
“In Digital Convergence, I’m pleased to say we earned important design wins in the FD-SOI advanced CMOS technology, the next-generation process technology that ST is pioneering,” said Carlo Bozotti, Chairman of the ST Managing Board, CEO and President in his opening remarks.
In a follow-up question from a BNP Paribas analyst, he added, “On the FD-SOI, we are working very aggressively on two fronts. The first front is communication infrastructure. We believe this is an area where the value of lower power dissipation for the same processing power / performance is important. Sometimes it is very important. And we have won the first project for this kind of application. However, there is another target area that is portable equipment, but not necessarily smartphone. There are other, I would say, great opportunities and some of these are really important opportunities that are outside the smartphones and outside the tablets, but they are very important opportunities. And, hopefully, we will have some more good news in the near future.”
Asked if it could be licensing revenues, he replied, “This is something that is possible.”