Tag Archive foundries

ByAdele Hars

FD-SOI in China – Foundries See Interest Mounting Fast

The foundries sent their top guns to the FD-SOI Forums organized by the SOI Consortium and its members in Shanghai and Nanjing. This is a quick recap of what they said.

GF: Winning with SOI

“With FD-SOI, we can deliver a level of integration never before possible,” said GlobalFoundries CEO Sanjay Jah in his Shanghai talk, Winning With SOI. The ecosystem they’re building is covering both design and supply. He showed a video of the new fab, which is going up at an enormous speed in Chengdu, China. It’s huge: a half-kilometer long on one side. And it will start producing wafers in H218, ramping up to a million/year.

GlobalFoundries CEO Sanjay Jah citing key TAMs at the FD-SOI Forum in Shanghai. (Photo courtesy: SOI Consortium & GlobalFoundries)

FD-SOI is past the discovery phase now, he continued. They’ve got 135 engagements and 102 PDKs downloaded. In China alone, they have ten customers taping out 15 products. The key is going after high-growth markets, including mobility, IoT, RF/mmW and automotive (see picture above). “We see intelligence migrating to the edge,” he said.

With 22FDX®, there are 11 fewer mask steps than industry standard 28nm HKMG processes, he said. Back bias is a big differentiator, reaping benefits without penalties and shortening time-to-market. eMRAM is also a big driver of interest. The IP – both foundation and complex – is silicon-proven: you can measure it. The FDXceleratorTM program now has 35 partners.

He also touched on RF-SOI, where GF is #1 in terms of market share.

“I’m very excited about the future for us,” he concluded.

With back bias, you can do even more, said GF’s Sanjay Jha, so customers feel the risk is lower. (Photo courtesy: SOI Consortium & SOI Consortium)

In the Nanjing SOI forum, GF’s head of China sales, Zhi Yong Han gave an excellent presentation that is posted on the SOI Consortium website (you can get it here). He emphasized that they are educating designers to help them take advantage of the FD-SOI for advanced devices, as well and working with universities. The result is that they’re seeing significant growth in the Chinese market.

Slide 9 from GF’s Nanjing presentation shows all the boxes ticked: 22FDX® is qualified for volume production. (Courtesy: GlobalFoundries and the SOI Consortium)

Zhi Yong Han also highlighted the excellent performance of GF’s RF-SOI offering, and the huge capacity they’re building out. NB-IoT clients are now approaching them, he added.

Samsung: World’s 1st eMRAM Test Chip

“E.S. stands for Engineering Sample,” quipped Dr. E.S. Jung, EVP/GM of the foundry business for Samsung Electronics. A very energetic speaker, his talk covered Cutting Edge Technology from a Trusted Foundry. (Samsung Foundry is now a standalone business unit.)

Samsung has seven major 28nm FD-SOI customers, and has taped out over 40 products. This coming year a number of products will be taking off in mass production, he said.

eMRAM (which only required three additional mask steps) is the newest addition to the family of embedded non-volatile memories and it offers unprecedented speed, power and endurance advantages (see the press release here).

Regarding back bias in the IP, he said they’ve solved it working with their suppliers, EDA vendors and customers. Migrations will re-use that IP.

At the Nanjing SOI forum, VP of Samsung Foundry Suk Won Kim looked at design methodology in his talk, 28FDS Samsung Foundry Platform. It’s easy to implement your SoC with FD-SOI technology, he said, explaining how PPA and cost/transistor makes 28FDS an optimal node. The PDK – including RF – are ready for high volume production. There is no design overhead: the differences between FD-SOI and bulk are not difficulties, he emphasized.

For 28FDS, the full spectrum of the ecosystem is available: design enablement, advanced design methodologies, and silicon-proven IP. Samsung has a body bias generator, and the design methodology takes care of checking the body bias integrity. In terms of the physical design, there is awareness in the floorplan for body biasing and flip-well devices. In terms of timing sign-off, there’s almost no change – in fact there are fewer PVT corners. The flow for power integrity sign-off doesn’t change. The RTL-to-GDS flow is about the same – and where they diverge, designers are embracing the differences.

And for those looking ahead, the PDK for 18FDS evaluation will be available soon.

More pics?

For pics of many more slides, check out articles posted about the SOI forums in the China press, including EETimes China, EEFocus, and EDN China (plus see their focus piece).

BTW, there were five days of events in Shanghai and Nanjing, with over 50 presentations  given in ballrooms full-to-bursting. As noted in my previous post, China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth, many (but not all) of the presentations are now available  in the Events section here on the SOI Consortium website.

So in future posts, we’ll cover the EDA/IP companies, design tutorials and user presentations for both the FD-SOI and RF-SOI China events — including those not posted. Stay tuned!

ByAdele Hars

China FD-SOI/RF-SOI Presentations Posted; Events Confirm Tremendous Growth

The FD-SOI and RF-SOI events in Shanghai and Nanjing were absolute success stories. Over the course of five days, hundreds of executives and design engineers packed halls for talks by the leaders of the top ecosystem players, and for tutorials given by the world-renowned design experts.

These annual events have been ongoing in China now for a few years now. Citing the tremendous growth of SOI, Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Science in Shanghai said in his keynote, “We’ve come a long way.” Five years ago, he recalled, very few people in China even knew what SOI was. Today the central government has recognized its value, and the ecosystem is riding a wave of growth and strength. A national industrial IC group has been approved for investment, and design/IP are ready. The industry has reached a consensus, he said, that FD-SOI is cost-effective and complementary to Finfet, while RF-SOI has reached an almost 100% adoption rate in front-end switches for mobile phones.

Dr. Xi Wang, DG of SIMIT and head of the Chinese Academy of Sciences in Shanghai giving a keynote address at the 5th Shanghai FD-SOI Forum. (Photo courtesy: Simgui and the SOI Consortium)

Many of the presentations are now publicly available on the Events page of the SOI Consortium website. Here are the links:

(Photo credit: Adele Hars)

Over the next few weeks, I’ll cover the highlights of each of these events. Their success clearly represents a tremendous vote of confidence for the SOI ecosystem in China and worldwide.

The success of these SOI events is a testament to China’s recognition of the great opportunity of SOI-based chip technologies. FD-SOI decreases power consumption and enables deep co-integration of digital, analog, RF, and mm-wave. RF-SOI enables 4G and 5G connectivity with even richer integrated functionalities. It allows the fusion of the RF switch, LNA, and PA, for supporting both traditional sub-6GHz but also mm-wave frequency ranges. SOI technologies also offer a means for China – already the world’s largest chip consumer – to leap to the forefront of chip design and manufacturing,” noted Giorgio Cesana, Executive Co-Director of the SOI Consortium.

The events were followed by top tech news outlets in China. Links follow below (the pieces are in Chinese; or you can open them in Google Translate or Chrome to read them in the language of your choice). Tip: in these pieces you’ll find lots of great pics of key slides, including some that have not been shared on the Consortium website.

FD-SOI coverage included pieces in top pubs such as EETimes China, EEFocus, EDN China (plus a focus piece) and Laoyaoba to name a few. Leading bloggers also posted excellent overviews as well as pieces about specific presentations, including those by Samsung, GlobalFoundries and Handel Jones.

RF-SOI coverage included pieces in leading publications such as China IC, EETimes China, EDN China, EEFocus and SemiInsights.

ByAdele Hars

GF Triples FDXcelerator Partner Base in 1st Year

As of September 2017, GlobalFoundries’ FDXcelerator program now counts 21 members. Its purpose is to extend the reach of the FD-SOI ecosystem, creating an open framework that allows these selected partners to integrate their products or services into a validated, plug-and-play catalog of design solutions. The program was first launched with seven partners in September 2016 – so membership has already tripled in just one year.

As such, FDXcelerator delivers design elements (IP), platforms (ASIC), tools (EDA), reference solutions (reference designs, system IP), resources (design consultation, services), and product packaging and test (OSAT) solutions that enable GF’s customers to improve FD-SOI-based SoC development cycle times and minimize development costs.

The program was originally founded with Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services).

Partners that have joined since then include:

QuickLogic — mass production proven ultra-low power embedded FPGA; complete SW support for FPGA design and SoC integration in 22FDX ultra-low power embedded FPGA (eFPGA) Intellectual Property, complete software tools and a compiler (press release here).

ASE Group — advanced packaging, assembly and test development services. Chip scale package types to include: flip chip and wafer level Fan In and Fan Out.

Amkor Technology — advanced packaging, assembly and test development services. Package types to include flip chip, wafer level fan out and wire bond.

Infosys — Silicon-to-systems range of engineering services. Software services ranging from various firmware, embedded and applications-specific offerings.

Mentor Graphics — FDX-tailored Calibre™ solutions for timing and physical verification. Mentor ICD to support, floor planning, synthesis, place & route capabilities and Tessent™ suite to offer DFT flow support (press release here).

Rambus — Cryptofirewall cores that complement security implementations; DPA counter measure solution offerings to enhance security measures (press release here).

Sasken — Software solutions and processes for IoT, automotive and industrial and emerging device technologies. Offer turnkey solutions including hardware and software for complete SoC production.

Sonics — EPU™ Studio based on the Sonics ICE-GRAIN™ power architecture to support body-bias. Configurable on-chip network suite of offerings to support design of complex on-chip interconnects between cores (press release here).

Attopsemi — proprietary I-fuse™ OTP IP provides small size, high reliability, low program voltage, low power and wide temperature range to enable harsh applications such as automotive, 3D IC, and IoT applications (more here).

Fraunhofer IIS — applied research and development for ASIC, system-on-chip (SoC), and IP. Offers dynamic biasing IPs for advanced SoC designs in 22FDX technology.

Racyics — IP and design services for 22FDX process technology. “makeChip” design service platform provides an IT infrastructure with EDA tools and technology data setup (press release here).

Perceptia — all-digital PLL IP and complementary design solutions for 22FDX. Custom IC design and physical implementation services for GF FD-SOI process technologies (press release here).

eVaderis — optimized eNVM and processor subsystems IP for non-volatile IoT SoCs. Advanced IP for efficient code and data management in ultra-low power designs (press release here).

Uniquify — DDR Interface IP provides the right power, performance, area and reliability for FDX™-based SoCs in portable applications. Memory interface IP employs industry-leading adaptive technology, based on 14 issued patents, to deliver maximum performance (press release here).

ByAdele Hars

Samsung Certifies Synopsys Custom Design Platform for 28nm FD-SOI

Custom Compiler visually-assisted automation flow. (Courtesy: Synopsys)

Synopsys’ custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology. The certified Synopsys custom design platform includes HSPICE® golden-accuracy circuit simulation, Custom Compiler visually-assisted layout automation, StarRC gold-standard parasitic extraction and IC Validator scalable physical signoff. The Synopsys custom design platform provides improved custom and mixed-signal design productivity for Samsung 28FDS users designing for various low power required applications such as IoT, connectivity, mobile computing and automotive. (Read the full press release here.)

“Samsung Foundry’s certification of Synopsys’ custom design platform is important to our mutual customers developing complex designs,” said Bijan Kiani, vice president of product marketing at Synopsys. “Through close collaboration, we have delivered a certified custom tool suite and accompanying iPDK to enable our mutual customers to improve their custom layout and circuit simulation productivity.”

Custom Compiler’s user-guided symbolic editing technology accelerates 28FDS device placement. It includes interactive custom routing technology that can quickly create DRC-correct routing, thus reducing late-stage physical signoff iterations. The combination of placement and routing assistants in the Custom Compiler solution cuts 28FDS layout effort by up to 30 percent. Custom Compiler support for these advanced features is provided through a jointly developed 28FDS PDK in the industry-standard interoperable (iPDK) format.

“Samsung Foundry’s 28FDS delivers lower design cost, lower total power and better analog performance, making it suitable especially for low power driven applications such as IoT and connectivity,” said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics. “We worked with Synopsys to certify Synopsys’ custom design platform for our 28FDS process technology to enable our customers to accelerate their custom design development.”

ByGianni PRATA

GF’s New RF-SOI PDK Simplifies Design for Smartphones, IoT

GFrfsoi-icon-newGlobalFoundries recently announced availability of a new set of RF-SOI PDKs for the company’s 7SW SOI technology. GF, which has now delivered more than 20 billion RF-SOI chips for the world’s smartphones, tablets and more, notes that its 7SW SOI technology is optimized for multi-band RF switching in next-generation smartphones. It is also poised to drive innovation in IoT applications.

The new PDKs feature an interoperable co-design flow to help chip designers improve design efficiency and deliver differentiated RF-SOI front-end solutions in increasingly sophisticated mobile devices. (See press release here.) The new PDKs are designed to use with Keysight Technologies’ (formerly Agilent) Advanced Design System (ADS) EDA software, so designers can edit their designs in ADS using a single Si2 OpenAccess database without any interference.

“Our 7SW platform, with superior LNA, switch devices, and trap-rich substrates, offer improved devices reception, interference rejection, and battery life for fewer dropped calls and longer talk time,” said Peter Rabbeni, senior director of RF product marketing and business development at GlobalFoundries. “Our RF-SOI technology has gained significant industry traction for cellular front-end module applications, and the new RFIC interoperability feature will allow us to provide our 7SW customers additional design flexibility with a single PDK.”

ByAdministrator

Silicon Valley FD-SOI Symposium Promises Best Ecosystem Line-Up Ever: ARM, Foundries, EDA, Designers, Experts & Users (13 April – free and open to all who sign up)

The SOI Consortium has lined up an excellent, comprehensive FD-SOI Symposium on April 13th in San Jose. They’ll be highlighting the tremendous progress of the FD-SOI ecosystem. Headliners include Cisco, Sony, NXP, SigmaDesigns, ARM, Ciena plus the big FD-SOI foundries, EDA companies, design partners, chipmakers and analysts. There is a special session dedicated to RF and analog design innovation on FD-SOI with STMicroelectronics, Stanford and others. In short, we’re going to get a chance to see the FD-SOI ecosystem in action.

To attend, all you have to do is register in advance – click here to go to the registration page. It’s free and open to everyone who registers.

FDSOI_SanJose13Apr16It’s really a terrific agenda – check it out:

08:00AM – 09:00AM – Registration

08:55AM – 09:00AM – Welcome by Carlos Mazure, SOI Consortium

09:00AM – 09:30AM – Aglaia Kong, Cisco Systems, CTO for Internet of Everything

09:30AM – 10:00AM – Thinh Tran, Sigma Designs, CEO

10:00AM – 10:30AM – Ron Martino, NXP, VP, Application Processors & Advanced Technology Adoption

10:30AM – 10:50AM – Coffee Break

10:50AM – 11:20AM – Subramani Kengeri, GLOBALFOUNDRIES, VP CMOS Business Unit

11:20AM – 11:50AM – Will Abbey, ARM, GM Physical IP

11:50AM – 12:20PM – Kelvin Low, Samsung Semiconductor, Senior Director, Foundry Marketing

12:20PM – 1:40PM Lunch

1:40PM – 2:10PM – Kenichi Nakano, SONY, Sr. Manager, Analog LSI Business Division

2:10PM – 2:40PM – Dan Hutcheson, VLSI Research, CEO

2:40PM – 3:05PM – Mahesh Tirupattur, Analog Bits, EVP

3:05PM – 3:30PM – Mike McAweeney, Synopsys, Sr. Director, IP Division

 

3:30PM – 4:00PM – Coffee Break

4:00PM – 4:30PM – Naim Ben-Hamida, Ciena, Senior Manager

4:30PM – 4:55PM – Rod Metcalfe, Cadence, Group Director, Product Engineering

4:55PM – 5:20PM – Prof. Boris Murmann, Stanford, on “Mixed-Signal Design Innovations in FD-SOI Technology”

5:20PM – 5:45PM – Frederic Paillardet, STMicroelectronics, Sr. Director, RF R&D

5:45PM – 6:00PM – Ali Erdengiz, CEA-LETI, Silicon Impulse

6:00PM – 6:05PM – Closing remarks by Giorgio Cesana, SOI Consortium

Seriously – this good. Plus during breaks you’ll want to check out the poster sessions with GSS, sureCore, Soitec, SEH and the SOI Consortium.

Please note that if you’ve already registered last month when the first announcement went out, the location has changed. The SOI Consortium FD-SOI Symposium will be held on Wednesday, 13 April 2016, from 8am to 6:30pm at the:

Doubletree Hotel San Jose

2050 Gateway Place

San Jose, California 95110, USA

If you can’t make it, not to worry – ASN will be there taking notes for a round-up and follow-up articles. Plus we’ll be tweeting and retweeting (follow us on Twitter at @FollowASN and @AdeleHars – look for the hashtag #FDSOI). And of course you’ll want to follow the Twitter feeds of participating companies, and of the SOI Consortium @SOIConsortium.org. logo_soiconsortium

ByAdministrator

Synapse Design CEO Interview: Designs Taping Out for Very High-Volume 28nm FD-SOI SOCs, Production in 2016

SatishBagalkotkar_outside

Satish Bagalkotkar, CEO of Synapse Design, is very optimistic about FD-SOI.

ASN spoke recently with Satish Bagalkotkar, the CEO of Synapse Design, which he co-founded with Devesh Gautam in 2003. With 800+ employees, the firm designs chips for the biggest companies in the industry. He’s very optimistic about FD-SOI. Here’s why.

Advanced Substrate News (ASN): How long has Synapse Design been working in FD-SOI? What sorts of projects have you done?

Satish Bagalkotkar (SB): We have been working on FD-SOI since 2010. We have been involved in four tape-outs so far and are working on three more now, so we’ll be at seven tape-outs by the end of this year. They are in several different sectors.

ASN: Are you getting more inquiries (and business) lately? In what areas (both in terms of types of chips and geographically)?

SB: We are engaged in negotiations with several Asian clients representing multiple market segments and are helping large US companies migrate next generation products to FD-SOI.synapse_logo_300_ppi

ASN: At what point in the design process do you typically come in? What sorts of services do you offer?

SB: Our customers are among the largest system and semiconductor companies in the world in any given sector – mobile, storage, multimedia, IoT, automotive and networking. In any of these areas, we are working with the top two or three customers. Of the 35 SoCs we completed in 2014, one-third was done from specification to GDSII; in another third, the majority of engineering was completed by us; and the final third was staff augmentation. We engage anywhere from developing the specification to complete product design including firmware and device drivers. However, we don’t deal with the production of the chips.

ASN: What do you see as the advantages of FD-SOI?

SB: The key advantage is the flexibility to optimally tune for power and/or performance. We did analysis for one customer showing that with FD-SOI they could increase performance by 25% at the same power, or decrease power by 25% and get the same performance. Those are big numbers. In battery operated IoT, for example, where battery life might be one-to-two years, getting 25% more battery life without compromising on performance – that’s huge.

SynapseDesign_FDSOI_v_bulk

An example of a PPA study Synapse Design did for a client, showing the relative advantages of FD-SOI vs. bulk at 28nm for performance, power, area and power consumption. Note that in this case, there is no forward body bias (FBB), so it is an apples-to-apples comparison. If the FD-SOI were to be implemented with FBB, the performance/power advantages would be expected to be be even greater. (Courtesy: Synapse Design) Click to enlarge.

We help our customers understand the potential advantages of any technology by analyzing the product requirements and then decide which technology is most effective taking into account the client’s requirements. To increase client confidence, sometimes we may take one of their previously taped-out designs and complete a power-performance-area study using their data and demonstrate to them the differences. Typically, we do several iterations, and then we might say, for example, “Hey, in this run you can get 25% better power, or 30% more performance,” and show them the spectrum of advantages on their own design. Once we show the numbers, it becomes an engineering decision based on facts, not just on trust. Once they agree on it, and say, “Yes, this makes sense,” we deep dive into their new projects. We can take a specification and carry it through to a device, or we can take a chip that’s already in mass production, and show the ROI of each approach.

ASN: Designers of what kinds of chips should be thinking about FD-SOI?

SB: Any product working at low voltage and low-power without comprising on performance or vice versa would definitely benefit a great deal. The biggest area from my perspective is IoT devices to improve battery life. These are simple devices with sensors that export limited data, so the battery has to last a year or multiple years. Also, FD-SOI has time-to-market advantages over many new technologies because it shares most of the same devices as Bulk process. Synapse Design has developed a methodology easy design porting to FD-SOI.

ASN: Why do they ultimately choose it? Why do they hesitate?

SB: They choose it because of the power-performance-area numbers. We’re looking at apples-to-apples comparisons, using the same design on same node. We’ve done this for customers, and we’re happy to do it for anyone who’s interested. Hesitations include: First, there’s not a single device in high volume production so there’s no proof of technology maturity; second, the ecosystem is not built-up; and finally, the costs are not yet where they need to be. With more foundries supporting FD-SOI, these things should be addressed.

ASN: Are there special considerations designers should think about before starting a project in FD-SOI?

SynapseDesign_FDSOI_diffSB: Switching to FD-SOI is not trivial and it’s important to partner with knowledgeable professionals who’ve practiced with several designs. I like to use the example of a car. In an automatic, everything is in place. But FD-SOI is like a manual shift car with a lot of knobs: to get the performance or save power you need know what you are doing. We’ve worked through 35 SOCs for the largest system and semiconductor companies worldwide – the full spectrum, from high-performance to very low-power devices. Oftentimes, a customer says, “OK, I want to use xyz technology.” We say, “Why?” “Because we need that performance.” So we look at the business case. What are the volumes, mask cost, performance, power and area requirement plus availability of the IPs etc. Then compare all options and make a decision. It’s all about ROI – we do a lot of these exercises for our clients. We tapeout several SoCs every month so can bring value to this discussion. We can generate those numbers with actual data – not just hypothesis.

ASN: Some have said body-biasing is difficult — does this concern your customers? Do you find that to be the case?

SB: Not if you have experience in this technology. It is important to have a clear plan on what you want otherwise you will waste too much time doing what-if analysis and not get the desired output.

Body Biasing (either reverse or forward) adds flexibility but also complication to the design. It requires closing timings at different corners, but it also requires learning how to adjust the bias based on the process or process/temperature corner the device is working at, which means support from the foundry, but also a good internal engineering department to optimize the strategy in production.

ASN: Between 28nm FD-SOI and 14nm FinFETS, is the choice always clear? What about 14nm FD-SOI?

SynapseDesign_FDSOI_summarySB: We’ve already done five 14nm FinFET chips, so we also know FinFETs well. But in terms of a business case, 14nm FinFETs are appropriate for a few companies who are targeting high-performance products expected to achieve ultra high volume. Many products may not need that level of performance or don’t have such high volume to support the cost. 28 nm FD-SOI might be more appropriate for IoT devices or anything that could benefit from low-power while maintaining a similar performance level. Regarding 14nm FD-SOI, we are working with a customer on a 14nm test chip, but this will take time to be available for the general market

ASN: Are you optimistic about FD-SOI based design gaining traction in the short-term? In the long-term?

SB: Yes, as long as the challenges of “proof” (volume production), a rich eco-system and cost are addressed quickly before other competing technologies become readily available. This technology definitely has merit for the long term as 28nm is here to stay for a few years.

ASN: Everyone wants to hear about high-volume FD-SOI chips hitting the street — do you see that happening? When?

SB: We will see high-volume chips from early adopters in 2016, however, the industry at large will lag as they wait to see how early adopters fare. In the meantime, we’ve actually invested in a 28nm FD-SOI chip ourselves – a chip that will be in high-volume in 2016.

We think there’s enough value and opportunity to take that risk. Devices in high-volume should set the stage for fast followers, and give the industry at large the remaining proof points to fully evaluate the merits of the FD-SOI business case.

~ ~ ~

Synapse Design is an industry leader in design services and is the engineering backbone of most top tier Semiconductor and System companies around the world. Synapse Design target customers are companies with $5+ billion in revenue, and enabling them to meet their technical & resource challenges to build the next generation products. Founded in 2003, the company is headquartered in San Jose (Silicon Valley) with operations all over US, China, Europe, Taiwan, Singapore, Vietnam and India. Synapse Design has over 800 employees around the globe and is aggressively growing. For more information, see www.synapse-da.com.