Tag Archive FPGA

Start-up SoCs on FD-SOI – Final Highlights from the Silicon Valley SOI Symposium (Part 3)

Some really innovative start-ups presented chips they’re doing on FD-SOI at the SOI Consortium’s 2018 SOI Symposium in Silicon Valley. We’ll cover those here in Part 3  of ASN’s coverage, as well as a presentation on China by wafer-maker Simgui and the final panel discussion.

BTW, if somehow you missed my coverage of the morning sessions about very cool new products and projects from NXP, Sony, Audi, Airbus and Andes Technology, be sure to click here to read it. And in the afternoon the foundry partners provided excellent insight into who’s designing chips on FD-SOI, and VLSIresearch explained why. You can read that here.

Some of the presentations are posted on the SOI Consortium Events page – but some won’t be. Either way, I’ll cover them here.

Start-ups

Ineda Systems began as an ADAS start-up, and are now working on developing low-power SoCs for use in consumer and enterprise applications. They’re using FD-SOI for their current family of chips. SVP Ramkumar Subramanian emphasized that NRE costs are really important for smaller designs. 22FDX, he said, enabled them to move from 40nm, and ramp to larger volumes.

In February, GreenWaves Technologies, a fabless semiconductor startup designing disruptive ultra-low power embedded solutions for image, sound and vibration AI processing in sensing devices, announced its GAP8 IoT application processor. GAP8 evaluation boards can now be ordered. The GAP8 agile power management architecture combined with IOT low duty cycling is a perfect fit for FDSOI processes. CEO Loic Lietar talked about how it would be used in AI applications at the very edge, wherein only the necessary data should be uploaded to the cloud.

Also in February, Dream Chips’ announced that its ADAS SoC fabbed in GlobalFoundries’ 22FDX (FD-SOI) technology was posting record power efficiency (you can read more about it in ASN’s coverage at the time here.) Dream Chips is Germany’s largest independent Engineering Service Provider. At the symposium, CEO Jens Benndor’s talked about their roadmap.

(Courtesy: eVaderis, SOI Consortium)

eVaderis CEO Jean Pascal Bost talked about how data-intensive IoT applications are enabled with FD-SOI and embedded magnetoresistive non-volatile memory (eMRAM) technology. You can get the slides from his talk here. eVaderis has eflash-like and eSRAM-like eMRAM IP that covers most MCU applications. They also have an eMRAM compiler tool and high-value-added IP for 22FDX. They foresee impressive power savings at the system level with body biasing: 25x this year and up to 45x in 2020, so that intelligence can be brought to IoT. In February they announced that they are co-developing an ultra-low power MCU reference design using GF’s eMRAM technology on the 22FDX® platform. And in March eVaderis and Mentor/Siemens announced that eVaderis proprietary Magnetic Tunnel Junction (MTJ) model would be co-optimized with AFS to speed-up simulations and generations of embedded MRAM IPs and compiler products with good accuracy.An 22FDX MCU reference design project is underway, with tape-out in July ’18.

Reduced Energy Microsystems (REM) CEO William Coven talked about realizing near-threshold computing with 22FDX and low-power memories. REM has two products on 22FDX: their Neuron Vision SoC and 64-bit RISC-V IP cores. 22FDX, he says, has been fantastic.

Simgui

Jeffrey Wang, the CEO of wafer-maker Simgui looked at why China is promoting its IC industry. (In the SOI ecosystem, Simgui is particularly known for its RF-SOI wafers, which it produces using Soitec’s Smart CutTM process.) This was more of an overview talk, not necessarily specific to the SOI ecosystem, but certainly interesting.

In terms of worldwide semiconductor sales, he said, about half end up in China. The CICF – aka the Big Fund – is currently running at about $74 billion. Having realized that mergers & acquisitions would not solve the problem, they’ve opened a second round, targeting another $160 billion.

China’s two biggest innovation success stories are Huawei (with its Kirin processor), and China Rail, which is now a global Fortune 500 company. The CAGR for the China semiconductor industry is 19%, though they need 20% to reach their goals.

IC design is a particularly successful area, posting a CAGR of 29%, with two players in China in the top 10 worldwide. Packaging and assembly/test are also very strong. Zing is working on increasing the supply of 300mm silicon wafers, while Simgui is expanding in both 200 and 300mm capex, due to “big demand”, he said.

Panel Discussion

SOI Symposium Panel Discussion: (left to right): Giorgio Cesana (Co-Director SOI Consortium), Dave Eggleston (VP GF), Tim Saxe (CTO, Quicklogic), Wayne Dai (CEO, Verisilicon), Samir Patel, (CEO Sankalp Semi), Kelvin Low (VP, ARM), Mahesh Tirupattur (EVP, Analog Bits)

The day wrapped up with an excellent panel discussion moderated by SOI Consortium Executive Co-Director Giorgio Cesana. Here are a few of the observations made by the panelists.

QuickLogic CTO Tim Saxe said that FD-SOI made their designs more compact. With FD-SOI for FPGAs, you’ve got one set of IP, and you can decide at runtime where you’re going for low power or high performance. With a lot of power domains, you see the benefits at the system level.

GF VP Dave Eggleston said they’re seeing early adopters of eMRAM, especially for wearables with RF and low power.

ARM VP Kelvin Low said people should do more than just migrate to FD-SOI. If they use back biasing, it can replace the need for big/little cores.

Body biasing makes things easier, maintained Verisilicon CEO Wayne Dai. His teams find that with body biasing, you can tape out for “typical” instead of “worst case”.

It’s not too late for FD-SOI: it’s perfect timing for the MCU market, which is still at 40nm, said Sankalp Semi CEO Samir Patel. As designers, they’re happy to focus on companies still on the older nodes.

The IP ecosystem should be more enthusiastic about FD-SOI, said Analog Bits EVP Mahesh Tirupattur. You’ve got more potential customers, and your volume runs can be bigger.

In his closing remarks, SOI Consortium Executive Co-Director Carlos Mazure reminded the audience of the day’s three take-aways:

  1. power consumption is driving even systems companies
  2. FD-SOI is penetrating fields like MCUs and SoCs where more intelligence is needed
  3. China is still a really big opportunity.

Press Heralds Lattice Semi’s Move to FD-SOI

The press is heralding Lattice Semi’s move to FD-SOI for all its new products. Recent articles in EE Journal, ElectronicsWeekly and eeNewsAnalog see it as a very savvy move.

As noted on the Lattice website, their business is to provide “… smart connectivity solutions powered by our low power FPGA, video ASSP, 60 GHz millimeter wave, and IP products to the consumer, communications, industrial, computing, and automotive markets worldwide.” And at their last Analyst and Investor Day, Lattice CEO Darin Billerbeck did a brilliant job explaining their strategy of targeting the “new edge”, where IoT devices really live.

Slide from Lattice Semiconductor 2017 Analyst & Investor Meeting. (Courtesy: Lattice Semi)

At EW, David Manners talked to Lattice COO Glen Hawk, who told him they’re moving all their new products to 28 nm FD-SOI over the next couple of years. Manners says they benefit from the “…flexibility, low-power and low-cost of FD-SOI”. (Read the full article here.)

A Lattice spokesperson told Peter Clarke at EENewsAnalog that, “Lattice will be migrating to 28 nm FDSOI for new products, which we believe will enable us to achieve 10x lower power with the highest performance devices for edge connectivity and edge computing applications. Existing products will remain on their existing nodes and foundries.” (Read the full article here.

And over at EE Journal, Kevin Morris spent a day at Lattice. Rather than copy the traditional FPGA companies that are going for the high end with advanced FinFET processes, he explains, “Lattice uses FD-SOI processes to milk out the most performance possible with the tiniest power budgets and lowest device cost.” The result he predicts is that, “Lattice will own the edge where pennies and millimeters and microwatts are at a premium.” (Read the full article here.)

FD-SOI Opportunities in China

Authors: Zhongli Liu, Kai Zhao, Jiajun Luo, Fang Yu, Tianchun Ye (IMECAS)

The Chinese IC industry is facing a real opportunity, and Chinese IC developers are looking for points of entry to best leverage this important moment.

The CTO of a large Chinese IC supplier is looking for system solutions for their SOC chips, in order to obtain the advantages of ultra-low power consumption and ultra-high electrical performance. It is expected that the establishment of a national R&D center for the Internet of Things will be announced soon.  Smart chips based on RF technology will be one of the main solutions to the Internet of Things.

Not long ago, the Chinese government issued 4G licenses. It is believed that in the next three years fierce competition will happen in the Chinese communications market. In addition, for the general chips like CPU/DSP/FPGA, it is very difficult to catch up or surpass the international leaders without the introduction of disruptive technologies. According to IBS forecasts [1], as shown in the following figure, the Chinese IC market will be increased from $100 billion in 2013 to about $200 billion in 2018. And all the above will contribute to this remarkable growth.

IC Market by Geographic Region (012814)

 (Source and courtesy of: International Business Strategies, Inc.)

Every time, when the world is in controversy over different advanced technologies, China is always willing to be independent and make our own choices, as we’ve seen recently in the Chinese communications market with the TD-LTE and FDD-LTE options [2]. Therefore, new ideas such as advanced FD-SOI platform technology are needed to be able to help Chinese IC developers to fully realize the potential of this golden opportunity.

The Institute of Microelectronics, Chinese Academy of Sciences (IMECAS) is one of the main promoters of SOI technology in China. (For an overview of IMECAS, click here.) Mass memory chips based on SOI technology have already begun shipping to end customers. The 300K system-gate FPGA chip [3] based on FD-SOI technology has also completed the final test, and eighty percent of the static power consumption is reduced compared with the same type of FPGA on a bulk substrate. In addition, IMECAS is planning to set up a new platform based on an advanced FD-SOI technology to design reconfigurable SOC chips, and lay the foundation for the new era of IC industry in China.

TableFDSOI_China14

In order to promote FD-SOI development in China, research institutes, technology providers and chip design companies are needed to form a tight alliance, to promote international cooperation, and jointly to create a suitable eco-environment for this advanced technology to thrive. [4]

CirclegraphicFDSOI_China14TreegraphicFDSOI_China14

References:

[1] Interactive presentation on key trends for advanced technologies and role of SOI, by Handel Jones from IBS, http://www.soiconsortium.org/fully-depleted-soi/presentations/october-2013/.

[2] TD-LTE: gearing up to cover 2.7bn people in Asia by 2013, Global Technology Equity Research by The Goldman Sachs Group, Inc., at 2011.

[3] A Low Power and Radiation Tolerant FPGA Implemented in FD SOI Process, Lihua Wu et al., Proceedings of IEEE S3S Conference, Oct. 2013.

[4] FDSOI Applications and Opportunity in China, by Zhongli Liu from IMECAS, http://www.soiconsortium.org/fully-depleted-soi/presentations/october-2013/.

 

With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling.

With the upcoming Hybrid Memory Cube (HMC) from Micron et al, SOI becomes an integral part of 2.5D and 3D stacks, notes SemiMD’s Ed Sperling. “The logic base layer—in this case made by IBM—uses an SOI substrate,” he explains, “…even if some of the other pieces use different materials.” He goes on to say that while the next-gen HMC enters production at the end of next year, in the meantime the existing HMC architecture can be attached to FPGAs, either in a vertical stack or in a 2.5D configuration. “Having an additional layer of insulation is a bonus in that architectural arrangement, as well, to buffer against a variety of physical effects ranging from noise to heat.”

Want Silicon Proof? Check Out the Fully-Depleted Tech Symposium During SF/IEDM

If you want to cut through the noise surrounding the choices for 28nm and beyond, an excellent place to start is the SOI Consortium’s Fully Depleted Technology Symposium.

As a member of the design and manufacturing communities, this is your chance to see and hear what industry leaders are actually doing. Planar? FinFET? The Consortium’s been doing these symposia during major conferences for going on four years now, and lively debates always ensue.

Hilton San Francisco Financial District

(Courtesy: Hilton Hotels & Resorts)

This next FD Tech symposium happens the first day of the IEEE’s IEDM conference in San Francisco – Monday, December 10th at 8:15pm. Conveniently, it’s also taking place in the same building – at the SF Hilton.

Top technologists from STMicroelectronics, ST-Ericsson, IBM, ARM, Altera, LETI, Soitec, MEMC and others will be debating comprehensive Fully-Depleted Technology solutions.

But perhaps most importantly, we’re going to get the first product-level benchmarking results of 28nm FD-planar for mobile SoC and FPGA applications.  That’s silicon proof straight from the companies who are doing it.

If you’ve been following recent ASN postings from STM, ST-Ericsson, IBM and others, you know these folks are really excited about the results they’re seeing.

Here’s a peak at the presentations planned for the symposium:

  • Planar Fully-Depleted Technology at 28nm and below for extremely power-efficient SoCs:  SoC level 28nm Planar Fully-Depleted silicon results
    By Joel Hartmann, Executive VP Front-End Manufacturing & Process R&D, STMicroelectronics
  • Evaluation and benchmarking of 14nm planar Fully-Depleted Technology for FPGAs
    By Jeff Watt, Ph.D. Fellow, Technology Development, Altera Corporation
  • Challenges and comparisons of designing power-efficient SoCs with planar Fully Depleted transistors and FinFETS
    By Rob Aitken, ARM Fellow
  • Second-generation FinFETs and Fin-on-Oxide
    By Ed Nowak, IBM Distinguished Engineer and Device Chief Designer, Semiconductor R&D Center, IBM Systems and Technology Group

The presentations will be followed by a Q&A.

Admission is free, but space is limited, so you must reserve in advance – click here to go to the special registration site.

To recap, it’s the:

Fully-Depleted Transistors Technology Symposium
Hilton San Francisco Union Square Hotel (333 O’Farrell St.)
Monday, December 10th, 2012
8:15pm to 10:30pm

Food & refreshments will be provided.

We won’t all be in San Francisco, so if you can’t get there, the presentations will be posted on the SOI Consortium website (you can also get the presentations from previous events there, too, as well as excellent white papers).

If you do go and want to share your reactions on Twitter, use #FDchipTech and @soiconsortium.

This will be a great event – don’t miss it!