Tag Archive GAA

SOI for MEMS, NEMS, sensors and more at IEDM ’14 (Part 3 of 3 in ASN’s IEDM coverage)

iedm_logoImportant SOI-based developments in MEMS, NEMS (like MEMS but N for nano), sensors and energy harvesting shared the spotlight with advanced CMOS and future devices at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 3, we’ll cover these remaining areas. (In Part 1 of ASN’s IEDM coverage, we had a rundown of the top papers on FD-SOI and SOI-FinFETs. Part 2 looked at papers covering future device architectures leveraging SOI.)

Summaries culled from the abstracts follow.

Sensors

4.2: Three-Dimensional Integrated CMOS Image Sensors with Pixel-Parallel A/D Converters Fabricated by Direct Bonding of SOI Layers

M. Gotoet al (NHK Research Labs, U Tokyo)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM '14)

This illustration (a) shows a schematic diagram of the 3D integrated CMOS image sensor; (b) shows a conceptual diagram of the image sensor pixel; (c) is a cross-sectional scanning electron microscope image of a bonded CMOS image sensor pixel with no voids observed at the bonded interface and with the upper layer thinned to 6.5 µm; and (d) is a photograph of the bonded CMOS image sensor array, where 60-µm-square photodiodes (PD) are stacked on inverters.(NHK paper 4.2 at IEDM ’14)

The resolutions and frame rates of CMOS image sensors have increased greatly to meet demands for higher-definition video systems, but their design may soon be obsolete. That’s because photodetectors and signal processors lie in the same plane, on the substrate, and many pixels must time-share a signal processor. That makes it difficult to improve signal processing speed. NHK researchers developed a 3D parallel-processing architecture they call “pixel-parallel” processing, where each pixel has its own signal processor. Photodetectors and signal processors are built in different vertically stacked layers. The signal from each pixel is vertically transferred and processed in individual stacks.

3D stacking doesn’t degrade spatial resolution, so both high resolution and a high frame rate are achieved. 3D stacked image sensors have been reported previously, but they either didn’t have a signal processor in each stack or they used TSV/microbump technology, reducing resolution. NHK discusses how photodiode and inverter layers were bonded with damascened gold electrodes to provide each pixel with analog-to-digital conversion and a pulse frequency output. A 64-pixel prototype sensor was built, which successfully captured video images and had a wide dynamic range of >80 dB, with the potential to be increased to >100dB.

 

4.5: Experimental Demonstration of a Stacked SOI Multiband Charged-Coupled Device

C.-E. Chang et al (Stanford, SLAC)

Multiband light absorption and charge extraction in a stacked SOI multiband CCD are experimentally demonstrated for the first time. This proof of concept is a key step in the realization of the technology which promises multiple-fold efficiency improvements in color imaging over current filter- and prism-based approaches.

 

15.4: A Semiconductor Bio-electrical Platform with Addressable Thermal Control for Accelerated Bioassay Development

T.-T. Chen et al (TSMC, U Illinois),

In this work, the researchres introduce a bioelectrical platform consisting of field effect transistor (FET) bio-sensors, temperature sensors, heaters, peripheral analog amplifiers and digital controllers, fabricated by a 0.18μm SOI-CMOS process technology. The bio-sensor, formed by a sub-micron FET with a high-k dielectric sensing film, exhibits near-Nernst sensitivity (56-59 mV/pH) for ionic detection. There were also 128×128 arrays tested by monitoring changes in enzyme reactions and DNA hybridization. The electrical current changes correlated to changes in pH reaching -1.387μA/pH with 0.32μA standard variation. The detection of urine level via an enzyme(urease)-catalyzed reaction has been demonstrated to a 99.9% linearity with 0.1μL sample volume. And the detection of HBV DNA was also conducted to a 400mV equivalent surface potential change between 1 μM matched and mismatched DNA. As a proof of concept, they demonstrated the capabilities of the device in terms of detections of enzymatic reaction and immobilization of bio-entities.  The proposed highly integrated devices have the potential to largely expand its applications to all the heat-mediated bioassays, particularly with 1-2 order faster thermal response within only 0.5% thermal coupling and smaller volume samples. This work presents an array device consisting of multiple cutting-edge semiconductor components to assist the development of electrical bio assays for medical applications.

 

NEMS & MEMS

22.1: Nanosystems Monolithically Integrated with CMOS: Emerging Applications and Technologies

J. Arcamone et al (U Grenoble, Leti, Minatec),

This paper reviews the last major realizations in the field of monolithic integration of NEMS with CMOS. This integration scheme drastically improves the efficiency of the electrical detection of the NEMS motion. It also represents a compulsory milestone to practically implement breakthrough applications of NEMS, such as mass spectrometry, that require large capture cross section (VLSI-arrayed NEMS) and individual addressing (co-integration of NEMS arrays with CMOS electronic loop).

 

22.2: A Self-sustained Nanomechanical Thermal-piezoresistive Oscillator with Ultra-Low Power Consumption

K.-H. Li et al (National Tsing Hua U)

This work demonstrates wing-type thermal-piezoresistive oscillators operating at about 840 kHz under vacuum with ultralow power consumption of only 70 µW for the first time. The thermally-actuated piezoresistively-sensed (i.e., thermalpiezoresistive) resonator can achieve self-sustained oscillation using a sufficient dc bias current through its thermal beams without additional electronic circuits. By using proper control of silicon etching (ICP) recipe, the submicron cross-sectional dimension of the thermal beams can be easily and reproducibly fabricated in one process step.

 

22.4: High Performance Polysilicon Nanowire NEMS for CMOS Embedded Nanosensors

I. Ouerghiet al (Leti)

The researchers present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low-cost co-integrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated when compared to crystalline Si. The minimum measured Allan deviation of 7×10-7 leads to a mass resolution detection down to 100 zg (100×10-2 g). Several poly-Si textures are compared and the impact on performances is studied (quality factor, gauge factor, Allan variances, noise, temperature dependence (TCR)). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

 

22.5: Integration of RF MEMS Resonators and Phononic Crystals for High Frequency Applications with Frequency-selective Heat Management and Efficient Power Handling

H. Campanella et al (A*STAR, National U Singapore)

A radio frequency micro electromechanical system (RFMEMS) Lamb-wave resonator made of aluminum nitride (AlN) that is integrated with AlN phononic crystal arrays to provide frequency-selective heat management, improved power handling capability, and more efficient electromechanical coupling at ultra high frequency (UHF) bands. RFMEMS+PnC integration is scalable to microwave bands.

 

22.6: A Monolithic 9 Degree of Freedom (DOF) Capacitive Inertial MEMS Platform

I. E. Ocak et al  (IME, A*STAR Singapore)

A 9 degree of freedom inertial MEMS platform, integrating 3 axis gyroscopes, accelerometers, and magnetometers on the same substrate is presented. This method reduces the assembly cost and removes the need for magnetic material deposition and axis misalignment calibration. Platform is demonstrated by comparing fabricated sensor performances with simulation results.

 

15.6: MEMS Tunable Laser Using Photonic Integrated Circuits

M. Ren et al (Nanyang Technological University, A*STAR)

This paper reports a monolithic MEMS tunable laser using silicon photonic integrated circuit, formed in a ring cavity. In particular, all the necessary optical functions in a ring laser system, including beam splitting/combining, isolating, coupling, are realized using the planar passive waveguide structures. Benefited from the high light-confinement capability of silicon waveguides, this design avoids beam divergence in free-space medium as suffered by conventional MEMS tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (55.5 nm),excellent single-mode properties (50 dB side-mode-suppression ratio (SMSR) and 130 kHz linewdith), compact size (3mm × 2mm), and single-chip integration without other separated optical elements.

 

Energy Harvesting

8.4: A High Efficiency Frequency Pre-defined Flow-driven Energy Harvester Dominated by On-chip Modified Helmholtz Resonating Cavity

X.J. Mu et al (A*STAR)

The researchers present a novel flow-driven energy harvester with its frequency dominated by on-chip modified Helmholtz Resonating Cavity (HRC). This device harvests pneumatic kinetic energy efficiently and demonstrates a power density of 117.6 μW/cm2, peak to peak voltage of 5 V, and charging of a 1 μF capacitor in 200 ms.

8.5: Fabrication of Integrated Micrometer Platform for Thermoelectric Measurements

M. Haras et al  (IEMN, ST)

Preliminary simulations of lateral thermo-generators showed that silicon’s harvesting capabilities, through a significant thermal conductivity reduction, could compete with conventional thermoelectric materials, offering additional: CMOS compatibility; harmlessness and cost efficiency. The researchers report the fabrication and characterization of integrated platforms showing a threefold reduction of thermal conductivity in 70nm thick membranes.

 

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This has been the 3rd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 2 (click here to  read it) looked at papers covering SOI-based future device architectures.

 

SOI-based future device structures at IEDM ’14 (Part 2 of 3 in ASN’s IEDM coverage)

iedm_logoBeyond FD-SOI and FinFETs, important SOI-based developments in advanced device architectures including nanowires (NW), gate all around (GAA) and other FET structures shared the spotlight at IEDM 2014 (15-17 December in San Francisco). IEDM is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here in Part 2 of ASN’s IEDM coverage, we’ll cover future device architectures. In Part 1, we had a rundown of the top SOI-based advanced CMOS papers. In Part 3 we’ll look at MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

16.2: Dual-Channel CMOS Co-Integration with Si Channel NFET and Strained-SiGe Channel PFET in Nanowire Device Architecture Featuring 15nm Gate Length

P. Nguyen et al (Leti, ST, Soitec)

 

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM 14, Paper 16.2)

Omega-gate CMOS nanowire transistors, with a diameter of 12nm and gate length of 15nm. The NFETs have a silicon channel while the PFETs have a SiGe channel. The germanium (Ge) content is estimated to be 30%. (Courtesy: Leti, ST, Soitec at IEDM
14, Paper 16.2)

The researchers have fabricated the first hybrid channel omega-gate CMOS nanowire (NW) with strained SiGe-channel (cSiGe) p-FETs and Si-channel n-FET. An optimized process flow based on the Ge enrichment technique results in a +135% hole mobility enhancement at long gate lengths compared to Si. Effectiveness of cSiGe channel is also evidenced for ultra-scaled p-FET NW (LG=15 nm) with +90% ION current improvement. [110]-oriented NW is shown to be the best candidate to improve drive current under compressive strain. In this work, the strain is measured by using precession electron diffraction with a 1nm spatial resolution. Furthermore, they show that hybrid integration reduces the delay of CMOS ring oscillator (FO=3) by 50% at VDD=0.9V. Finally, they demonstrate the most aggressively scaled hybrid CMOS NWs reported to date with NW width and gate length down to 7nm and 11nm, while maintaining high drive current (687µA/µm for p-FET and 647µA/µm for n-FET) with low leakage current and excellent short-channel-control (DIBL<50mV/V).

 

20.5: Study of the Piezoresistive Properties of NMOS and PMOS Omega-Gate SOI Nanowire Transistors: Scalability Effects and High Stress Level

J. Pelloux-Prayer et al (Leti, Soitec, Tokyo Tech)

The researchers present a comprehensive study of piezoresistive properties of aggressively scaled MOSFET devices. For the first time, the evolution of the piezoresistive coefficients with scaled dimensions is presented (gate length down to 20nm and channel width down to 8nm), and from the low to high stress regime (above 1GPa). They show that the downscaling of geometrical parameters doesn’t allow the use of the conventional definition of piezoresistivity tensor elements. The obtained results give a comprehensive insight on strain engineering ability in aggressively scaled CMOS technology.

 

20.3: Direct Observation of Self-heating in III-V Gate-all-around Nanowire MOSFETs

S.H. Shin et al (Purdue U)

Multi-gate devices, such as, FinFET, Gate-all-around transistors (GAA-FET) improve 3D electrostatic control of the channel, but the corresponding increase in self-heating may compromise both performance and reliability. Although the self-heating effect (SHE) of FinFET appears significant, but tolerable, the same may not be true for GAA geometry, especially in quasi-ballistic regime where hot spots and non-classical heat-dissipation pathways may lead to localized damage. The existing reports of the SHE on the SOI, FinFET or GAA-FET have so far relied either on indirect electrical measurements with inherent temporal delays, or on optical infra-red (λ>1.5μm ) imaging that cannot resolve deep submicron features. As a result, it has so far been impossible to resolve the spatio-temporal features of SHE fully. In this paper, the researchers develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the local temperature rise of GAA-FET with different number of nanowires (NW)(ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW.

 

9.6: In-situ Doped and Tensilely Stained Ge Junctionless Gate-all-around nFETs on SOI Featuring Ion = 828µA/µm, Ion/Ioff ~ 1×105, DIBL= 16-54 mV/V, and 1.4X External Strain Enhancement

I-H. Wong et al (Taiwan U)

In-situ CVD doping and laser annealing can reach [P] and tensile strain as high as 2×1020 cm-3 and 0.37%. Junctionless Ge gate-all-around nFETs with 9 nm-Wfin and 0.8 nm-EOT achieves the record high Ion of 828 µA/µm. The Ion enhancement of ~40% is achieved under the tensile strain of 0.25%.

 

27.6: Flexible High-performance Nonvolatile Memory by Transferring GAA Silicon Nanowire SONOS onto a Plastic Substrate

J.-M. Choi et al (KAIST, NASA)

Flexible nonvolatile memory is demonstrated with excellent memory properties comparable to the traditional wafer-based rigid type of memory. This  achievement is realized through the transfer of an ultrathin film consisting of single crystalline silicon nanowire (SiNW) gate-all-around (GAA) SONOS memory devices onto a plastic substrate from a host silicon wafer.

13.2: High Ion/Ioff Ge-source Ultrathin Body Strained-SOI Tunnel FETs – Impact of Channel Strain, MOS Interfaces and Back Gate on the Electrical Properties

M. Kim et al (U Tokyo)

The researchers demonstrated Ge/strained-Si hetero-junction TFETs with in-situ B doped Ge. The increase in channel strain and optimization of PMA have successfully realized high performance of steep SSmin below 30 mV/dec and large Ion/Ioff ratio over 3×107.

13.3: Comprehensive Performance Re-assessment of TFETs with a Novel Design by Gate and Source Engineering from Device/Circuit Perspective

Q. Huang et al (Peking U)

In this paper, a novel TFET design, called Pocket-mSTFET, is proposed and experimentally demonstrated by evaluating the performance from device metrics to circuit implementation for low-power SoC applications. For the first time, from a circuit design perspective, TFETs performance in terms of ION, IOFF, subthreshold slope (SS), output behavior, capacitance, delay, noise and gain are experimentally benchmarked and also compared with MOSFET. By gate and source engineering without area penalty, the compatibly-fabricated Pocket-mSTFET on SOI substrate shows superior performance with the minimum SS of 29mV/dec at 300K, high ION (~20μA/μm) and large ION/IOFF ratio (~108) at 0.6V. Circuit-level implementation based on Pocket-mSTFET also shows significant improvement on energy efficiency and power reduction at VDD of 0.4V, which indicates great potential of this TFET design for low-power digital and analog applications.

13.4: A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current

J. Zhang et al (EPFL)

The researchers demonstrate a steep subthreshold slope silicon FinFET with Schottky source/drain. The device shows a minimal SS of 3.4 mV/dec and an average SS of 6.0 mV/dec over 5 decades of current swing. Ultra-low leakage floor of 0.06 pA/μm is also achieved with high Ion/Ioff ratio of 107.

 

26.2: Thin-Film Heterojunction Field-Effect Transistors for Ultimate Voltage Scaling and Low-Temperature Large-Area Fabrication of Active-Matrix Backplanes

B. Hekmatshoar et al (IBM)

Heterojunction field-effect thin-film transistors with crystalline Si channels and gate regions comprised of hydrogenated amorphous silicon or organic materials are demonstrated. The HJFET devices are processed at 200ºC and room temperature, respectively; and exhibit operation voltages below 1V, subthreshold slopes of 70-100mV/dec and off currents as low as 25 fA/um.

 

26.7 Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel for 3D IC Applications

Y.-C. Cheng et al (National Tsing Hua U, National Chiao Tung U)

The hybrid fin poly-Si channel junctionless field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of steep SS (64mV/dec), high Ion/Ioff (>107) and small DIBL (3mV/V). The devices are highly promising for future further scaling and 3D stacked ICs applications.

 

35.1: A Physics-based Compact Model for FETs from Diffusive to Ballistic Carrier Transport Regimes

S. Rakhejaet al (MIT, Purdue U)

The virtual source (VS) model provides a simple, physical description of transistors that operate in the quasi-ballistic regime. Through comparisons to measured data, key device parameters can be extracted. The VS model suffers from three limitations: i) it is restricted to short channels, ii) the transition between linear and saturation regions is treated empirically, and iii) the injection velocity cannot be predicted, it must be extracted by fitting the model to measured data. This paper discusses a new model, which uses only a few physical parameters and is fully consistent with the VS model. The new model: i) describes both short and long channel devices, ii) provides a description of the current at any drain voltage without empirical fitting, and iii) predicts the injection velocity (device on-current). The accuracy of the model is demonstrated by comparison with measured data for III-V HEMTs and ETSOI Si MOSFETs.

 

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This is the 2nd post in a 3-part series. Part 1 (click here to  read it) of ASN’s IEDM ’14 coverage gave a rundown of the top FD-SOI and SOI-FinFET papers.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.

 

10nm FD-SOI, SOI FinFETs at IEDM ’14 (Part 1 of 3 in ASN’s IEDM coverage)

iedm_logoFD-SOI at 10nm (and other nodes) as well as SOI FinFETs shared the spotlight at IEDM 2014 (15-17 December in San Francisco), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

There were about 40 SOI-based papers presented at IEDM. Here in Part 1 of ASN’s IEDM coverage, we have a rundown of the top SOI-based advanced CMOS papers. In Part 2, we’ll cover papers on future device architectures. In Part 3 we’ll look at the papers on MEMS, NEMS, sensors and more.

Summaries culled from the abstracts follow.

 

The FD-SOI Papers

9.1: FD-SOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node.

Q. Liu et al (STMicroelectronics, CEA-LETI, IBM, Soitec)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In their IEDM ‘14 paper 9.1 on 10nm FD-SOI, ST, IBM, Leti and Soitec reported a low-temperature process that was developed to form a defect-free SiGe channel from the strained SOI starting substrate. (Image courtesy: ST et al, IEDM 2014)

In this work, researchers from STMicroelectronics and the IBM Technology Development Alliance demonstrate the successful implementation of strained FDSOI devices with LG, spacer & BOX dimensions scaled to 10nm feature sizes.

Two additional enabling elements for scaling FD-SOI devices to the 10nm node are reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 µA/µm for NFET at Ioff=1 nA/um (the highest performing FD-SOI NFET ever reported), and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 µA/µm at Ioff=1 nA/um. Competitive sub-threshold slope and DIBL are also reported.

 

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14. (Courtesy: ST et al, IEDM 2014)

[13] and [14] are Intel papers on 22nm bulk FinFET. [15] is TSMC on 16nm bulk FinFET. [9] is Leti et al on 14nm FD-SOI. “This work” pertains to the 10nm FD-SOI process presented by ST et al at IEDM ‘14.
(Courtesy: ST et al, IEDM 2014)

7.2: A Mobility Enhancement Strategy for sub-14nm Power-efficient FDSOI Technologies

B. De Salvo et al. (Leti, ST, IMEP, IBM, Soitec)

This paper presents an original multi-level evaluation methodology for stress engineering device design of next-generation power-efficient devices. Ring oscillator simulations showed that a dynamic power gain of 50% could be achieved while maintaining circuit frequency performance thanks to the use of efficient mobility boosters. Thus a clear scaling path to achieve high-mobility, power-efficient sub-14nm FDSOI technologies has been identified.

 

3.4: Single-P-Well SRAM Dynamic Characterization with Back-Bias Adjustment for Optimized Wide-Voltage Range SRAM Operation in 28nm UTBB FD-SOI

O. Thomas et al (UC Berkeley, ST)

This paper demonstrates the 28nm ultra-thin body and buried oxide (UTBB) FD-SOI high-density (0.120µm²) single pwell (SPW) bitcell architecture for the design of low-power wide voltage range systems enabled by back-bias adjustment. A 410mV minimum operating voltage and less than 310mV data retention voltage with less than 100fA/bitcell are measured in a 140kb programmable dynamic SRAM. Improved bitcell read access time and write-ability through back-bias are demonstrated with less than 5% of stand-by power overhead.

 

27.5: New Insights on Bottom Layer Thermal Stability and Laser Annealing Promises for High Performance 3D Monolithic Integration

C. Fenouillet-Beranger et al (Leti, ST, LASSE)

For the first time the maximum thermal budget of in-situ doped source/drain state-of-the-art FD-SOI bottom MOSFET transistors is quantified to ensure transistors stability in Monolithic 3D (M3D) integration. Thanks to silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Thanks to in-depth morphological and electrical characterizations, it shows very promising results for high performance Monolithic 3D integration.

 

9.2 Future Challenges and opportunities for Heterogeneous process technology. Toward the thin films, Zero intrinsic Variabiliiy devices, Zero power Era (Invited)

S. Deleonibus et al (Leti)

By 2025, 25 % of the World Gross Domestic Product will depend on the development of Information and Communication Technologies . Less greedy device, interconnect, computing technologies and architectures are essential to aim at x1000 less power consumption.

IBM’s SOI-FinFET, eDRAM and 3D Papers

32.1: Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme

H. Tsai et al (IBM)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

These drawings illustrate the process flow for forming groups of SOI fins using the directed self-assembly technique. (IBM at IEDM ’14, paper 32.1)

High density fin formation is one of the most critical processes in the FinFET device fabrication flow. Given that a typical device is composed of an ensemble of fins, each fin must be nearly identical to avoid performance degradation arising from geometric variation. Thus, techniques for fin patterning must demonstrate the ability to form fins with a high degree of structural precision. In this paper, IBM researchers present the use of directed self-assembly using block copolymers (BCP) and 193nm immersion (193i) lithography as a suitable way to make the fins of FinFETs for beyond the 10 nm node.

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

(a) Shows groups of two fins formed by the process, while (b) is a cross-sectional image of a larger group of fins. (IBM at IEDM ’14, paper 32.1)

 

Essentially, a topographic template pattern was created on a chemically neutral surface. Confinement of the BCP between the sidewalls of the template provides an ordering force that drives the pattern into registry with the surface topography. Electrical data produced from fins with a 29-nm pitch patterned with this approach showed good uniformity, with no signs of gross variation in critical dimensions.

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

Fabrication of FinFET devices using the self-assembly process (a) before customization; (b) after customization; (c) after gate patterning; and (d) after spacer formation and epitaxial Si growth. (IBM at IEDM ’14, paper 32.1)

 

3.8 High Performance 14nm SOI FinFET CMOS Technology with 0.0174μm2 embedded DRAM and 15 Levels of Cu Metallization (Late News)

C-H. Lin et al (IBM)

The IBM team presents a fully integrated 14nm CMOS technology featuring FinFET architecture on an SOI substrate for a diverse set of SoC applications including high-performance server microprocessors and low-power ASICs. A unique dual workfunction process optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel and without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. Because the technology is envisioned for use in SoC applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom than ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.

The SOI FinFET’s excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

 

16.1: First Demonstration of High-Ge-Content Strained-Si1-xGex (x=0.5) on Insulator PMOS FinFETs with High Hole Mobility and Aggressively Scaled Fin Dimensions and Gate Lengths for High-Performance Applications

P. Hashemi et al (IBM)

Strained SiGe FinFETs are a promising PMOS technology for the 10nm technology node and beyond, due to their excellent electrostatics and built-in uniaxial compression. Yet while SiGe FinFETs with moderate germanium (Ge) content have been characterized, little data exists on FinFETs with high Ge  content. And, what little data does exist is mostly focused on relaxed or strained pure Ge. For the first time anywhere, IBM detailed CMOS-compatible, low-power and high-performance SiGe PMOS FinFETs with more than 50% Ge content. The devices feature ultra-narrow fin widths – down to 3.3 nm – which provide excellent short-channel control for low-power applications.  Using a Si-cap-free passivation process, they report SS=68mV/dec and μeff=390±12 cm2/Vs at Ninv=1e13 cm-2, outperforming the state-of-the-art relaxed Ge FinFETs. They demonstrated the highest performance ever reported (Ion=0.42mA/µm and Ioff=100nA/µm) for sub-20nm PMOS FinFETs at 0.5 V.

 

19.4: 0.026µm2 High Performance Embedded DRAM in 22nm Technology for Server and SOC Applications

C. Pei et al (IBM)

This paper presents the industry’s smallest eDRAM based on IBM’s 22nm (partially depleted) SOI technology, which has been recently leveraged for IBM’s 12-core 649mm2 Server Processor POWER8™. It summarizes the n-band resistance innovations, and reports for the first time the asymmetric embedded stressor, cavity implant and through gate implant employed in 22nm eDRAM technology. The fully integrated 256Mb product array has demonstrated capability of 1.4ns cycle time, which is significantly faster than any other embedded DRAM.

 

14.6: Through Silicon Via (TSV) Effects on Devices in Close Proximity– the Role of Mobile Ion Penetration – Characterization and Mitigation

C. Kothandaraman et al (IBM)

The research team identified and studied a new interaction between TSV processes and devices in close proximity, different from mechanical stress. Detailed characterization via Triangular Voltage Sweep (TVS) and SIMS shows the role of mobile ion penetration from BEOL layers. They then presented an improved process, confirmed in test structures and DRAM.

 

RF-SOI

18.4: Technology Pathfinders for Low Cost and Highly Integrated RF Front End Modules

C. Raynaud (Leti)

This paper highlights the challenges related to the increasing number of modes (GSM, WCDMA, LTE) and frequency bands in mobile devices. It describes the technology pathfinders to get cheaper highly integrated multimode multi–band RF Front End modules.

 

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This is the 1st post in a 3-part series. Part 2 (click here to  read it) of ASN’s IEDM ’14 coverage looks at papers covering SOI-based future device architectures.  Part 3 (click here to read it) covers SOI-based MEMS, NEMS, sensors and more.

IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers

SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13.  Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices.

Brief summaries, culled from the program (and some of the actual papers) follow.

 

SOI-FinFETS

9.4 2nd Generation Dual-Channel Optimization with cSiGe for 22nm HP Technology and Beyond (IBM)

This paper about performance boosters is applicable to all flavors of SOI-based devices, including FinFET, planar FD-SOI and partially-depleted SOI. At 22nm for high-performance (HP), IBM is still doing the traditional partially-depleted (PD) SOI. At 14nm, when they go to SOI-FinFETs, one of the channel stressors to boost performance is Silicon-Germanium (cSiGe). To better understand the physics, layout effects and impact of cSiGe on device performance, IBM leveraged their 22nm HP technology to do a comprehensive study. They got a 20% performance boost and 10% Short Channel Effect (SCE) improvement, and showed that this 2nd generation high-performance dual-channel process can be integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology.

 

13.5 Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-Fin SOI FINFETs  (GlobalFoundries, IBM)

SOI FINFETs are very attractive because of their added immunity to Vt variability due to undoped channels. However, circuit level performance also depends on the effective current (Ieff) variability. According to the advance program, “A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.”

 

20.5 Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs (AIST, Nissin Ion Equipment)

In this paper, the researchers thoroughly investigated the impact of the heated ion implantation (I/I) technology on HK/MG SOI FinFET performance and reliability, which it turns out is excellent. They demonstrated that “…the heated I/I brings perfect crystallization after annealing even in ultrathin Si channel. For the first time, it was found that the heated I/I dramatically improves the characteristics such as Ion-Ioff, Vth variability, and bias temperature instability (BTI) for both nMOS and pMOS FinFETs in comparison with conventional room temperature I/I.”

 

26.2:  Advantage of (001)/<100> oriented Channel to Biaxial and Uniaxial Strained Ge-on-Insulator pMOSFETs with NiGe S/D (AIST)

In this paper about boosters in fully-depleted planar SOI and GeOI based devices, the researchers “compared current drivability between (001)/<100> and (001)/<110> strained Ge-on-insulator pMOSFETs under biaxial and uniaxial stress.” They experimentally demonstrated for the first time that in short channel (Lg < 100 nm) devices, <100> channels exhibit higher drive current than <110> channels under both the biaxial- and the uniaxial stress, in spite of the disadvantage in mobility, although this is not the case with longer channel devices. The advantage is attributable to higher drift velocity in high electric field along the direction and becomes more significant for shorter Lg devices. The strained-Ge (001)/<100> channel MOSFET have a potential to serve as pFET of ultimately scaled future CMOS.

 

33.1 Simulation Based Transistor-SRAM Co-Design in the Presence of Statistical Variability and Reliability (Invited) (U. Glasgow, GSS, IBM)

With ever-reducing design cycles and time-to-market, design teams need early delivery of a reliable PDK before mature silicon data becomes available. This paper shows that the GSS ‘atomistic’ simulator GARAND used in this study provides accurate prediction of transistor characteristics, performance and variability at the early stages of new technology development and can serve as a reliable source for PDK development of emerging technologies, such as SOI FinFET.  Specifically, the authors report on, “…a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modeling strategy is developed for early delivery of a reliable PDK, which enables TCAD- based transistor-SRAM co-design and path finding for emerging technology nodes.” 

 

RF-SOI

1.3: Smart Mobile SoC Driving the Semiconductor Industry: Technology Trend, Challenges and Opportunities (Qualcomm)

In this plenary presentation, Geoffry Yeap, VP of Technology at Qualcomm gave a perspective on state of the art mobile SoCs and RF/analog technologies for RF SOCs. The challenge, he said in his paper, is “…lower power for days of active use”. He cited the backgate for asymmetric gate operation and dynamic Vt control, noting that FinFETs lack an easy way to access the back gates. “This is especially crucial when Vdd continues to scale lower to a point that there is just not sufficient (Vg-Vt) to yield meaningful drive current,” he continued. While he sees FD-SOI “very attractive”, he is concerned about the ecosystem, capacity and starting wafer price.

With respect to RF-SOI, the summary of his talk in the program stated, “Cost/power reduction and unique product capability are enabled by RF front end integration of power amplifiers, antenna switches/tuners and power envelope tracker through a cost-effective RF-SOI instead of the traditional GaAs.”

 

Advanced Devices

Post-FinFETs, one of the next-generation device architectures being heavily investigated now is  gate-all-around (GAA). While FinFETs have gate material on three sides, in GAA devices the gate completely surrounds the channel. A popular fabrication technique is to build them around a nanowire, often on an SOI substrate.

4.4 Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling  (Forschungszentrum Jülich, U. Udine, Soitec)

This is a paper about a strained Si (sSi) nanowire array Tunnel FETs (TFETs). The researchers demonstrated that scaled gate all around (GAA) strained Si (sSi) nanowire array (NW) Tunnel FETs (TFETs) allow steep slope switching with remarkable high ION due to optimized tunneling junctions. Very steep tunneling junctions have been achieved by implantations into silicide (IIS) and dopant segregation (DS) with epitaxial Ni(AlxSi1-x)2 source and drain. The low temperature and pulse measurements demonstrate steep slope TFETs with very high I60 as TAT is suppressed. GAA NW TFETs seem less vulnerable to trap assisted tunneling (TAT). Time response analysis of complementary-TFET inverters demonstrated experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

 

IBM_IEDMBangsaruntip20.2Fig.4

(image courtesy: IBM, IEEE/IEDM)

20.2 Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond (IBM)

Record Silicon Nanowire MOSFETs: IBM researchers described a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10-nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured an incredible 30-nm SiNW pitch (the spacing between adjacent nanowires) with a gate pitch of 60 nm. Devices with a 90-nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

 

 

26.4 FDSOI Nanowires: An Opportunity for Hybrid Circuit with Field Effect and Single Electron Transistors (Invited) (Leti)

This paper is about nanowires and single electron transistors (SET).  As indicated in the  program, “When FDSOI nanowires width is scaled down to 5nm, the nanowires can encounter a dramatic transition to single electron transistor characteristics. This enables the first room temperature demonstration of hybrid SET-FET circuits thus paving the way for new logic paradigms based on SETs. Further scaling would rely on deterministic dopant positioning. We have also shown that Si based electron pumps using tunable barriers based on FETs are promising candidates to realize the quantum definition of the Ampere.”

 

26.6 Asymmetrically Strained High Performance Germanium Gate-All-Around Nanowire p-FETs Featuring 3.5 nm Wire Width and Contractable Phase Change Liner Stressor (Ge2Sb2Te5) (National U. Singapore, Soitec)

In this paper about GAA and nanowires, the researchers report “…the first demonstration of germanium (Ge) GAA nanowire (NW) p-FETs integrated with a contractable liner stressor. High performance GAA NW p-FET featuring the smallest wire width WNW of ~3.5 nm was fabricated. Peak intrinsic Gm of 581 μS/μm and SS of 125 mV/dec was demonstrated. When the Ge NW p-FETs were integrated with the phase change material Ge2Sb2Te5 (GST) as a liner stressor, the high asymmetric strain was induced in the channel to boost the hole mobility, leading to ~95% intrinsic Gm,lin and ~34% Gm,sat enhancement. Strain and mobility simulations show good scalability of GST liner stressor and great potential for hole mobility enhancement.”

 

III-V, More Than Moore and Other Interesting Topics

28.5 More than Moore: III-V Devices and Si CMOS Get It Together (Invited) (Raytheon)

This is continuation of a major ongoing III-V and CMOS  integration project that Raytheon et al wrote about in ASN five years ago (see article here).  As noted in the IEDM program, the authors “…summarize results on the successful integration of III-V electronic devices with Si CMOS on a common silicon substrate using a fabrication process similar to SiGe BiCMOS. The heterogeneous integration of III-V devices with Si CMOS enables a new class of high performance, ‘digitally assisted’, mixed signal and RF ICs.

 

31.1 Technology Downscaling Worsening Radiation Effects in Bulk: SOI to the Rescue (Invited) (ST)

In this paper, the authors explore the reliability issues faced by the next generation of devices.  As they note in the description of the paper in the program, “Extrinsic atmospheric radiations are today as important to IC reliability as intrinsic failure modes. More and more industry segments are impacted. Sub-40nm downscaling has a profound impact on the Soft Error Rate (SER) of BULK technologies. The enhanced resilience of latest SOI technologies will fortunately help leveraging existing robust design solutions.”

 

13.3 A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications (ST, Luxtera)

Luxtera’s work on Silicon Photonics and now products based on integrated optical communications has been covered here at ASN for years. In this paper Luxtera and ST (which now is Luxtera’s manufacturing partner) present a low-cost 300mm Silicon Photonics platform for 25Gb/s application compatible with 3D integration and featuring competitive optical passive and active performance. This platform aims at industrialization and offering to system designers a wide choice of electronic IC, targeting markets applications in the field of Active optical cables, optical Modules, Backplanes and Silicon  Photonics Interposer.

 

Irisawa (2.2) Fig.9

The graph above shows the high electron mobility of Triangular MOSFETs with InGaAs Channels. (Image courtesy: AIST, IEEE/IEDM) 

 

2.2. High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures (AIST, Sumitomo, Tokyo Institute of Technology)

InGaAs is a promising channel material for high-performance, ultra-low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration. A research team led by Japan’s AIST built triangular InGaAs-on-insulator nMOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30 nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 μA/μm at a 300-nm gate length, showing they have great potential for ultra-low power and high performance CMOS applications.

 

16.4. High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator Tri-gate MOSFETs with high short channel effect immunity and Vth tenability (Sumitomo, Tokyo Institute of Technology)

This III-V paper investigates the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. “It was found that Tbody scaling provides better SCEs control, whereas Tbody scaling causes μfluctuation reduction. To achieve better SCEs control, Tchannel scaling is more favorable than Tbuffer scaling, indicating QW channel structure with MOS interface buffer is essential in InAs-OI MOSFETs. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/μm. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control. These results strongly suggest that the Tri-gate ETB III-V-OI structure is very promising scaled devices on the Si platform to simultaneously satisfy high performance high SCE immunity and Vth tunability.”

11.1 A Flexible Ultra-Thin-Body SOI Single-Photon Avalanche Diode (TU Delft)

This is a paper on flexible electronics for display and imaging systems. “The world’s first flexible ultra-thin-body SOI single-photon avalanche diode (SPAD) is reported by device layer transfer to plastic with peak PDP at 11%, DCR around 20kHz and negligible after pulsing and cross-talk. It compares favorably with CMOS SPADs while it can operate both in FSI and BSI with 10mm bend diameter,” say the researchers.

 

11.7 Local Transfer of Single-Crystalline Silicon (100) Layer by Meniscus Force and Its Application to High-Performance MOSFET Fabrication on Glass Substrate (Hiroshima U.)

In this is a paper on flexible electronics for display and imaging systems, the researchers “…propose a novel low-temperature local layer transfer technique using meniscus force. Local transfer of the thermally-oxidized SOI layer to glass was carried out without any problem. The n-channel MOSFET fabricated on glass using the SOI layer showed very high mobility of 742 cm2V-1s-1, low threshold voltage of 1.5 V.  These results suggest that the proposed (meniscus force-mediated layer transfer) technique (MLT) and MOSFET fabrication process opens up a new field of silicon applications that is independent of scaling.”

 

Note: the papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.

 

Special thanks to Mariam Sadaka and Bich-Yen Nguyen of Soitec for their help and guidance in compiling this post.

Self-Heating Effect and Variability in Gate-All-Around (GAA) Silicon Nanowire Transistors (SNWT)

Researchers in academia have partnered with industry to increase understanding of critical issues in advanced non-classical CMOS devices.

Highly scaled devices present a new range of challenges with respect to critical issues such as leakage current, short-channel effects, high-field effects, variability, reliability, noise and parasitic impact. Device structure and material innovation are the primary enablers for performance enhancement in CMOS technology.

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is a kind of multiple-gate SOI transistor that is considered as one of the promising candidates for ultimate scaling, due to its excellent electrostatic control capability, improved transport properties and feasible device design.

Figure 1. Schematic view of a gate-all-around silicon nanowire transistor.

As shown in Figure 1, this kind of device has a very unique structure: the gate material surrounds the channel region – the silicon nanowire – on all sides. This three-dimensional surrounding gate-stack has multiple crystallographic interface orientations, and there is a sharp transition from the large source/drain region to the narrow nanowire part (of the source/drain extension).

Figure 2. SEM image of the fabricated SNWT with 10nm diameter.

Because of the extreme length-to-width ratio, the nanowire channel can be considered as “quasi-one-dimensional”, which confers properties not seen in 3D materials.

Some of the critical issues may be even more complicated, giving rise to new challenges in device engineering of SNWTs.

In previous work, our team has investigated the parasitic effects[1], reliability[2] and noise characteristics[3] of SNWTs. In a recent paper[4] we presented at the IEEE SOI Conference, we discussed the self-heating effect (SHE) and variability in SNWTs, which are two key issues of nano-scaled devices for practical circuit applications.

Figure 2 shows the SEM image of the fabricated SNWT with 10 nm diameter.

Self-Heating Effects

As devices size scales and circuit density increases, the self-heating effect becomes a critical concern for device performance and reliability degradation. Due to the 1-D nature of nanowire and increased phonon-boundary scattering in the GAA structure, the self-heating of SNWTs in bulk is comparable or even a little bit worse than SOI devices.

The ultimate performance of SNWT-based circuits may be intrinsically limited by SHE.  Therefore, special design approaches are needed, such as new thermal-aware design methodology for SNWT circuits.

Variability in SNWTs

Highly-scaled CMOS devices and circuits suffer from serious variability issues. For SNWTs, with their ultra-scaled dimensions of the nanowire and surrounding gate stack structure, variability shows unique features.  Identifying and understanding these specificities can help provide guidelines for robust SNWT design. The variation sources in SNWTs are schematically shown in Figure 3.

Figure 3. Schematic 3D view of various fluctuation sources in SNWTs.

Our experiments found the SNWT-based SRAM cell more stable than its planar counterparts, due to the superior electrostatic control and thus better immunity of surface potential variations. That makes SNWTs a good candidate for future SRAM cell applications from the perspective of variation suppression.

Conclusion

Like in any design, there are tradeoffs to be made when designing nanowire diameters. The use of an SOI substrate for simplifying the nanowire device fabrication may be a better approach. In any case, there is a long road ahead, as we need to further our in-depth physical understanding of the device. However, the GAA SNWT’s excellent electrostatics, improved transport and easier 3D integration should ultimately enable new applications – in both the “More Moore” and “More Than Moore” realms.

The author wishes to acknowledge the work of her students and the staff at the Peking University cleanroom, and the collaboration of Dr. D.-W. Kim and Dr. D. Park of Samsung.

[1] J. Zhuge et al., T-ED, p.2142, 2008
[2] R. Wang et al., IEDM, p.821, 2007; L. Zhang et al., IEDM, p.123, 2008
[3] J. Zhuge et al., EDL, p.57, 2009; R. Wang et al., IEDM, p.753, 2008
[4] Self-Heating Effect and Characteristic Variability of Gate-All-Around Silicon Nanowire Transistors for Highly-Scaled CMOS Technology (invited). 2010 IEEE SOI Conference.