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Semicon Europa ’14 (Grenoble, 7-9 October) Includes Top Speakers at Conferences on Low Power, 3DI, Power Electronics & more

(Image courtesy: SEMI)

 

For the first time ever, Semicon Europa will be held in Grenoble this year, and FD-SOI will be a major part of it (website link here). With more than 5000 visitors and 350 exhibitors, Semicon Europa is the greatest annual event for the European microelectronics industry.

And Grenoble can fairly be considered the epicenter of all things SOI: it really took off when Leti researcher Michel Bruel invented the Smart CutTM technology there for manufacturing SOI wafers in the early 1990’s. That was then spun off to Soitec up the road, and the rest is history in the making. In fact, Forbes recently recognized Grenoble as one of the Top 5 Most Inventive Cities in the world.

So from now on, Semicon Europa will alternate between Dresden, Germany (home to GlobalFoundries’ fabs) and Grenoble, France.

Happily this is coinciding with an industry upturn, so Semi’s signed up 25% more exhibitors than last year. In addition to the exhibition floor, the 3-day event will also host over 300 speakers at over 70 conferences and more than 100 hours of technology sessions and presentations. This is no longer your quiet Euro-equipment show – this is a dynamic happening covering the entire supply chain, with a big emphasis on innovation and applications.

For those attending the popular Fab Managers Forum, the opening keynote will be made by Soitec founder and CEO André-Jacques Auberton-Hervé. In addition to heading up the world’s largest SOI wafer manufacturer, Dr. Auberton-Hervé is a member of the EC’s High-Level Group on Key Enabling Technologies (KET) and of the Electronic Leaders Group (ELG), which is in charge of implementing the European Union’s “10/100/20” strategy (they’re looking to leverage €10 Billion Public/Private Funding for a €100 Billion investment from industry for manufacturing to capture 20% of the semiconductor market value for Europe by 2020). As we reported here in ASN earlier this year, SOI-based apps are an important part of all this.

In the abstract for his Semicon presentation, Dr. Auberton-Hervé indicates he’ll describe the ELG implementation plan focused on demand accelerators (IoT, mobile convergence), supply chain strengthening, and an enhanced framework development across Europe. The Pilot Lines initiative was started in 2012, and industry is ready to invest now, he notes, with 5 pilot lines in progress, and numerous projects submitted. He’ll highlight how manufacturing performance is key in the European semiconductor industry, from materials and equipment to components design and wafer production.

 

FD-SOI at the Semicon Europa Low Power Conference

The key Semicon Europa event for the FD-SOI ecosystem will be The Low Power Conferencewhich features a cast of heavy hitters (abstracts for the talks and speaker bios are available here.) It kicks off on Tuesday afternoon (7 September) with a market analysis by ST COO Jean-Marc Chery, exploring solutions for mobile to servers and IoT.

Next up, Manfred Horstmann, GlobalFoundries’ Director of Products and Integration in Dresden will focus on SOCs for at 28/20nm. He’s using the term “ET-SOI” with BB (back bias) options. The ET stands for Extremely Thin SOI – it’s the term IBM first used for FD-SOI, but the two terms are now used seemingly interchangeably. As Horstmann notes in the conference abstract, “Being a planar device, ET-SOI devices allow the continuation of previous nodes manufacturing and design experience. Vt-tunability and low GIDL currents are a clear advantage of ET-SOI BB devices for SoC applications, too.” He’ll conclude with an outlook on FinFETs.

Thomas Skotnicki Fellow and Director of Advanced Devices at STMicroelectronics and all around giant of FD-SOI (and in particular ST’s flavor: ultra-thin box and body aka UTBB) has what sounds like a groundbreaking IoT talk. Beyond FD-SOI, he’ll cover how the technology will be used in conjunction with energy harvesting, storage, power management, sensors and MEMS. He’s got a low-power mobile app example to show us, too.

Other talks include imec on FinFETs, Imagination Technology on MIPS, Qualcomm on the “Landscape for More Moore”, and Leti on FD-SOI and 3D stacking for multicore embedded systems.

Renesas will detail their flavor of FD-SOI, which they’ve been working on for a long time (especially with innovations from Hitachi). They call it Silicon-on-Thin-Buried Oxide, aka SOTB.

David Jacquet of ST will address design, showing among other things how FD-SOI opens the way to new opportunities like Wide DVFS and dynamic leakage management. He’ll be detailing the key IP for implementing those technologies. (He’s got a great video on FD-SOI design techniques, btw – click here for more on that.)

Soitec CTO Carlos Mazure will cover the range of substrate solutions for devices across the mobile space, including RF, FD-SOI and SOI FinFET.

Wednesday morning, the conference continues with more from ST, and a must-see talk on FD-SOI and IoT costs and projections by Handel Jones of IBS. (If you’ve missed his excellent pieces here in ASN, you’ll find them all here.)

The rest of the afternoon will focus on design tools and applications, with talks from Cadence, ANSYS, Docea, HP (two talks from them), Ericsson, Schneider and Sorin (medical devices).

ASN will be there – follow us on Twitter for live coverage – and we’ll bring you more details of the key talks in the weeks to come.

 

Power and 3DI

A couple of other last notes if you’re planning a trip to Semicon Europa. On Wednesday afternoon (8 September), a 3D Integration Session (details here) will cover recent updates on 3D circuit and process technologies. Following an introduction by Ionut Radu, Soitec Senior Scientist, speakers from TSMC, imec, Leti, EV Group, Entegris, Fujifilm and Rockwood will address the status of 3D circuits, including 3D TSV and monolithic 3D integration schemes, manufacturing challenges and readiness for application specific systems.

Another terrific Semicon Europa event for the advanced substrates community will be the Power Electronics Conference: the ultimate path to CO2 reduction. Topics cover GaN, GaN-on-Si, SiC and SOI. Renault, Leti, Schneider Electric, ST, Infineon, Yole, Fairchild, and Siltronic will be presenting, as well as Arnaud Rigny of Soitec, who’ll will give a talk on smart substrates for smart power. This all takes place on Wednesday and Thursday, the 8th and 9th of September. Details can be found here.

Hope to see you in Grenoble!

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IP Value Starts at the Substrate Level

If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.

Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI)  in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.

Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.

In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents.  This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.

smart-stacking

So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.

For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.

In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.

One example of how effective our IP policy is came about in 1997 when we contracted with  Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.

Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.

The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.

Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.

Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.

The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level.   We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.

In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.

ByGianni PRATA

SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments.

SOI and other advanced substrate based technologies will be significant beneficiaries of the European Commission’s “New European Industrial Strategy for Electronics”, targeting the mobilization of €100 billion in new private investments. In addition to the recently announced €360M FD-SOI Places2Be project (which stands for Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe), other projects announced by the ENIAC JU* include:

  • E450EDL (“European 450mm Equipment Demo Line”, €205.7M, 43 members) – this project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition.
  • AGATE (“Development of Advanced GaN substrates & Technologies”, €59.6M, 10 members, lead by Soitec) The project plans to set-up three pilot lines for GaN-based advanced substrates and devices to help the introduction and market acceptance of these More-Than-Moore technologies.
  • Lab4MEMS (“LAB FAB for smart sensors and actuators MEMS”, €28.5M, 21 members, lead by ST) aims to establish a European Pilot Line targeting the market drivers in consumer and healthcare application such as body area sensors and remote monitoring.

As European Commission Vice President Neelie Kroes said, “I want to double our chip production to around 20% of global production. […] It’s a realistic goal if we channel our investments properly.”

*The ENIAC Joint Undertaking (JU) is a public-private partnership focusing on nanoelectronics that brings together ENIAC Member/Associated States, the European Commission, and AENEAS (an association representing European R&D actors in this field). The document providing details on the pilot line projects is available here.

ByGianni PRATA

An agreement between Soitec and GT Advanced Technologies is aiming to lower the cost of LED production and accelerate adoption in commercial and residential lighting

An agreement between Soitec and GT Advanced Technologies is aiming to lower the cost of LED production and accelerate adoption in commercial and residential lighting. GT is developing an HVPE (high productivity hydride vapor phase epitaxy) system incorporating Soitec Phoenix Labs’ (a subsidiary of Soitec) unique and proprietary HVPE technology. This includes Soitec’s novel and advanced source delivery system that is expected to lower the costs of precursors delivered to the HVPE reactor. The HVPE system will enable the production of GaN template sapphire substrates at scale. The expected target date for the commercial availability of the HVPE system is the second half of 2014.

ByGianni PRATA

Soitec’s Smart Cut™ technology is now being leveraged to produce GaN substrates for high-performance LED lighting applications

Soitec‘s Smart Cut™ technology, best known for its role as the leading technology for producing SOI wafers, is now being leveraged to produce GaN substrates for high-performance LED lighting applications. Following a successful pilot line announced last year, Sumitomo Electric will now industrialize the product and invest in Smart Cut technology. Yoshiki Miura, general manager of the Compound Semiconductor Materials Division at Sumitomo Electric, said, “By combining the two innovative technologies – Soitec’s Smart Cut technology and our high-quality, large-diameter, free-standing GaN substrates – we are able to offer a high-value proposition to our LED customers. Soitec’s unique material-transfer technology enables the reuse of GaN wafers several times, achieving a substantial reduction in the cost of high-quality GaN materials to serve high-volume applications.”

ByGianni PRATA

Soitec and Sumitomo Electric are launching pilot production of 4” and 6” GaN wafers for the LED and power markets

World-leading advanced substrate maker Soitec and compound materials leader Sumitomo Electric are launching pilot production of 4” and 6” GaN wafers for the LED and power markets. Soitec applies its Smart CutTM layer-transfer process to Sumitomo’s bulk GaN wafers to generate engineered wafers with the same thermal expansion (CTE) as standard GaN wafers but at lower costs.

ByGianni PRATA

Soitec has inked deals with Peregrine and Sumitomo

In recent months, Soitec has inked deals with:

Peregrine for joint development and production of a new, bonded silicon-on-sapphire (SOS) substrate for RFICs;

• and with Sumitomo for the development of engineered gallium nitride (GaN) substrates for applications like high brightness LEDs as well as electric power devices designed for hybrid and full electric vehicles.

ByGianni PRATA

Soitec’s Smart Cut technology teams with Sumitomo Electric’s industry-leading GaN wafers

Soitec’s Smart Cut technology teams with Sumitomo Electric’s industry-leading GaN wafers to make lower-cost, high quality GaN engineered substrates for high-brightness LEDs and power devices for hybrid & electric vehicles.

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GaN’s Bright Future

GaN-on-Si is moving towards becoming a cost-effective enabler for next-generation LED and power devices.

During the past decade gallium nitride (GaN) has become an important compound semiconductor as it enables numerous key applications in optoelectronics and in power electronics.

GaN LED technology could well be the Holy Grail in terms of providing the next generation of lighting. LEDs in general present many advantages over incandescent light sources, including a higher luminous efficacy in combination with a longer lifetime.

Power SiN/AlGaN/GaN transistors mounted on AlN ceramics.

Within the LED family, GaN is the only material that enables fabrication of efficient blue and white LEDs. Today, InGaN/GaN based blue, green and white devices are already available on the LED market – which is a multi-billion euro high-volume market.

In power electronics, the GaN materials system enables the fabrication of power components that offer a competitive advantage to traditional silicon MOSFET power devices. GaN intrinsically possess an electrical breakdown field that is 10 times larger than silicon, while offering excellent transport properties: key enablers for very effective reductions of both conduction and switching losses at high voltages or for high-power/high-frequency operation. Due to its wide band gap (3.4eV), operation at high temperatures is no longer an obstacle.

All these characteristics make the material especially suited for fabricating the next-generation of switching components to be used in electric motors, power invertors or DC/DC convertors, for example. And although GaN technology for these applications is still in its infancy, the market for such switching components is destined to grow considerably, because of the drive to use more hybrid electrical vehicles in transport, more solar installations, more wind farms, and the smart grids to connect it all.

Reigning in costs

But today, GaN technology is still very expensive. Lower costs and greater productivity consistency are prerequisite for a further widespread acceptance by industry.

Measuring an InGaN/GaN based LED.

One way to address this concern is to bring GaN LED and power manufacturing processes towards a production platform that uses a CMOS-like process on 8-inch silicon wafers. Today, GaN processes are typically performed on smaller size substrates, such as the very expensive silicon carbide (SiC – for power and RF electronics) and sapphire (for LEDs) substrates, predominantly available in diameters of 2, 3 or 4 inches.

At imec, we are convinced of the tremendous advantages of using 8-inch silicon substrates in an 8-inch silicon facility: up-scaling the wafer size increases the productivity and hence the cost-efficiency, as more chips become available for an equal amount of fabrication steps. But we can also benefit from the many years of high-volume silicon manufacturing know how.

For example, for LED manufacturing, the availability of process and particle control, in-situ metrology and accelerated lifetime testing facilitates the production of highly reliable devices with long lifetime that are highly uniform in terms of light intensity and wavelength. In other words, we will achieve lower cost by leveraging the ‘economies of scale’ of silicon.

At imec, we tackle these challenges in our industrial affiliation program (IIAP) on GaN power and LED devices, together with our program partners. This IIAP builds on imec’s excellent track record in GaN epi-layer growth, new device concepts (e.g. HEMTs, double HEMTs, e-mode devices) and CMOS device integration. We are on track in making these GaN processes silicon compatible and, meanwhile, we are developing GaN epitaxy on 8 inch in a new epi reactor – important steps towards the fabrication of cost-effective next-generation GaN devices.

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Closing the Rectifier Gap

The G2REC project leader explains the role GaN can play in solving a major energy efficiency challenge.

Under the aegis of the €30 million European G2REC (Grand Gap Rectifier) project, Jean-Baptiste Quoirin of STMicroelectronics, is leading a consortium of companies and labs tackling the problem of rectifiers for things like computer server power supplies and motor control in large appliances. Read More