The FD-SOI ecosystem is strong. This was made clear at the recent Tokyo SOI Workshop, organized by the SOI Consortium. The event was spread out over two days, and most of the presentations are now posted (click here to access them). To cover the full scope of the workshop will take (at least) a couple ASN posts. So let’s start with Day 1, which was billed as the “FD-SOI Ecosystem” day.
A full house for the 3rd Annual Tokyo SOI Workshop, Day 1, FD-SOI Ecosystem(Courtesy: SOI Consortium)
It kicked off with a full-house for an afternoon session in the Yokohama Landmark Tower hosted by Silvaco, with presentations from some of the key players in the FD-SOI Ecosystem.
Silvaco: FD-SOI EDA Pioneer
David Sutton, CEO of EDA provider Silvaco opened the session with his talk, TCAD, EDA & IP to Support FD-SOI. Silvaco has deep FD-SOI roots, having supported Lapis Semi (formerly Oki) in its first forays into the technology – and that was back in 2002! The company is on a growth run this year, having acquired four companies, including IPextreme.
FD-SOI, he said, has been shown to be cost-effective. The capacity is in place, and it’s getting design wins. Silvaco’s full suite of EDA and custom CAD tools for FD-SOI cover the complete design flow from TCAD to sign-off. Their IP is very strong, he said, especially in automotive (including CAN IP), and their partnerships with key players like IBM and NXP are long running. In fact, Silvaco commercializes IP from NXP and others.
GF: FD-SOI Primetime
We got some great insights from Gregg Bartlett, GlobalFoundries’ SVP of the CMOS Business Unit, in his presentation FDX (FDSOI) Goes Mainstream – Roadmap for Product Competitiveness (it’s posted – click here to download it). “It is primetime for FD-SOI,” he said, and since one technology does not fit all, they’re redefining the mainstream. GF’s first FD-SOI offering, 22FDX, was qualified in March, and 12FDX will be taping out in the second half of 2018. They’ve currently got over 80 active engagements.
(Courtesy: GlobalFoundries, SOI Consortium)
FD-SOI will be strong in China, he said. GF and the Chengdu municipality recently announced they are investing more than $100 million to build a world-class FD-SOI ecosystem including multiple design centers in Chengdu and university programs across China. This will lower the barriers to entry and increase IP availability even further, he said. They’re looking to put 500 design engineers in place. Customer tape-outs of 22FDX will begin at the new fab there in 2H2018, with volume production expected to start in 2019.
He went on to drill down on FDX applications, focusing on four main areas:
mobility: application processors that need high performance, RF integration and significant power reduction
IoT: this was the target when FDX was first conceived, and it continues to be a point of significant investment by the company
RF and mmWave: for BLE (Bluetooth Low Energy), WiFi, ZigBee and integrated PA’s (aka power amplifiers – where they’re seeing some impressive numbers, he said)
automotive: Grade 2 is done, and Grade 1 is underway (these are industry ratings related to reliability at the high-temperatures you get under the hood and in hotspots in the passenger compartment).
Citing a slide of customer testimonials, he concluded that the ecosystem is really starting to work, adding that they’ve got the right technology for the right applications, and it’s the right path for them to be on.
Invecas IP & Services
Invecas has been working on 22FDX since 2015 through a strategic partnership with GF. They’ve optimized IP and offer ASIC services, explained Bhaskar Kolla, the company’s Sr. Director of BizDev & Customer Engineering. His presentation, Invecas IP Portfolio in 22FDX is posted – click here to get it. It’s full of detail (standard cells, memories, analog & IO, and interface), so you’ll really want to check it out. The IPs are silicon proven and validated; the results are available, he said.
The foundation IPs are sponsored by GF, so they’re free to customers and cover a broad array of calibrations. They include forward and reverse body biasing (FBB and RBB) and body bias generator IP. Customers are really taking advantage of this, he said, citing as an example one that’s going for 2.5GHz by leveraging FBB.
Custom IP for analog & IO is a place they’re seeing a lot of interest, he continued, and on which they’re doing more and more work with clients. And their Interface IP is in a lot of silicon, especially for customers that are area sensitive. In fact, they’ve developed their own Interface IP demo platform in-house, from build through test and compliance checks.
In moving to FD-SOI, customers are seeing significant PPA improvements, he said. In one of the customer use cases for a high-level IoT product he cited, the customer requirements were easily achieved: cutting leakage in half, dynamic power consumption by roughly a third and area by 20%.
Leti: boosting at 10nm
There’s so much technical detail on performance boosters in Laurent Grenouillet’s presentation, FD-SOI: a Low Power, High Performance Technology Scalable Down to 10nm, you really just have to look at it yourself – click here to get it. A CMOS & Memory Integration Expert at Leti, he did a quick review of 28-22-14nm, then took a deep dive into the myriad of performance boosting options for 10nm, including impressive benchmarking regarding the effectiveness of mobility boosters on FD-SOI vs. FinFET.
Here are the boosters he detailed for 28-22-14nm:
(Courtesy: CEA-Leti, SOI Consortium)
Interestingly he noted that with each node, the thickness of the insulating BOX layer of the SOI wafer scales down, and as it does, back bias efficiency improves even more.
Here’s what he then covered for 10nm (and detailed with data packed in the 20 slides that followed):
(Courtesy: CEA-Leti, SOI Consortium)
FD-SOI is the sweet spot when you need lower power, lower cost, more sensing (analog), more comm (RF), more flexibility and more energy efficiency, he concluded – and he provided powerful data to back that up.
Attopsemi’s non-breaking fuse
I-fuseTM: the best OTP of Choice for FD-SOI and sub-14nm nodes was the topic of a talk by Attopsemi Technology’s Chairman, Shine Chung (you can get the ppt here). The company recently joined GF’s FDXcelerator partner program. OTP stands for one-time programmable memory, and I-fuse is different from other OTP technologies (notably NVM and e-fuses), he explained, in that it’s a non-breaking fuse with ultra-high reliability even in high-temp conditions. It’s been qualified by companies worldwide and is in volume production.
He’s a big fan of FD-SOI because it offers the best RF integration, small form factor, ULP and low cost. Want to make a cellphone as small as a watch? Then you need FD-SOI, he quipped with a tip of the hat to a Dick Tracy image. The fact that FD-SOI has a lower junction breakdown than bulk makes I-fuse the best choice for it, he said. You just program a gate as a fuse.
Get it out the door, fast!
During breaks (on both days!), everybody was talking about the terrific Product Design Methodology presentation by Christophe Tretz, the SOI Consortium’s design guru (and longtime IBM guy). In fact, Christophe has agreed to write it up for ASN in the weeks to come, so don’t miss that. You’ll want to look at the whole presentation — click here to get it. In the meantime, here are some highlights.
(Courtesy: SOI Consortium)
He suggests designers consider an incremental approach in which FD-SOI benefits accrue. “No, you don’t have to know everything about the technology to use it,” he began (especially addressing those in smaller design teams and houses). “The ecosystem is there. Everything you need to use it is there.”
He used a number of cases to explain.
Case 1: a simple, digital SOC – you get significant power savings just by reusing existing library blocks and doing minor recompile.
Case 2: RF/mixed-signal – turnaround time is very fast (Analog Bits, for example cut leakage by 5x in a port that took just three months). FD-SOI gives analog designers a great new thing to play with for big power savings – and they learn fast.
Case 3 (= Cases 1 + 2): “complex” SOC with RF blocks – rework the RF blocks, but reuse library elements for the digital part without a lot of design effort. You get significant power savings very easily.
Case 4: a more complex SOC – in this case, you optimize or customize a few blocks in the first design pass, but then optimize/customize more blocks in subsequent design passes. It just keeps getting better and better.
Case X: a fully optimized SOC. This takes more time, but you can do parts in parallel and get dramatic results – especially if you use body biasing.
He then looked at the state of the ecosystem:
three fabs are ready
we have the tools (Synopsys, Cadence, Silvaco)
the libraries are there and ready to use
“You don’t have to learn everything to get your product out the door,” he concluded. “You don’t have to do it all at once: you can do it incrementally. Within a few months, you’ll have a nice product, and as you do new products every six months, each time you can re-use, but also tune for more improvements.”
In short: just do it!
So that’s a recap of Day 1. Next post (or posts?) I’ll recap Day 2. Stay tuned!