What’s Behind the Power Savings in sureCore’s FD-SOI SRAM IP?
By Duncan Bremner, CTO SureCore Limited
Editor’s note: sureCore just announced availability of its 28nm FD-SOI memory compiler (press release here), which supports the company’s low-power, Single and Dual Port SRAM IP. Here, the company’s CTO explains why this IP is getting such impressive results.
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Recently, sureCore announced results from a 28nm FD-SOI test chip that showed dynamic power savings exceeding 75% and static power cuts up to 35% (when compared against a number of current commercial offerings), while only incurring a 5-10% area penalty for its ultra-low power SRAM IP.
And while this data is easily substantiated as shown in Figure 1, the sceptical industry pundits have raised questions that fall into two camps: (a) That can’t be done; or (b) How did they manage that? In answer to both of these questions, here’s a quick look at the history and engineering strategy that we adopted to deliver these results.
Figure 1: sureCore SRAM performance versus 5 leading IP suppliers.
Looking back to the early days of sureCore, SRAM fascinated us because despite many process iterations, the SRAM in use today bears a striking resemblance to the SRAM architectures that existed in the ’70s and ’80s. We concluded that no one had really taken a “blank-sheet-of-paper” look at the architecture for over 40 years. Recognising the growing importance of power efficiency for SoCs targeting forward-looking applications such as wearables, IoT, and other mobile devices, we examined power consumption in detail, and began by investigating how we could reduce SRAM power to a level attractive to the next generation of power critical, SoC designers.
Our starting point differed significantly from the traditional approach to SRAM R&D that typically starts at the bit cell. We recognised that the basic bit cell is fixed by the foundry; it’s a piece of electronics that is carefully optimised for fabrication. Modern bit cells are designed by the foundries who tend to put an emphasis on the broadest possible manufacturability drivers; yield and faster-time-to-volume as opposed to more performance-centric metrics. Their focus is on the front-end process optimisation, area and yield.
The basic rule of R&D fabless foundry engagement has been, “use the storage array – you won’t get a better packing density.” Consequently, the application use model had become separated from the technology — ‘faster or cheaper’ became the industry’s mantra instead of ‘faster and better’. This resulted in SRAM design teams focusing on how to build more sensitive read amplifiers to detect the signals, and better write amplifiers to drive the signal on to the bit cell. Not much time was spent looking at the fundamental architecture and asking: “Is this the best way?”
sureCore decided to take a more holistic view and stood back from the whole problem. We started with a clean sheet of paper and asked, “Where does the power go when you start storing data on SRAM?”
We discovered that a lot of the power is consumed hauling parasitic capacitance around. Our design strategy was therefore very simple; we developed a system architecture to optimize power while still retaining the area advantages of the standard foundry bit cell.
Simply stated, we architected the internal block architecture of SRAM by splitting the read amplifier function into a local and global read amplifier, thus dividing the capacitive load from the word-line, only driving the areas being addressed and not the whole array. This resulted in significant dynamic power savings during the read cycle. In a similar fashion, we reduced the write cycle power by a similar amount. Whilst hierarchical solutions are not new, the sureCore “secret sauce” is at circuit level developed by our engineering teams leading to not only significant power savings, but also comparable performance levels.
Our “blank sheet” approach delved deep; right down to the fundamental device physics level. Our strategic partners, Gold Standard Simulations — recognised world leaders in modelling devices at the atomic level and experts in nano-scale process nodes, helped us to understand the behaviour and limitations of processes at nodes below 28nm at a device level and bit cell level. Combining this fundamental device understanding with excellent circuit design and system analysis skills, we’ve identified where existing SRAM solutions waste power, and architected our solution to avoid this; we deliver power savings without the added complexity of write and read-assist.
At the outset, we determined it was important that our IP be process-independent. sureCore IP is based on architecture and circuit techniques rather than a reliance on process features. The result of this is technology that can reduce power in standard bulk CMOS, but is equally applicable to newer FinFET or FD-SOI processes and across all geometries, even down to 16nm and below. We believe our approach is paying off and, because we insisted in retaining the foundry optimised bit cell, sureCore’s technology can be retrofitted into existing designs enabling extended product life cycles.
This is our basic technology story… a start-up deciding to take a fresh look at an old technology and dramatically improving power performance over 75% compared with existing solutions. This is a new approach to SRAM power consumption for power sensitive applications and it delivers tangible battery life benefits to both the end user and the FD-SOI designers. Today’s FD-SOI technology is optimised for low power applications, bringing extended battery life to the nascent markets of wearables and IoT.
GF takes multimillion dollar GSS TCAD/EDA license
Gold Standard Simulations Ltd. (GSS) announced a multimillion dollar contract to license its complete TCAD/EDA tool suite to GlobalFoundries (see press release here). The fully integrated and automated tool chain includes GARAND, the GSS ‘atomistic’ TCAD simulator; Mystic, the GSS statistical compact model extractor; and RandomSpice, the GSS statistical circuit simulator. The GSS tool suite is the world’s only fully integrated tool chain that performs simulation-based Design/Technology Co-Optimisation (DTCO) in advanced bulk, FD-SOI and FinFET technologies, including statistical variability and reliability.
IEDM ’13 (Part 2): More SOI and Advanced Substrate Papers
SOI and other advanced substrates were the basis for dozens of excellent papers at IEDM ’13. Last week we covered the FD-SOI papers (click here if you missed that piece). In this post, we’ll cover the other major SOI et al papers – including those on FinFETs, RF and various advanced devices.
Brief summaries, culled from the program (and some of the actual papers) follow.
SOI-FinFETS
9.4 2nd Generation Dual-Channel Optimization with cSiGe for 22nm HP Technology and Beyond (IBM)
This paper about performance boosters is applicable to all flavors of SOI-based devices, including FinFET, planar FD-SOI and partially-depleted SOI. At 22nm for high-performance (HP), IBM is still doing the traditional partially-depleted (PD) SOI. At 14nm, when they go to SOI-FinFETs, one of the channel stressors to boost performance is Silicon-Germanium (cSiGe). To better understand the physics, layout effects and impact of cSiGe on device performance, IBM leveraged their 22nm HP technology to do a comprehensive study. They got a 20% performance boost and 10% Short Channel Effect (SCE) improvement, and showed that this 2nd generation high-performance dual-channel process can be integrated into a manufacturable and yieldable technology, thereby providing a solid platform for introduction of SiGe FinFet technology.
13.5 Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-Fin SOI FINFETs (GlobalFoundries, IBM)
SOI FINFETs are very attractive because of their added immunity to Vt variability due to undoped channels. However, circuit level performance also depends on the effective current (Ieff) variability. According to the advance program, “A first time rigorous experimental study of effective current (Ieff) variability in high-volume manufacturable (HVM) 14nm Silicon-On-Insulator (SOI) FINFETs is reported which identifies, threshold voltage (Vtlin), external resistance (Rext), and channel trans-conductance (Gm) as three independent sources of variation. The variability in Gm, Vtlin (AVT=1.4(n)/0.7(p) mV-μm), and Ieff exhibit a linear Pelgrom fit indicating local variations, along with non-zero intercept which suggests the presence of global variations at the wafer level. Relative contribution of Gm to Ieff variability is dominant in FINFETs with small number of fins (Nfin); however, both Gm and Rext variations dominate in large Nfin devices. Relative contribution of Vtlin remains almost independent of Nfin. Both n and p FINFETs show the above mentioned trends.”
20.5 Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs (AIST, Nissin Ion Equipment)
In this paper, the researchers thoroughly investigated the impact of the heated ion implantation (I/I) technology on HK/MG SOI FinFET performance and reliability, which it turns out is excellent. They demonstrated that “…the heated I/I brings perfect crystallization after annealing even in ultrathin Si channel. For the first time, it was found that the heated I/I dramatically improves the characteristics such as Ion-Ioff, Vth variability, and bias temperature instability (BTI) for both nMOS and pMOS FinFETs in comparison with conventional room temperature I/I.”
26.2: Advantage of (001)/<100> oriented Channel to Biaxial and Uniaxial Strained Ge-on-Insulator pMOSFETs with NiGe S/D (AIST)
In this paper about boosters in fully-depleted planar SOI and GeOI based devices, the researchers “compared current drivability between (001)/<100> and (001)/<110> strained Ge-on-insulator pMOSFETs under biaxial and uniaxial stress.” They experimentally demonstrated for the first time that in short channel (Lg < 100 nm) devices, <100> channels exhibit higher drive current than <110> channels under both the biaxial- and the uniaxial stress, in spite of the disadvantage in mobility, although this is not the case with longer channel devices. The advantage is attributable to higher drift velocity in high electric field along the direction and becomes more significant for shorter Lg devices. The strained-Ge (001)/<100> channel MOSFET have a potential to serve as pFET of ultimately scaled future CMOS.
33.1 Simulation Based Transistor-SRAM Co-Design in the Presence of Statistical Variability and Reliability (Invited) (U. Glasgow, GSS, IBM)
With ever-reducing design cycles and time-to-market, design teams need early delivery of a reliable PDK before mature silicon data becomes available. This paper shows that the GSS ‘atomistic’ simulator GARAND used in this study provides accurate prediction of transistor characteristics, performance and variability at the early stages of new technology development and can serve as a reliable source for PDK development of emerging technologies, such as SOI FinFET. Specifically, the authors report on, “…a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modeling strategy is developed for early delivery of a reliable PDK, which enables TCAD- based transistor-SRAM co-design and path finding for emerging technology nodes.”
RF-SOI
1.3: Smart Mobile SoC Driving the Semiconductor Industry: Technology Trend, Challenges and Opportunities (Qualcomm)
In this plenary presentation, Geoffry Yeap, VP of Technology at Qualcomm gave a perspective on state of the art mobile SoCs and RF/analog technologies for RF SOCs. The challenge, he said in his paper, is “…lower power for days of active use”. He cited the backgate for asymmetric gate operation and dynamic Vt control, noting that FinFETs lack an easy way to access the back gates. “This is especially crucial when Vdd continues to scale lower to a point that there is just not sufficient (Vg-Vt) to yield meaningful drive current,” he continued. While he sees FD-SOI “very attractive”, he is concerned about the ecosystem, capacity and starting wafer price.
With respect to RF-SOI, the summary of his talk in the program stated, “Cost/power reduction and unique product capability are enabled by RF front end integration of power amplifiers, antenna switches/tuners and power envelope tracker through a cost-effective RF-SOI instead of the traditional GaAs.”
Advanced Devices
Post-FinFETs, one of the next-generation device architectures being heavily investigated now is gate-all-around (GAA). While FinFETs have gate material on three sides, in GAA devices the gate completely surrounds the channel. A popular fabrication technique is to build them around a nanowire, often on an SOI substrate.
4.4 Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling (Forschungszentrum Jülich, U. Udine, Soitec)
This is a paper about a strained Si (sSi) nanowire array Tunnel FETs (TFETs). The researchers demonstrated that scaled gate all around (GAA) strained Si (sSi) nanowire array (NW) Tunnel FETs (TFETs) allow steep slope switching with remarkable high ION due to optimized tunneling junctions. Very steep tunneling junctions have been achieved by implantations into silicide (IIS) and dopant segregation (DS) with epitaxial Ni(AlxSi1-x)2 source and drain. The low temperature and pulse measurements demonstrate steep slope TFETs with very high I60 as TAT is suppressed. GAA NW TFETs seem less vulnerable to trap assisted tunneling (TAT). Time response analysis of complementary-TFET inverters demonstrated experimentally for the first time that device scaling and improved electrostatics yields to faster time response.
(image courtesy: IBM, IEEE/IEDM)
20.2 Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10 nm Node and Beyond (IBM)
Record Silicon Nanowire MOSFETs: IBM researchers described a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10-nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured an incredible 30-nm SiNW pitch (the spacing between adjacent nanowires) with a gate pitch of 60 nm. Devices with a 90-nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.
26.4 FDSOI Nanowires: An Opportunity for Hybrid Circuit with Field Effect and Single Electron Transistors (Invited) (Leti)
This paper is about nanowires and single electron transistors (SET). As indicated in the program, “When FDSOI nanowires width is scaled down to 5nm, the nanowires can encounter a dramatic transition to single electron transistor characteristics. This enables the first room temperature demonstration of hybrid SET-FET circuits thus paving the way for new logic paradigms based on SETs. Further scaling would rely on deterministic dopant positioning. We have also shown that Si based electron pumps using tunable barriers based on FETs are promising candidates to realize the quantum definition of the Ampere.”
26.6 Asymmetrically Strained High Performance Germanium Gate-All-Around Nanowire p-FETs Featuring 3.5 nm Wire Width and Contractable Phase Change Liner Stressor (Ge2Sb2Te5) (National U. Singapore, Soitec)
In this paper about GAA and nanowires, the researchers report “…the first demonstration of germanium (Ge) GAA nanowire (NW) p-FETs integrated with a contractable liner stressor. High performance GAA NW p-FET featuring the smallest wire width WNW of ~3.5 nm was fabricated. Peak intrinsic Gm of 581 μS/μm and SS of 125 mV/dec was demonstrated. When the Ge NW p-FETs were integrated with the phase change material Ge2Sb2Te5 (GST) as a liner stressor, the high asymmetric strain was induced in the channel to boost the hole mobility, leading to ~95% intrinsic Gm,lin and ~34% Gm,sat enhancement. Strain and mobility simulations show good scalability of GST liner stressor and great potential for hole mobility enhancement.”
III-V, More Than Moore and Other Interesting Topics
28.5 More than Moore: III-V Devices and Si CMOS Get It Together (Invited) (Raytheon)
This is continuation of a major ongoing III-V and CMOS integration project that Raytheon et al wrote about in ASN five years ago (see article here). As noted in the IEDM program, the authors “…summarize results on the successful integration of III-V electronic devices with Si CMOS on a common silicon substrate using a fabrication process similar to SiGe BiCMOS. The heterogeneous integration of III-V devices with Si CMOS enables a new class of high performance, ‘digitally assisted’, mixed signal and RF ICs.
31.1 Technology Downscaling Worsening Radiation Effects in Bulk: SOI to the Rescue (Invited) (ST)
In this paper, the authors explore the reliability issues faced by the next generation of devices. As they note in the description of the paper in the program, “Extrinsic atmospheric radiations are today as important to IC reliability as intrinsic failure modes. More and more industry segments are impacted. Sub-40nm downscaling has a profound impact on the Soft Error Rate (SER) of BULK technologies. The enhanced resilience of latest SOI technologies will fortunately help leveraging existing robust design solutions.”
13.3 A Multi-Wavelength 3D-Compatible Silicon Photonics Platform on 300mm SOI Wafers for 25Gb/s Applications (ST, Luxtera)
Luxtera’s work on Silicon Photonics and now products based on integrated optical communications has been covered here at ASN for years. In this paper Luxtera and ST (which now is Luxtera’s manufacturing partner) present a low-cost 300mm Silicon Photonics platform for 25Gb/s application compatible with 3D integration and featuring competitive optical passive and active performance. This platform aims at industrialization and offering to system designers a wide choice of electronic IC, targeting markets applications in the field of Active optical cables, optical Modules, Backplanes and Silicon Photonics Interposer.
The graph above shows the high electron mobility of Triangular MOSFETs with InGaAs Channels. (Image courtesy: AIST, IEEE/IEDM)
2.2. High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures (AIST, Sumitomo, Tokyo Institute of Technology)
InGaAs is a promising channel material for high-performance, ultra-low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration. A research team led by Japan’s AIST built triangular InGaAs-on-insulator nMOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30 nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 μA/μm at a 300-nm gate length, showing they have great potential for ultra-low power and high performance CMOS applications.
16.4. High performance sub-20-nm-channel-length extremely-thin body InAs-on-insulator Tri-gate MOSFETs with high short channel effect immunity and Vth tenability (Sumitomo, Tokyo Institute of Technology)
This III-V paper investigates the effects of vertical scaling and the tri-gate structure on electrical properties of extremely-thin-body (ETB) InAs-on-insulator (-OI) MOSFETs. “It was found that Tbody scaling provides better SCEs control, whereas Tbody scaling causes μfluctuation reduction. To achieve better SCEs control, Tchannel scaling is more favorable than Tbuffer scaling, indicating QW channel structure with MOS interface buffer is essential in InAs-OI MOSFETs. Also, the Tri-gate ETB InAs-OI MOSFETs shows significant improvement of short channel effects (SCEs) control with small effective mobility (μeff) reduction. As a result, we have successfully fabricated sub-20-nm-Lch InAs-OI MOSFETs with good electrostatic with S.S. of 84 mV/dec, DIBL of 22 mV/V, and high transconductance (Gm) of 1.64 mS/μm. Furthermore, we have demonstrated wide-range threshold voltage (Vth) tunability in Tri-gate InAs-OI MOSFETs through back bias voltage (VB) control. These results strongly suggest that the Tri-gate ETB III-V-OI structure is very promising scaled devices on the Si platform to simultaneously satisfy high performance high SCE immunity and Vth tunability.”
11.1 A Flexible Ultra-Thin-Body SOI Single-Photon Avalanche Diode (TU Delft)
This is a paper on flexible electronics for display and imaging systems. “The world’s first flexible ultra-thin-body SOI single-photon avalanche diode (SPAD) is reported by device layer transfer to plastic with peak PDP at 11%, DCR around 20kHz and negligible after pulsing and cross-talk. It compares favorably with CMOS SPADs while it can operate both in FSI and BSI with 10mm bend diameter,” say the researchers.
11.7 Local Transfer of Single-Crystalline Silicon (100) Layer by Meniscus Force and Its Application to High-Performance MOSFET Fabrication on Glass Substrate (Hiroshima U.)
In this is a paper on flexible electronics for display and imaging systems, the researchers “…propose a novel low-temperature local layer transfer technique using meniscus force. Local transfer of the thermally-oxidized SOI layer to glass was carried out without any problem. The n-channel MOSFET fabricated on glass using the SOI layer showed very high mobility of 742 cm2V-1s-1, low threshold voltage of 1.5 V. These results suggest that the proposed (meniscus force-mediated layer transfer) technique (MLT) and MOSFET fabrication process opens up a new field of silicon applications that is independent of scaling.”
Note: the papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.
Special thanks to Mariam Sadaka and Bich-Yen Nguyen of Soitec for their help and guidance in compiling this post.
At 14nm FD-SOI’s 30-40% Cheaper than Intel’s Technology, Says GSS CEO
“At 14nm FD-SOI is much cheaper, 30-40% cheaper, than Intel’s technology,” Asen Asenov told David Manners in a recent Electronics Weekly post (see full post here). Asenov is CEO and Founder of Gold Standard Simulations (GSS). The subject of the post was how TSMC has turned to GSS for statistical analysis tools. Professor Asenov is a fan of ST’s FD-SOI, noted Manners. The main challenge is building the ecosystem, he concluded.
Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant from the Technology Strategy Board SMART
Targeting low-power SRAM for FD-SOI and FinFETs, UK physical IP start-up sureCore has received a £250K grant (about 292K Euros or $380.5K) from the Technology Strategy Board SMART. Working with the major foundries developing FD-SOI and FinFET technologies, the grant will be used in the development of a demonstrator chip to showcase sureCore’s patented array control and sensing scheme, which significantly lowers active power consumption. Through a combination of detailed analysis and using advanced statistical models, sureCore has designed an SRAM memory consuming less than half the power of existing solutions. SureCore is working closely with Gold Standard Simulations (GSS) Ltd. (GSS Founder/CEO Asen Asenov is a sureCore director).
GSS has declared, “Metal-gate-first FD-SOI will be very good but metal-gate-last could be spectacular
Following investigations and simulations, GSS has declared, “Metal-gate-first FD-SOI will be very good but metal-gate-last could be spectacular.” “…the technologist who that could develop and deliver metal-gate-last FD-SOI at 28nm will be able to offer you supply voltage below 0.5V,” they explained. They also noted, “The statistical variability introduced by the random discrete dopants in the FD-SOI MOSFETs is significantly lower compared to bulk MOSFETs with equivalent dimensions.”
Spotlight on FD-SOI & FinFETs at Upcoming IEEE SOI Conference
(1-4 Oct. in Napa – register by 17 Sept. for best rate)
The 38th annual SOI Conference is coming up in just a few weeks. Sponsored by IEEE Electron Devices Society, this is the only dedicated SOI conference covering the full technology chain from materials to devices, circuits and system applications.
Chaired this year by Gosia Jurczak (manager of the Memories Program at imec), this excellent conference is well worth attending. It’s where the giants of the SOI-related research community meet the leading edge of industry. But there are also excellent courses for those new to the technology. And it’s all in an atmosphere that’s at once high-powered yet intimate and collegial, out of the media spotlight.
The 2012 IEEE SOI Conference will be held October 1-4 at the Meritage Resort and Spa in Napa Valley, California.
(Photo Credit: Rex Gelert)
This year it will be held 1-4 October at the Meritage Resort and Spa, a Napa Valley luxury hotel and resort, set against rolling hills with its own private vineyards. Finding the right spot for this conference is key. One of the things that people really like about it is that in addition to the excellent speakers and presentations, the locations are conducive to informal discussions and networking across multiple fields. This year’s spot looks like the perfect setting, with easy access to Silicon Valley.
The Conference includes a three-day Technical Program, a Short Course, a Fundamentals Class, and an evening Panel Discussion. Here’s a look at what’s on tap for this year.
(To register at the discounted rate, be sure to send in your registration by September 17th. You can get the pdf of the full program & registration information from the website.)
The papers
ARM’s SOI guru Jean-Luc Pelloie chaired this year’s Technical Program committee, which selected 33 papers for the technical sessions. There will also be 18 invited talks given by world renowned experts in process, SOI device and circuits design and architectures and SOI-specific applications like MEMS, high temperature and rad-hard.
Here’s a rundown of the sessions:
- Plenary: talks by Soitec and ARM
- Fully–Depleted SOI: topics include Ground Plane Optimization for 20nm, strain, process & design considerations. GF will present the foundry’s perspective on the move to 28nm FD-SOI and beyond. Also contributors from ST, Leti, Soitec, IBM, GSS/U.Glasgow and more.
- FinFET and Fully Depleted SOI: topics include Tri-Gate, SOI-FinFET, Flash Memory, strain solutions, flexible Vth. Contributors include Leti, AMD, Soitec, Synopsys, imec, UCL, AIST and UCBerkeley.
- Poster session: from universities & research institutes supported by industry (IBM, Samsung, etc.)
- RF and Circuits: topics include high-performance RF, tunable antennas, TSVs. Contributors include Skyworks, ST, Xilinx and leading universities in China.
- Memory: contributors from IMEP, ST, TI, R&D institutes and academia
- Novel Devices and Substrate Engineering: topics include nanowires, strained SOI wafers and III-V devices, with contributions from Tokyo Tech, Toshiba, IBM, Soitec, Leti and more.
- MEMS and Photonics: includes an invited talk by U. Washington on their Intel-sponsored photonics foundry service and papers from MIT and more.
- RF and Circuits: covering high-voltage, high-temperature, with contributions from Cissoid, IBM, UCL and more.
- Hot Topics: Fully–Depleted Technology and Design Platforms: six invited talks by ST, IBM, CMP, GF, UC Berkeley and the SOI Consortium.
- Late News: tbd, of course…
The courses & panel
Short course: Design Enablement for Planar FD & FinFET/Multi-gates (chaired by UCL & Leti) The conference kicks off on Monday with six sessions by experts in technological trends, the physics of fully depleted devices, technology design kits as well as digital, analog and RF designs specific for FD-SOI.
The fundamentals course: FinFET physics (chaired by Intel): on Wednesday afternoon, three hour-long sessions will give comprehensive insights into the physics and processes related to multi-gate FETs.
Panel: Is FinFET the only option at 14nm? (chaired by Soitec) Following the always-popular Wednesday evening cookout, the panel discussion is a lively favorite event. This year’s invited distinguished experts will share their views on the industry’s FinFET roadmap.
All in all, it’s a great event. If you go, why not share your impressions on Twitter with #SOIconf12, @followASN and @IEEEorg? And of course ASN will follow-up with summaries of the top papers in our PaperLinks section. See you there?
Power & Performance: GSS Sees SOI Advantages for FinFETS
Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere. But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.
The GSS IEDM ’11 Paper
GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks. The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones. Then they also need to provide reliable models to designers who will use them before committing chips to silicon. One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs. This covered “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”. Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project. It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
- A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”. Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
- The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.
The Blogs
A few months later, when Chipworks published pictures of the (bulk silicon) Intel 22nm FinFETs, the folks at GSS started a series of blogs that caught the attention of major tech pubs such as EE Times, Electronics Weekly and EDN. For reference, here are the blogs and basically what they concluded:
- Simulation analysis of the Intel 22nm FinFET (9 May ’12) – using their TCAD simulator GARAND, GSS found the essentially triangular (rather than a rectangular) shape “contributed to worsening of short-channel effects (SCE)”
- Process-induced variability in the Intel FinFETs (6 June ’12) – continued the analysis by looking at process variability, and concluded that there was “a reduction in the on-current by 12-15% compared to rectangular-gate bulk FinFETs”
- FD SOI FinFETS can offer better performance than bulk FinFETs (27 July ’12) asked:
“Assuming that you can make ideal rectangular bulk and SOI FinFETs, which one will have better performance?” The answer: SOI.
Specifically, the July 27th blog indicated that if FinFETs are rectangular in shape, drive current would be 12-15% better. Would that be easier to do on an SOI wafer? Soitec has argued that their “fin-first” SOI-based approach to FinFET manufacturing will save both time & money while getting better results (see Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET in Semiconductor Manufacturing & Design).
The GSS blog also reminded readers that the company’s CEO and founder, Asen Asenov (an extremely heavy hitter who’s published over 550 papers), has hinted that “…SOI FinFETs with an almost ideal rectangular shape may be a better solution for future FinFET scaling”. GSS has noted previously that “FinFETs built on an SOI substrate could have significant advantages terms of simpler processing, better process control and reduced statistical variability”.
Fin shape aside, GSS said that by virtue of the layer of insulation, SOI would give another 5% boost to FinFET drive current. But perhaps more importantly, that layer of insulation in SOI-based FinFETs would deliver on average 2.5 times less leakage – which would translate into a doubling of battery-life for your cell phone.
Next project
IBM has now entered into an agreement with GSS et al on a project called StatDES, for Statistical Design and Verification of Analogue Systems – see last month’s IBM blog by IBM Research Scientist Dr. Sani Nassif, entitled “Fins on transistors change processor power and performance”.
Dr. Nassif writes, “IBM, University of Glasgow and the Scottish Funding Council are collaborating on a project to simulate 3D microprocessor transistors at a mere 14 nanometer scale (the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator (SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES, promises to keep improving microprocessor performance and energy conservation.”
The steering group also includes folks from ST, Freescale, Wolfson and Cadence, so one would guess we’ll be hearing more from this project – and others like it, to be sure – in the future, wouldn’t you think?