Tag Archive high-perf


GlobalFoundries and Synopsys Streamline the Move to 22nm FD-SOI

By: Tamer Ragheb, Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys

It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT).

GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 1_Benefits of 22FDX body-biasing

Figure 1: Benefits of 22FDX body-biasing

The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode.

GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 2_22FDX Body Bias Optimizes Performance and Power

Figure 2: 22FDX Body Bias Optimizes Performance and Power

In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include:

  • Improved electrostatic control of the transistor acts as a performance booster and enables lower VDD (i.e., lower power consumption) while reaching significant performance
  • Low variability and body-biasing capability that can achieve 0.4 volt operation
  • Complete RF enablement with ‘knobs’ to reduce RF power by up to 50 percent

Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs.

There are four application optimized extensions available with 22FDX (Fig. 3). These are:

  • 22FDX ULP- an ultra low-power extension that provides logic libraries and memory compilers that are optimized for 0.4 volt operation.
  • 22 FDX ULL- an ultra low-leakage extension that brings in an expanded device suite capable of achieving one pico-amp per micron leakage.
  • 22 FDX UHP- an ultra high-performance extension that leverages the overdrive capabilities and body-biasing features to maximize the performance of technologies in a turbo or a burst mode. It has high performance libraries and high speed interfaces and BEOL stacks optimized for competing architectures or applications.
  • 22 FDX RFA- an RF and analog extension that brings in full characterization and enablement for RF applications, including optimized RF layouts and P cells, BEOL passives, and IP for Bluetooth LE and WIFI applications.
GLOBALFOUNDRIES and Synopsys Streamline the Move to 22nm FD-SOI_Fig. 3_22FDX Platform and Extensions

Figure 3: 22FDX Platform and Extensions

GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications.

GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction.

Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include:

  • Design Compiler® Graphical synthesis with IEEE 1801 (UPF) driven bias-aware multi-corner multi-mode (MCMM) optimization
  • Formality® formal verification with bias-aware equivalence checking
  • IC Compiler™ and IC Compiler II™ layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation
  • StarRC™  parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF)
  • PrimeTime® timing analysis and signoff including distributed multi-scenario analysis (DMSA) static timing and noise analysis, using AOCV and POCV technology
  • IC Validator In-Design physical verification

The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.


GF’s 22nm FD-SOI Offering – Where to Get Lots of Excellent Info

A fast-growing body of information is now posted by GlobalFoundries on their new 22nm FD-SOI offering.

After years of asking “where’s FD-SOI on the GF website??”, it’s (finally!) there, front and center. There are some excellent new videos and documents. Here’s a rundown of what you’ll find.


The 22FDX Platform introduction is the currently the lead topic on the GlobalFoundries website.

When you click down the “Technology Solutions” tab and select “Leading Edge Technologies”, here’s how they describe their 22nm FD-SOI offering:

GLOBALFOUNDRIES 22FDX™ platform employs 22nm Fully-Depleted Silicon-On-Insulator (FD-SOI) technology that delivers FinFET-like performance and energy-efficiency at a cost comparable to 28nm planar technologies. While some applications require the ultimate performance of three-dimensional FinFET transistors, most wireless devices need a better balance of performance, power consumption and cost. 22FDX provides the best path for cost-sensitive applications. The 22FDX platform delivers a 20 percent smaller die size and 10 percent fewer masks than 28nm, as well as nearly 50 percent fewer immersion lithography layers than foundry FinFET.

  • Ultra-low power consumption with 0.4V operation
  • Software-controlled transistor body-biasing for flexible trade-off between performance and power
  • Integrated RF for reduced system cost and back-gate feature to reduce RF power up to ~50%
  • 70% lower power than 28HKMG

Here are some of the resources posted on the website as of this writing:

Product Brief: 22FDX™ – a two-page pdf summarizing the platform advantages, the various application-optimized offerings, and basic graphics explaining how body-biasing works and what advantages it provides

FD-SOI Technology Innovations Extend Moore’s Law (white paper) – NEW! Just posted in September 2015, this 8-page white paper covers the basics of the FD-SOI transistor, how body biasing works, the impact the technology has on common circuit blocks (digital, analog & RF, embedded SRAM), and the outlook for future scaling (which goes down to 10nm).


This slide is about 17 minutes into GF’s “How to build ULP chips with 22nm FD-SOI…” webinar.

Webinar: How to Build Ultra Low Power Chips with New 22nm FD-SOI TechnologyNEW! Just posted on September 24, 2015. GF’s Jamie Schaeffer, Ph.D. Leading Edge Product Line Manager is talking to designers here. After a brief overview (he looks at the features, the extensions, the IP suite, and so forth), he gets into the fundamentals of body biasing, the different transistor optimizations, specific advantages for RF & analog, the tools for ultra-low-power design, and what’s in the design starter kits that are available today. Total running time is just under 20 minutes.


This slide is shown about 12 minutes into GF’s “Extending Moore’s Law with FD-SOI” webinar.

Webinar: Extending Moore’s Law with FD-SOI Technology – this is the webinar Jamie Schaeffer gave with ChipEstimate.com the day of the company’s FD-SOI announcement in July 2015. It’s a fairly high level presentation: very useful for designers, but also accessible to those outside the design community. There’s a lot of background on FinFET vs. FD-SOI, cost comparisons, target apps, and actual results seen in silicon. It’s an especially good place to start if FD-SOI is new to you. It runs just over 35 minutes.

Tech Video: Benefits of FD-SOI Technologies – in this short video by Subi Kengeri, GF’s VP of the CMOS Platforms BU, he gives a quick rundown of the benefits of FD-SOI. It runs about 2 minutes.

Another excellent place to get more indepth info on FD-SOI is an interview with Subi Kengeri by SemiEngineering Editor-in-Chief Ed Sperling (click here to see it on YouTube). This video, entitled Tech Talk: 22nm FD-SOI, was made just after the July announcement. Subi really goes into substantial detail, and clearly explains the key differences between FinFETs and FD-SOI. He explains why FD-SOI has less variability than FinFETs, why FinFETs have higher device capacitance, and how only with FD-SOI can you dynamically change Vt. FD-SOI also comes out better in terms of dynamic power, thermal budget and RF integration. Highly recommended – it runs just over 20 minutes.

You might also want to check out GF CEO Sanjay Jha’s Shanghai FD-SOI Forum presentation, The Right Technology at the Right Time, on the SOI Consortium website. (There are lots of others there, too!) Taking a bird’s eye view of the semiconductor industry drivers and requirements, he concludes, “22FDX and RFSOI have the power, performance, and cost to drive growth in mobile, pervasive, and intelligent computing.”

Which is great news for the SOI ecosystem and the entire industry.

ByGianni PRATA

IBM Photonics (That’s SOI!) Ready for Cloud, Big Data Apps


Cassette carrying several hundred chips intended for 100 Gb/s transceivers, diced from wafers fabricated with IBM SOI-CMOS Integrated Nano-Photonics Technology. The dense monolithic integration of optical and electrical circuits and the scalable manufacturing process provide a cost-effective silicon photonics interconnect solution, suitable for deployment in cloud servers, datacenters, and supercomputers. (US quarter coin shown for scale.) (Courtesy: IBM)

For the first time, IBM engineers have designed and tested a fully integrated wavelength multiplexed silicon photonics chip, which the company says will soon enable manufacturing of 100 Gb/s optical transceivers (read the press release here). This will allow datacenters to offer greater data rates and bandwidth for cloud computing and Big Data applications.

Early in the program (back in 2007), IBM contributed a piece to ASN about why their photonics program is on SOI – you can read that here. (Most all photonics — except the lasers — are on SOI. You can read more ASN photonics pieces from Intel and others here.)

Silicon photonics greatly reduces data bottlenecks inside of systems and between computing components, improving response times and delivering faster insights from Big Data. IBM’s breakthrough enables the integration of different optical components side-by-side with electrical circuits on a single silicon chip using sub-100nm semiconductor technology.

IBM’s silicon photonics chips uses four distinct colors of light travelling within an optical fiber, rather than traditional copper wiring, to transmit data in and around a computing system. In just one second, this new transceiver is estimated to be capable of digitally sharing 63 million tweets or six million images, or downloading an entire high-definition digital movie in just two seconds.

IBM presented details at the recent 2015 Conference on Lasers and Electro Optics.

ByGianni PRATA

New Semico Study on SOI Apps, Opps & Markets

Research and consulting group Semico has issued a new report entitled SOI Update 2015: Finding New Applications (for information on getting a copy of the report, click here). As described on the Semico website: “With the recent growth in RF-SOI for switches and integrated solutions for RF functions such as power amplifiers and transceivers, the opportunities for growth in SOI wafer demand have once again garnered a lot of attention. In addition, as the industry transitions to very complex and expensive finFET technology, SOI is providing a high performance, low power option to semiconductor vendors who do not want take on the challenges of finFETs. This report explores the markets, products and outlook for SOI wafer adoption over the next five years.”

ByGianni PRATA

28nm FD-SOI cryptocurrency ASIC first to debut in silicon, surpasses expectations with 0.45V operation

(Courtesy: SFARDS)

SFARDS’ SF3301 cryptocurrency ASIC is the world’s first chip to use 28nm FD-SOI. Surpassing expecttions, it operates at a stunning 0.45V. (Courtesy: SFARDS)

Right on schedule, the SFARDS cryptocurrency ASIC on 28nm FD-SOI has made its debut in silicon, and is surpassing expectations. In what is clearly a stunning success, the company announced that the ASIC’s lowest working voltage is 0.45V. This means it operates stably at a power supply voltage that’s about half that of competing 28nm offerings.

An article published on the SFARDS website (see the whole thing here) said, “Using the latest in FD-SOI processing technology, SFARDS has successfully completed its 28nm SF3301 dual-algorithm ASIC chip. The SF3301 is the world’s first chip to use this manufacturing process and is at the same time the world’s first 28nm dual-algorithm (SHA-256 & Scrypt) chip, capable of mining these two algorithms simultaneously or singularly.

“SFARDS’ SF3301 fully utilizes the advantages of the FD-SOI technology. This brings increased forward body bias; the chip is operational at lower voltage while maintaining a higher frequency. The chip boasts impressive power efficiency while affording high hash power, allowing for much lower wastage per hash. The ASIC’s lowest working voltage is 0.45V.”

As noted in ASN’s Buzz in March 2015 (read it here), cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips.  As well-explained in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.

ByGianni PRATA

28nm FD-SOI Cryptocurrency Mining ASIC tapes out, to debut April 2015

Cryptocurrency mining hardware company SFARDS is preparing to release its debut miner, which is built on a 28nm FD-SOI ASIC, by April 2015. (You can read the announcement here.)

At the time of this post, tape out of the company’s SF3301ASIC has been announced as complete. Cryptocurrency (the best-known example of which is Bitcoin) depends on “ledgers” supported by bitcoin “mining” chips.  As noted in an arstechnica piece (read it here), while some Bitcoin mining is done on CPUs and GPUs, serious mining requires much faster and lower power ASICs in the hardware.

As posted on the SFARD blog, “By using FDSOI technology not currently present in any other chip on the market, power efficiency when mining with SHA-256 is predicted to reach below the 0.3 J/GH range, and 2.0 J/MH when mining with Scrypt.

“The SF3301 is extremely versatile, allowing you to mine multiple currencies with one device. This means price fluctuations can be harnessed and being forced to turn off your miner is far less likely.

“A condition can arise where altcoins are utilized to cover electricity costs while bitcoin is continuously and simultaneously being mined. This ability is something never seen before with 28nm technology.”

ByGianni PRATA

IBM z13, world’s fastest microprocessor – on SOI, of course!

A 22nm SOI chip is at the heart of IBM’s new z13 mainframe, one of the most sophisticated computer systems ever built. (Augusto Menezes/Feature Photo Service for IBM)

A 22nm SOI chip is at the heart of IBM’s new z13 mainframe, one of the most sophisticated computer systems ever built. (Augusto Menezes/Feature Photo Service for IBM)

The recently announced IBM z13, which is billed as the world’s fastest microprocessor, is built on SOI (of course!) (read the press release here).

At the heart of the latest in the IBM z-series of mainframes, the chip is manufactured in 22nm SOI (partially depleted). IBM says it is 2X faster than the most common server processors, has 300 percent more memory, 100 percent more bandwidth and vector processing analytics to speed mobile transactions. As one of the most sophisticated computer systems ever built, the z13 is the first system able to process 2.5 billion transactions a day, enabling transaction analysis in “real time” to help prevent fraud as it is occurring, allowing financial institutions to halt the transaction before the consumer is impacted.

IBM says the z13 lowers the cost of running cloud. For compared environments, it is estimated that a z Systems cloud on a z13 will have a 32 percent lower total cost of ownership over three years than an x86 cloud and a 60 percent lower total cost of ownership over three years than a public cloud.

The z-series has been on SOI since it first launched in 2003.


Successful RF-SOI 2014 International Symposium Held in Shanghai

A very successful international workshop on RF-SOI was held in Shanghai earlier this fall.  Jointly organized by industry leaders, it brought together world-class players in RF to discuss the opportunities and challenges in rapid development of RF applications.Sponsors included the SOI Industry Consortium, the Chinese Academy of Sciences (CAS) / Shanghai Institute of Microsystem and Information Technology (SIMIT), Shanghai Industrial μTechnology Research Institute Co.,Ltd. (SITRI) and VeriSilicon.

The first talk, given by Dr. Xi Wang, Academician of CAS and Director General of SIMIT, covered China’s huge market prospects for RF applications. RF-SOI, he noted, is an area in which Shanghai Simgui Technology Co.,Ltd. ,  a spin-off company from SIMIT,  and French SOI wafer manufacturer Soitec are working closely to explore the market opportunities now. He also presented some of the latest research findings and the industry dynamics in this field.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.

Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) giving the first talk at the 2014 International RF-SOI Workshop.


Next, Handel Jones, CEO of IBS, gave a detailed analysis of the markets for smart phones and tablet PCs and other mobile consumer applications. These are strong drivers of the huge market opportunity and demand for chips based on RF-SOI technology. (Click here to view his presentation.)


(Courtesy: IBS)

(Courtesy: IBS)

This workshop also featured presentations by ST, GlobalFoundries and SMIC, as well as several important RF-SOI platform providers.

Mark Ireland, Vice President of Strategy and Business Development at the IBM Microelectronics Division, noted that that IBM first began offering RF-SOI manufacturing in 2006.  He explained the key role RF-SOI plays in redefining chips for mobile applications, where integration and performance are key. (Click here to view his presentation.)

Laura Formenti, Infrastructure and RF-SOI Business Unit Director at STMicroelectronics, gave a detailed analysis of RF-SOI. She covered the advantages of RF front-end integration and introduced ST’s H9SOI_FEM technology platform. (Click here to view her presentation.)

Paul Colestock, Sr. Director of Segment Marketing at GlobalFoundries shared specifics and the latest developments in the 130nm RF-SOI technology platform, UltraCMOS 10.


The room was full at the Shanghai RF-SOI Workshop 2014

The room was full at the Shanghai RF-SOI Workshop 2014


Herb Huang, Sr. Director Development, Technology R&D at SMIC, China’s largest foundry, addressed SOI in RF switches. He shared details on SOI NFETs for enhanced performance, and on CMOS MEMS RF filters. SOI CMOS will facilitate integration of switches (SW), power amplifiers (PA), envelope tracking (ET) and antenna tuning (AT) in SoCs. The foundry provides not only device-level processes but also support for high-performance system-in-package (SiP) solutions at the wafer level.

Professor Jean-Pierre Raskin of the Catholic University of Leuven (Belgium) and Bernard Aspar, General Manager of Soitec’s Communication & Power Business Unit presented detailed technical analyses of SOI substrates.  They covered the influence of substrates on RF signal integrity and the key role they play in improving RF performance thanks to the enhanced Signal Integrity (eSI™) High Resistivity SOI substrate.  (Click here to view the UCL presentation, and here to view the Soitec presentation.)

James Young, VP of Engineering, FES Si Platform Engineering at Skyworks focused on RF and wireless semiconductor design. In particular he addressed mobile phone design, including PA, ET and APT (Average Power Tracking). He gave performance comparisons and analysis for SOI/CMOS vs. GaAs devices.  (Click here to view the presentation.)

Dr. Yumin Lu, VP of the Shanghai Industrial μTechnology Research Institute Co.,Ltd. elaborated on how 4G wireless communications brings new challenges for RF front-end modules and components. RF-SOI has become a mainstream technology for antenna/switches. There is also significant potential for RF-SOI to make further inroads in applications such as tunable components (including antennas, PAs, filters/duplexers, etc.). (Click here to view the presentation.)


Roundtable Discussion at the 2014 International RF-SOI Workshop in Shanghai

The final panel discussion session on the “China RF market” started a lively debate. Topics included the specificities and drivers of the China RF market, Chinese foundry capacity, the RF-SOI supply chain, RF front-end module (FEM) system packaging and system integration trends, and LTE and WiFi common platforms on RF-SOI substrates.  Audience members had questions about device design. The need for the industry to establish a broader ecosystem was a common theme.

 ~ ~ ~

Editor’s note: This article was first posted in Chinese at Shanghai Institute of Micro-Technology Industry Views. You can see the original hereMany thanks to Xi Wang, Academician and Director General of the Shanghai Institute of Microsystem and Information Technology (SIMIT) /Chinese Academy of Sciences (CAS) for his permission to translate/adapt and reprint it here in ASN.


Is China Interested in FD-SOI? You bet.

At the recent FD-SOI Forum in Shanghai, the IoT (Internet of Things) was the #1 topic in all the presentations.

The event was sponsored by the SOI Consortium, the Shanghai Institute of Microsystem and Information Technology / Chinese Academy of Sciences (SIMIT/CAS), and VeriSilicon. By all accounts it was a great success. Speakers included experts from Synopsys, ST, GF, Soitec, IBS, Synapse Design, VeriSilicon, Wave Semi and IBM (see below for key slides and links to the full presentations). The goal was to gather IC industry decision makers, technology owners, opinion leaders and market analysts to exchange and assess the opportunities that FD-SOI technology brings in terms of ultra-low power operation at high performance for mobile and IoT.


A panel discussion during the SOI Consortium's Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

A panel discussion during the SOI Consortium’s Shanghai FD-SOI Forum brought whole ecosystem onto same stage – a clear sign of FD-SOI becoming mainstream solution. (Courtesy: SOI Consortium)

Here are some of the points made by the speakers:

  • FinFET is a tough (Intel is running 15 months behind) and capex consuming technology (exponential situation in terms of costs), so not everybody will be able to go for it
  • FD-SOI will be a game changer
  • the FD-SOI ecosystem is now ready but industry still seems a bit too conservative to get started
  • FD-SOI is a great opportunity for China to take the lead
  • need a big fabless house with a high-volume application and then foundries building capacity
  • promising outlook: designs are underway; in 6 to 9 months there could be significant volumes. It is no longer a question of why FD-SOI – now we are at when FD-SOI.
  • 28nm will be a long lifetime technology node (2012-2024)
  • IoT: a good opportunity for FD-SOI
  • work is being done by the ecosystem to improve FD-SOI IP
  • FD-SOI is not only for 28nm but also 20/22nm and 14nm (ST discussed its 14nm FD-SOI)
  • the industry acknowledges ST and Soitec’s commitment to developing FD-SOI technology

We know that FD-SOI 28nm has moved into the manufacturing and volume production phase. It offers the chip industry the unique features of being able to fabricate at competitive cost, ultra low power, high speed ICs. It is a game changer technology platform that brings new powerful elements to the designers and a strong differentiation potential at IC and system level. But the speakers acknowledged that challenges remain, in particular that there’s a need for a greater commitment from industry and for very big customers (but that’s going to change).


The presentations

Here are brief summaries of the presentations. Click on the presentation names to download the full pdfs, or on the slides for enlarged images.

Market Overview and Opportunities by Handel Jones, CEO, International Business Strategies

Starting from a bird’s-eye view of the world, this presentation then zooms down deep into the nitty-gritty of chip manufacturing costs. Considering the various technology options for current and future nodes, it looks at costs per gate and per wafer, costs for design and for tooling, yield impact and fab life. The world’s largest chip consumer, China currently imports about 90% of the chips used there. The government has targeted 2020 as the year by which Chinese semiconductor companies should be supplying 40% of semiconductors consumed in China. IBS sees FD-SOI as the most astute choice, especially for IoT.

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)

Slide 5 from the IBS presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBS)


FD-SOI Technology by Laurent Remont, VP Technology & Product Strategy, STMicroelectronics

This presentation gives an overview of FD-SOI technology, roadmaps and markets. One of the points made is that 28nm will be the longest process generation with the highest volume manufacturing. FD-SOI extends the 28nm offering with improved power and performance rivaling existing 20nm bulk.

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 13 from the first ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)


Design with FD-SOI, Innovation Through Collaboration by Marco Casale-Rossi, Product Marketing Manager, Synopsys

The Synopsys presentation detailed FD-SOI/EDA readiness, with illustrations from an ST design. Among the many impressive results, time-to-good-floorplan was reduced 10x, and leakage was reduced by 59% through advanced EDA in the flow.

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)

Slides 20 and 34 from the Synopsys presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synopsys and ST)


Designing with FD-SOI for Power Efficiency by Haoran Wang, Associate General Manager, Synapse Design China

Synapse Design is an industry leader in design services for most top tier semiconductor and system companies around the world. They have been working on designs in FD-SOI for over four years. In fact, they’ve already had four tapeouts in FD-SOI and are working on three others. The presentation noted that “…FD-SOI has more degrees of freedom than bulk” conferred by device physics. They recommend starting with a deep power analysis at RTL, looking carefully at performance requirements vs. battery life. They conclude, “At 28nm, FDSOI does show the benefits of speed/power advantage. It is a viable solution from technology point of view and easy to be integrated in current design flow.”


Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)

Slide 2 from the Synapse Design presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: Synapse Design)


Leveraging FD-SOI to Achieve Both Low Power AND High Speed by Pete Fowley, CEO, Wave Semiconductors

Wave is a fabless semiconductor startup “commercializing a programmable solution addressing power, concurrency, design time, design cost, and deep submicron challenges facing the semiconductor market.” The founders come from a veritable who’s who industry background* (the CEO was one of the first members of Apple’s original Mac chip design team). They bill their FD-SOI based Wave Threshold Logic (WTL) as their “secret sauce”. WTL can use both very fast flip-well LVT devices with Forward Body Bias (FBB) and Standard VT devices that have very low leakage through very high Reverse Body Bias (RBB). According to Wave, “WTL‐ BB represents a unique differentiator for FD‐SOI: enabling significant performance and power advantages over bulk processes. This strategic advantage will persist into deeper nodes.” Clearly one to watch!


The FD-SOI Technology for Energy Efficient SoCs by Giorgio Cesana, Director of Marketing, STMicroelectronics

Here ST gives a FD-SOI primer, explaining the technology, design considerations and Forward Body Bias (FBB) use and results. Examples from both fast CPU/GPU and ultra-low power designs are given.

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

Slide 19 from the second ST presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: ST)

SOI Ecosystem – Strategic Opportunity for China by Tom Reeves, VP Technology Alliance, IBM

The SOI ecosystem is a central theme in this presentation. It has a long history of producing successful ICs, and the SOI enabled device structure pipeline continues through 7nm. IBM sees big opportunities for China in mobile, automotive, industrial, IoT, wearable and other More-than-Moore apps. The call to action is clear: now is the time for China to accelerate the building of its SOI ecosystem.

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Slides 3 and 7 from the IBM presentation at the 2014 Shanghai FD-SOI Forum (Courtesy: IBM)

Foundry Business Opportunities by Paul Colestock, Sr. Director of Segment Marketing, GlobalFoundries has not yet been posted as of this writing. But keep checking back – it should be there soon.

Also, look for another ASN post on the Shanghai 2014 RF-SOI Workshop coming up shortly.


Special thanks to the folks at the SOI Consortium for their help in compiling details for this piece.

* A tip of the hat to Eric Esteve at Semiwiki for first pointing this out in his recent piece on Wave Semi’s technology, which you can read here.


FD-SOI: The Best Enabler for Mobile Growth and Innovation

The following in-depth analysis, an IBS study entitled How FD-SOI will Enable Innovation and Growth in Mobile Platform Sales, concludes that the benefits of FD-SOI are overwhelming for mobile platforms through Q4/2017 based on a number of key metrics. In fact, FD-SOI has the ability to support three technology nodes, which can mean a useful lifetime through 2020 and beyond for digital designs and through 2030 for mixed-signal designs. Here are some of the highlights from the study.

First, let’s consider the markets we’re addressing.

The unit volume of smartphones and tablet computers is projected to reach nearly 3B units in 2020 worldwide. These mobile platforms need to have access to low-cost and low-power semiconductor products, including application processors and modems. Performance must also be enhanced, but this needs to be done within the cost and power consumption constraints.

Mobile platforms need essentially the same performance as notebook computers, but have to rely on much smaller battery capacity. They also need to support high-performance graphics and ever-greater data rates, including the support of 1Gbps when the 5G protocol is tested in 2018. Better cameras demands high-performance image signal processing. 3-D imaging, now under development, will require multiple image sensors. All of this needs to be accommodated with lower power consumption and lower cost.

It is significant that a high percentage of smartphones and tablet computers will be manufactured byChinese companies. Semiconductor technologies that increase battery lifetime without incurring additional costs or potentially providing lower cost can be very attractive to smartphone vendors.

The market requirements are clear, and our detailed analysis of various technology options, including bulk CMOS at 28nm and 20nm and FinFET at 16/14nm, shows FD-SOI is the best option for supporting the requirements of high-volume mobile platforms.


FinFET Realities

FinFETs have the potential to be in high volume in the future: the key issue is timing. Our analysis indicates that FinFETs have high design costs, along with high product costs. It is not realistic to expect FinFETs to be effective for the low-cost and low-power modems, application processors, and other processor engines for mobile platforms in 2016 and 2017.

FinFETs need to go through two phases in the 2015 to 2016 time frame to reach the point where they are suitable for low power and low cost applications.

In the first phase, they will be used in high-performance products such as processors for servers, FPGAs, graphics accelerators, and other similar product categories. This approach was used in the past for new-generation process technologies, where price premiums were obtained from the initial products. The time frame for the high-performance phase of 16/14nm FinFETs within the foundry environment can be 2015, 2016, and potentially 2017.

The high-performance phase can allow extensive characterization of the 16/14nm process and provide a good understanding of various categories of parasitic so that product yields can become high. There is also the need to establish design flows so that new products can be brought to the market within short design windows. The high priced product phase can position 16/14nm FinFETs to be potentially used in high volume, low cost products at a future time.

The second FinFET phase comprises the ramp-up to high volumes for high end processor engines for mobile platforms. High-end mobile platforms, including tablet computers and smartphones, can provide relatively high volumes for FinFET products if costs are competitive. Modems, application processors, and graphics functionality will be suited to the 16/14nm FinFETs from the foundries in the 2017 to 2018 time frame.

This type of methodical approach in solving the manufacturing challenges at 16/14nm can be applied to 10nm and 7nm FinFETs. There is the need to establish design flows that can yield high gate utilization as well as the ability to obtain high parametric yields. The time frame for the high-volume, low-cost phase of FinFETs can potentially be 2017 or 2018.

With the delays in ramping 16/14nm FinFETs into high volume until potentially 2017 or 2018, an alternate technology is needed to support the next phase of the mobile platform IC product supply, which can give low power consumption and low cost.


FD-SOI: Competitive Positioning

 To provide visibly into the options for technology selection, IBS has analyzed projected wafer costs and gate costs for bulk CMOS, FD-SOI, and FinFETs. Considerations include processing steps, masks, wafer costs, die shrink area, tool depreciation and parametric yield. The results are shown in the following figures.

 wafercosts (2)  gatecosts (2)

Processed wafer cost comparison for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)

Gate cost comparison  for FD-SOI, bulk CMOS and bulk FinFETs at the 28nm through 16/14nm nodes. (Source: IBS)


The low cost per gate of 28nm wafers in Q4/2016 and Q4/2017 allows this technology node to have a long lifetime. The performance of 28nm FD-SOI is 30% higher compared to 28nm bulk CMOS, with leakage also being 30% lower. There are, consequently, significant benefits in using 28nm FD-SOI compared to 28nm bulk CMOS for the high volume cost- and power-sensitive applications.

 Furthermore, the performance of 28nm FD SOI is 15% better than 20nm bulk CMOS, giving 28nm FD-SOI a potentially even longer lifetime.

 The gate cost of 20nm FD-SOI is 20%  lower than 20nm bulk CMOS, while offering 40% lower power. and 40% higher performance. The higher cost per gate of 20nm bulk CMOS compared to 20nm FD-SOI is due to the higher number of processing and masking steps. There are also parametric yield penalties at 20nm because of difficulties in controlling leakage. Fabless companies that choose 20nm bulk CMOS over 20nm FD-SOI (called 14nm by STMicroelectronics) risk to find themselves with a noncompetitive platform.

 14nm FD-SOI (called 10nm by STMicroelectronics) has an almost 30% lower cost per gate than 14nm FinFETs (including 16nm FinFETs) in Q4/2017, which is a major advantage in price-sensitive applications. Power consumption and performance are expected to be comparable between two technologies.


Why the hesitation in using FD-SOI?

While we clearly see that the benefits of FD-SOI, we also recognize that there is an expectation in the semiconductor industry that Intel sets the bar, so if Intel is doing FinFETs, everyone else should, too. The financial metrics of Intel are, however, different from those applicable to the fabless-foundry ecosystem. Intel is obtaining large revenues from its data center processors. And even though the company has promoted its 14nm and Tri-Gate processors for mobile platforms, Intel’s success in this arena has not been outstanding to date. Intel has, however, delayed the high-volume production of its 14nm Tri-Gate from Q4/2013 to H1/2015 because of low yields. The yield challenges that Intel is experiencing at 14nm should be a warning to fabless-foundry companies of the difficulties in ramping 16/14nm FinFETs within relatively short time frames.

Nonetheless, the manufacturing ecosystem is committed to making FinFET successful, so the resources that have been committed to FD-SOI have been limited. There is also reluctance to admit that the decision to adopt FinFET was premature and a thorough analysis of the cost penalties was not done. A similar perspective applies to 20nm bulk CMOS in following the industry pattern for not having a thorough review of the cost and performance impact.


FD-SOI for High-Volume Applications

The benefits of FD-SOI are clear, and as the yield and cost problems related to 20nm bulk CMOS and 16/14nm FinFETs become clearer, it is expected that there will be increased momentum to adopt FD-SOI at 28nm, 20nm (14nm by STMicroelectronics), and 14nm (10nm by STMicroelectronics).

To recap, FD-SOI provides the following benefits for high-volume mobile multimedia platforms:

  • At 28nm, FD-SOI has lower gate cost than bulk CMOS HKMG through Q4/2017.
  • 28nm FD-SOI performs 15% better than 20nm bulk CMOS HKMG.
  • At 20nm, FD-SOI has lower power consumption than bulk CMOS and lower cost per gate, (about 20% lower in Q4/2017). FD-SOI also has lower power consumption or higher performance compared to bulk CMOS.
  • Shrinking FD-SOI to 14nm yields about 30% lower gate cost in Q4/2017 than 16/14nm FinFET, with comparable performance and power consumption levels.

At 28nm, 20nm, and 14nm technologies, IBS concludes that FD-SOI is superior to competitive offerings for smartphones and tablet computers, and the advantages of FD-SOI extend through Q4/2017. As the supply base for FD-SOI strengthens, FD-SOI is expected to become a key part of the semiconductor supply chain ecosystem for high-volume applications such as smartphones and tablet computers.

The ecosystem in the semiconductor industry should focus on the technologies that optimize the benefits for customers.