Tag Archive high-resistivity


First SOI wafers based on Smart Cut tech produced in China, target strong 200mm SOI demand in smart power, RF, automotive

Shanghai-based Simgui has produced the company’s first 200mm SOI wafers based on Soitec‘s Smart CutTM manufacturing technology (read the press release here). Samples will be going to customers in the coming weeks for qualification, with high-volume ramp planned for early 2016. Simgui will be selling the wafers directly to its own customers in China, and manufacturing on an OEM basis for Soitec customers worldwide. This includes manufacturing Soitec’s fabulously successful RFeSI90 substrates for LTE-A, 5G and Gigabit Wi-Fi in smartphones and other devices (read about those here), substantially increasing worldwide capacity to meet the recent rapid rise in demand.


Simgui’s first 200mm SOI wafer manufactured using Soitec’s Smart Cut technology. (Courtesy: Simgui)

While overall worldwide 200mm wafer demand (including bulk and epi) has slipped a bit over the last year (they’re now accounting for a little over a quarter of all wafer sales), demand is increasing for certain types of 200mm SOI wafers. What’s driving it? RF and smart power (both of which are seeing big opps in automotive). SOI wafer leader Soitec, for example, is seeing an uptick of 20% in 200mm SOI wafers for smart power for automotive. RF is growing even faster.

The thick and thin of it

What’s different about these 200mm SOI wafers? It’s a question of layer thickness, quality and the manufacturing technology used to make them. Simgui and many others have been producing very “thick” 200mm SOI wafers for years. Traditionally in “thick” SOI (which has been used in things like power, aerospace, automotive, MEMS and sensors for decades), the top silicon might be up to anywhere from 2 µm to 300 µm thick, with an insulating box layer in the range of 3 µm (sometimes much more). But new apps in smart power and RF, for example, need a very high quality top silicon layer that might be as thin as 0.145µm for power*, or under 0.1µm for RF. The insulating layer also needs to be far thinner, and the bottom supporting layer also has to fulfill specific, advanced parameters.

(Bear in mind that these wafers for RF and smart power are still relatively thick compared to what you need for FD-SOI, for example, which is considered “ultra-thin”, and has ultra-uniform top silicon with a thickness in the range of 10-20 nm (0.01 – 0.02µm).)


This graphic explains which SOI wafers are used for which applications, correlating top silicon and insulating buried oxide layer thicknesses.

There are several different manufacturing approaches to fabricating SOI wafers. To make the SOI wafers needed for new markets in smart power and RF, Simgui has opted to use Soitec’s Smart Cut technology (which is well-explained here). Smart Cut’s especially good for producing very high-quality wafers, with a thin and very uniform top layer of silicon and a thin layer of insulating buried oxide (BOx).

The new deal

Simgui is a high-tech company in Shanghai focused on supplying SOI wafers and providing foundry services for epi wafers. It was spun off from the Shanghai Institute of Microsystem and Information Technology (SIMIT) within the Chinese Academy of Sciences (CAS) and now is a joint venture with a group of investors from Silicon Valley. Both its SOI and epi businesses are growing dramatically.

With a surge in demand for leading-edge thick 200mm SOI wafers, Simgui partnered with Soitec, the industry’s SOI wafer leader, back in May 2014 (see that press release here).


Simgui’s Fab-3 in Shanghai, where the company is manufacturing 200mm SOI wafers for power & RF using Soitec’s Smart Cut technology.

The May 2014 deal was a licensing and technology transfer agreement under which Simgui would manufacture Soitec’s 200-mm SOI wafers using Soitec’s proprietary Smart Cut™ technology. The news now is that it’s actually happened. Simgui has established a high-volume SOI manufacturing line to directly supply the Chinese market. In addition, Simgui will manufacture Soitec’s 200 mm SOI wafers for the global market outside China, expanding Soitec’s supply to customers worldwide in the growing RF and power markets. Beyond this initial cooperation, the two companies are expanding their collaborative efforts in the future to take advantage of their synergies.

China markets and beyond

Roughly a third of the fabs in China are 200mm (see SEMI’s map below). As recently noted by IC Insights, “Fabs running 200mm wafers will continue to be profitable for many more years and be used to fabricate numerous types of ICs, such as specialty memories, image sensors, display drivers, microcontrollers, analog products, and MEMS-based devices.”


Current map of fabs by wafer diameter in China (as of April, 2015, Courtesy: SEMI)

The Soitec-Simgui partnership addresses two key areas: 1. China’s growing demand and 2. the need for an increase in worldwide production capacity for 200-mm SOI wafers used in fabricating semiconductors for RF and power applications. It’s also seen as a key element in establishing an SOI ecosystem in China.

Dr. Xi Wang, chairman of the board of directors of Simgui, notes that, “China is a hot spot for the IC industry today. The fast growth of China’s mobile devices demands a large number of SOI wafers. Through the collaboration with Soitec, Simgui has successfully demonstrated a strong technical ability and expanded capacity to meet our customers’ needs. In addition to the planned high-volume manufacturing of SOI wafers, we will continue to promote the SOI ecosystem in China and build a globally influential Chinese silicon industry.”

It’s also good news for Soitec’s 200mm SOI customers. “We are very pleased to have reached this major milestone with Simgui, which now has the capability to manufacture Soitec’s SOI products using our Smart Cut technology. This represents a key step in our commitment to increase capacity in response to the needs of our customers who serve the fast-growing RF and power markets, both in China and worldwide,” said Paul Boudre, CEO and chairman of the board of Soitec.

Which explains why the two companies see it as a win-win situation.


LTE-A/5G: Bring it on. Next-gen Soitec eSI90 wafers predict & improve RF performance.

The folks at SOI wafer maker Soitec have announced an amazing update to their RF wafer line-up, with what they’re calling their eSI90 substrate (read the press release here). As you might expect, it improves on their terrifically successful line of substrates for the RF chips in smartphones and other mobile devices. And now with this latest substrate, they’ve developed metrology that allows designers to predict the linearity of finished RF devices, ensuring they meet the demands for next-gen networks.

SOI wafers for RF are mainly 200mm (8”) in diameter. Soitec CEO Paul Boudre says they’ll continue to run at full capacity in 2015-2016. Additional wafers will also be available through Soitec’s partnership with Simgui in China.

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

(Courtesy: Soitec. (C) photo Christian Morel / www.morel-photos.com)

How successful is this line? “Today, we estimate that more than one billion RF devices are produced each quarter using our eSI wafers,” says Dr. Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit.  That’s for 2G, 3G and now 4G and LTE.

But with the advent of LTE-Advanced (aka LTE-A), 5G and Wi-Fi 802.11.ac (aka Gigabit Wi-Fi), RF designers need a whole lot more linearity in finished devices. That’s where eSI90 comes in.

Why? We’re looking at a 10x increase in smartphone data traffic (much of it due to high-def video) between 2013 and 2018, with average connection speeds jumping from 4Mbps to 7 Mbps.


SOI wafers. (Courtesy: Soitec)

But to achieve the throughput needed, designers are faced with draconian linearity requirements and far more complex front-end modules (FEM). The wafer substrate they start on has a major impact on the performance level of the final devices.

Seeing this coming, a few years ago Soitec teamed up with experts at the Université catholique de Louvain (UCL). Leveraging Soitec’s Smart Cut™technology, they developed and industrialized the addition of a “trap-rich” layer in high-resistivity (HR) SOI wafers (if you missed it, they wrote an excellent ASN piece explaining the technical details at the time – you can read it here).

The first generation of these trap-rich HR SOI wafers, which Soitec called eSI (for enhanced Signal Integrity), was a tremendous success from the get-go. Designers loved that the wafers enabled relaxed design rules, reduced process steps and gave them highly competitive performance and die cost, including a smaller area per function (well explained here).

So here’s what’s new about the new eSI90 wafers: they exhibit higher effective resistivity than first-generation eSI wafers, enabling a 10-decibel (dB) improvement in linearity performance in RF front-end modules to address the stringent new requirements of LTE-A smart phones.

Those eSI90 SOI wafers are designed to improve the RF performance of mobile communication components such as high-linearity switches and antenna tuners that are integrated in high-end smart phones for LTE-A networks using carrier aggregation. This enables multiple LTE carriers to be used together, providing higher data rates to enhance user experience.

To ensure that the new wafers would deliver on their promise, the Soitec team developed a new metrology metric, the Harmonic Quality Factor (HQF), to predict the expected RF linearity of finished ICs. We’ll have a more in-depth explanation of how this works coming up in ASN from the Soitec team. But for now, designers will appreciate that HQF correlates with the second harmonic distortion value of a coplanar waveguide deposited on the substrate. The new eSI90 wafers’ HQF maximum value is set to -90 decibel- milliwatts (dBm) compared to -80 dBm for first-generation eSI substrates. The lower limit on eSI90 wafers enables chipmakers to take advantage of design and process improvements to increase the RF performance of their chip designs and to meet MIMO (Multi-Input Multi-Output) and Carrier Aggregation LTE-A requirements, providing faster data connections.

The new eSI90 substrates are already under evaluation at leading chipmakers and foundries. Production-ready samples are now available from Soitec.

When it comes to next-gen mobile design, innovation really does start at the substrate level.


SOITEC and UCL boost the RF performance of SOI substrates

Soitec and a team from UCL have been working together to identify the technological opportunities to further improve the high-frequency performance of SOI substrates. Based on the wideband characterization techniques developed at UCL, the RF characteristics of high-resistivity (HR) SOI substrates have been analyzed, modeled and greatly improved in order to meet the specifications of wireless communication standards.

In 2003, UCL demonstrated the possibility of further improving the RF performance of HR-SOI substrates by minimizing or even eliminating the so-called parasitic surface conduction inherent in any oxidized silicon substrate [1]. UCL proposed a figure of merit, the effective resistivity, which helps compare the RF performance of various technological solutions as well as monitoring in-line the quality of fabricated substrates.

The effective resistivity accounts for the wafer inhomogeneities (i.e., oxide covering and space charge effects) and corresponds to the resistivity that a uniform (without oxide nor space charge effects) silicon wafer should have in order to sustain identical RF substrate losses. In other words, it is the value of the substrate resistivity that is actually seen by the coplanar devices.

Therefore, comparing the wafers in terms of their effective resistivity allows us to isolate the performance of the substrate by eliminating series losses and skin effect inside conductors. The interest of the effective resistivity as a factor of merit is not limited to the monitoring of the RF quality of the fabricated substrate but it is also a physical parameter which is used by RF designers to properly model the impact of the substrate.

A new substrate is born

Soitec and UCL have been working together to identify the technological opportunities to still further improve the high-frequency performance of commercially available HR-SOI substrates. Thanks to the introduction of an engineering substrate handle, Soitec can now provide a new flavor of HR-SOI called eSI, for enhanced Signal Integrity (see Figure 1) substrate (previously named Trap Rich) with a measured effective resistivity as high as 10 kOhm.cm [2].

New generation of HR-SOI substrate

Figure 1. A new generation of HR-SOI substrate: enhanced Signal Integrity (eSI) (Image courtesy of Soitec)

This high-resistivity characteristic, which is conserved after a full CMOS process, translates to very low RF insertion loss (< 0.15 dB/mm at 1 GHz) along CPW lines and purely capacitive crosstalk similarly to quartz substrate. It has been demonstrated that the presence of a trap-rich layer does not alter the DC or RF behavior of SOI MOS transistors [3].

Besides the insertion loss issue along interconnection lines, the generation of harmonics in the Si-based substrates has been investigated. HR-SOI substrate presents reduced harmonics compared with standard SOI substrate and the introduction of engineering eSI substrate handle leads to harmonics levels well below the wireless communication systems [4] (see Figure 2).

Harmonic distortion along a 2,146 µm-long CPW line

Figure 2. Harmonic distortion along a 2,146 µm-long CPW line when a signal at 900 MHz is injected at the input for a trap-rich HR-SOI wafer from SOITEC. The specification (specs straight line) for the harmonic distortion corresponds to that of RF switches for GSM/EDGE transmitter modules [5].

The improvement of the HR-SOI substrate brings also clear benefits for the integration of passives, such as the quality factor of spiral inductors or tunable MEMS capacitors, for the reduction of the substrate noise (crosstalk) between devices integrated on the same chip, etc.

Thanks to the introduction of eSIengineered substrate handle, the HR-SOI substrate can really be considered as a lossless Si-based substrate. eSI HR-SOI technology opens the path to further system integration in the Front End Module space as well as even more complex mixed-signal System-on-Chip (SoC).



A BIT OF HISTORYFor over 15 years, UCL’s Raskin research group has been developing high-frequency characterization techniques, which are today widely used by industry as well as other research teams. The group has been measuring advanced MOS devices (fully and partially depleted SOI transistors, FinFETs, Ultra-Thin Body and BOX (UTBB) devices, silicon nanowires, Junctionless multiple gate MOSFETs, etc.) from international research centers and companies.

UCL's Welcome platform

Figure 3. UCL’s Welcome platform: electrical characterization room of 350 m2.

The experimental platform known as “Welcome” at UCL (see video) is equipped with the latest electrical measurement equipment covering on-wafer measurements over a wide frequency range (DC up to 110 GHz) and temperature range (4K up to 300°C). UCL also has 1,000 m² in cleanroom facilities, including an SOI CMOS process (see Figure 4).

UCL's Winfab

Figure 4. UCL’s Winfab has 1000 m² of class M1 cleanroom facilities

In 1997, Prof. J.-P. Raskin presented pioneering work on the RF performance of HR-SOI substrates [6]. This paper demonstrated the great interest of HR-SOI substrates to reduce RF losses as well as the crosstalk in Si-based substrates.

In 2005, the team demonstrated the possibility creating HR-SOI substrates characterized with an effective resistivity as high as 10 kOhm.cm thanks to the introduction of a high density of traps at the BOX/HR-Si handle substrate [3]. Those traps originated from the grain boundaries in a thin (300 nm-thick) layer.

In 2011, with former PhD student Dr. Mostafa Emam, the team launched a spin-off company, Incize (www.incize.com), which offers RF electrical characterization services.


[1]    D. Lederer, F. Brunier, C. Desrumaux and J.-P. Raskin, “High Resistivity SOI substrates: how high should we go?”, IEEE International SOI Conference, Newport Beach Marriott Newport Beach, CA, USA, September 29 – October 2, 2003, pp. 50-51.

[2]    K. Ben Ali, C. Roda Neve, A. Gharsallah and J.-P. Raskin, “RF SOI CMOS technology on commercial trap-rich high-resistivity SOI wafer”, IEEE International SOI Conference – SOI’12, Napa, CA, USA, October 1-4, 2012, pp. 112-113.

[3]    D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity”, IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, November 2005.

[4]    C. Roda Neve and J.-P. Raskin, “RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates”, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 924-932, April 2012.

[5]    M. Carroll et al., “High-Resistivity SOI CMOS Cellular Antenna Switches,” CSIC 2009, October 2009, Greensboro, NC, pp. 1-4.

[6]    J.-P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, “Substrate Crosstalk reduction using SOI technology”, IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2252-2261, December 1997.