Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it briefly in a SemiWiki piece last month entitled FDSOI As a Multi-Node Platform, which you can read here). The chips can operate down to 0.4V, and consume 1/10th of the power of previous generations.
If you’ve been reading ASN right along, you might already know about it, from our piece last year on the Semicon Europa (’14) Low Power Conference (read it here). At the time, Renesas talked about a demo they’d done of a 32 bit CPU on 65nm SOTB (aka Silicon on Thin Box, which is a planar FD-SOI technology) with back bias that operates eternally (!!) with ambient indoor light.
Renesas has roots with Hitachi, which was an early SOTB/FD-SOI innovator. In fact, here at ASN we had a Hitachi/Renesas piece in ASN on SOTB back in 2006 (read it here), highlighting work they’d presented at IEDM in 2004. Then in 2010, Dr. Sugii, who’s a very highly respected researcher, wrote in ASN advocating SOTB for older nodes (read that here). So this has been in the works for a while. Does this not put these companies in an incredibly strong position for IoT?
Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.
This year’s program includes:
The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.
Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris
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The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928
October 5th thru 8th, 2015
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There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes.
Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm – and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them.
The four most significant reasons to change to this solution now rather than later are that hybrid SOTB:
1. cuts power and leakage in half
2. gets threshold voltage (Vt) and variability under control
3. is fully compatible with current bulk design is easy to manufacture.
4. is easy to manufacture. Read More
Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More
Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation.
In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research Laboratory demonstrated that the planar FDSOI devices fabricated on SOTB have the smallest Vth variability among planar CMOS due to low-dose channel and back bias control. Read More
Breakthrough SOI News at VLSI Symposia
Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond.
Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node. Read More