Tag Archive Hitachi

ByGianni PRATA

Renesas Coming Out with 65nm FD-SOI chips (but they call it SOTB), says EETimes Japan

Renesas Electronics will be coming out with chips built on 65nm FD-SOI technology by spring of 2016, reports EETimes Japan (see article in Japanese here, or a version translated by Google here). Although the story dates from February 2015, it has barely been covered in the English-speaking press. (FD-SOI expert Ali Khakifirooz talked about it briefly in a SemiWiki piece last month entitled FDSOI As a Multi-Node Platform, which you can read here). The chips can operate down to 0.4V, and consume 1/10th of the power of previous generations.

If you’ve been reading ASN right along, you might already know about it, from our piece last year on the Semicon Europa (’14) Low Power Conference (read it here). At the time, Renesas talked about a demo they’d done of a 32 bit CPU on 65nm SOTB (aka Silicon on Thin Box, which is a planar FD-SOI technology) with back bias that operates eternally (!!) with ambient indoor light.

Renesas has roots with Hitachi, which was an early SOTB/FD-SOI innovator. In fact, here at ASN we had a Hitachi/Renesas piece in ASN on SOTB back in 2006 (read it here), highlighting work they’d presented at IEDM in 2004. Then in 2010, Dr. Sugii, who’s a very highly respected researcher, wrote in ASN advocating SOTB for older nodes (read that here). So this has been in the works for a while. Does this not put these companies in an incredibly strong position for IoT?

ByFanny Rodriguez

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.

S3Sadvprgmpic_lowres

Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:

S3S15lineup

The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.

ByAdministrator

The FD-SOI Papers at IEDM ’13

FD-SOI was a hot topic at this year’s IEEE International Electron Devices Meeting (IEDM) (www.ieee-iedm.org), the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

The FD-SOI papers featured high performance, low leakage, ultra-low power (0.4V),  excellent variability, reliability and scalability down to the 10 nm node using thin SOI and thin BOX substrate. Performance boosters using high mobility materials such as thin strain Si, Ge, and III-V on-Insulator were also presented.

Brief summaries of the FD-SOI papers, culled from the Advance Program (and some of the actual papers) follow.

9.2 High Performance UTBB FDSOI Devices Featuring 20nm Gate Length for 14nm Node and Beyond (STMicroelectronics, Leti, IBM, Renesas, Soitec, GlobalFoundries) 

This was the big paper reporting on ST’s flavor of high-performance FD-SOI (UTBB, which stands for ultra-thin-body-and-box) with 20nm gatelength, which target the 14nm node. In addition to excellent results, the paper demonstrated that  “…FD-SOI reliability is superior to Bulk devices.”

ST_IEDM13table1
[8] C. Auth, et al, VLSI, p.131, 2012 [9] C.-H. Jan, et al, IEDM, p.44, 2012

 

Specifically, the alliance reports, for the first time, on high performance UTBB FD-SOI devices with a gate length (LG) of 20nm and BOX thickness (TBOX) of 25nm, featuring dual channel FETs (Si channel NFET and compressively strained SiGe channel PFET). Competitive effective current (Ieff) reaches 630μA/μm and 670μA/μm for NFET and PFET, respectively, at off current (Ioff) of 100nA/μm and Vdd of 0.9V.

Excellent electrostatics are obtained, demonstrating the scalability of these devices to14nm and beyond. Very low AVt (1.3mV•μm) of channel SiGe (cSiGe) PFET devices is reported for the first time. BTI was improved >20% vs a comparable bulk device. The paper concludes with evidence of continued scalability to 10nm 

ST_IEDM13_Fig4

and below.

The effective current (Ieff), as a function of Ioff, is shown in Fig. 4. At Vdd=0.9V, NFET/PFET Ieff reach 630/670μA/μm at Ioff=100nA/μm, respectively. They are the best performing FDSOI CMOS devices reported so far, featuring non-strained Si channel NFET and strained SiGe channel PFET.”

7.3 Innovative ESD protections for UTBB FD-SOI Technology (STMicroelectronics, IMEP-LAHC)

ESD (electrostatic discharge) protection is often cited as a challenge in FD-SOI, and the ESD devices are typically put into a “hybrid” section of the chip, where the top silicon and insulator are etched away exposing the “bulk” silicon base wafer. In this paper, however, the ST-IMEP team presented FD-SOI ESD protection devices that achieve “remarkable performance in terms of leakage current and triggering control.” They demonstrate “ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V < Vt1 < 2.6V) capability. These devices rely on gate-controlled injection barriers and match the 28nm UTBB-FDSOI ESD design window by triggering before the nominal breakdown voltage of digital core MOS transistors.”

 

7.4 Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and Ultra-Thin BOX SOI MOSFETs: Impacts of Doped Well, Ambient Temperature, and SOI/BOX Thicknesses on SHE (Keio University, AIST)

This paper refutes those who say that the self-heating effect (SHE) is a bigger concern for SOI-based devices than bulk. The researchers investigated and compared bulk and SOI FETs including 6-nm ultra-thin (UT) BOX devices. They clarified, for the first time, that SHE is not negligible in bulk FETs, mainly due  to a decrease in the thermal conductivity of the more heavily doped well.  They found that the channel temperature of 6-nm UT BOX SOI FETs is close to that of bulk FETs at a chip temperature under operations. They then proposed a thermal-aware FD-SOI device design structure based on evaluated BOX/SOI thickness dependences of SHE. They concluded that SHEs in UTBB FETs with raised S/D and/or contact pitch scaling could be comparable to bulk FETs in deeply scaled nodes.

 

20.3 Gate-Last Integration on Planar FDSOI MOSFET: Impact of Mechanical Boosters and Channel Orientations  (Leti, ST)

This paper presents the industry’s first “gate last” (GL) results for FD-SOI, with ultra-thin silicon body (3-5nm) and BOX (25nm).  The team successfully fabricated transistors down to the 15nm gate length, with metal-last on high-k first (TiN/HfSiON). They thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. They report excellent Ion, p=1020μA/μm at Ioff, p=100nA/μm at Vdd=0.9V supply voltage for <110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. They cite the high efficiency of the strain transfer into the ultra-thin channel (-1.5%), as evidenced by physical strain measurements by dark field holography.

 

12.4 UTSOI2: A Complete Physical Compact Model for UTBB and Independent Double Gate MOSFETs (ST, Leti)

Compact models of transistors and other elementary devices are used to predict the behavior of a design. As such, they are embedded in simulations like SPICE that designers run before actual manufacturing. In this paper, ST and Leti researchers presented a complete physical compact model called UTSOI2, which is dedicated to Ultra-Thin Body and Box FD-SOI technology, and is able to describe accurately independent double gate operation for sub-20nm nodes. It meets standard Quality and Robustness tests for circuit design applications.

12.5 Mobility in High-K Metal Gate UTBB-FDSOI Devices: From NEGF to TCAD Perspectives (Invited) (ST, Leti, U. Udine, Synopsys, Laboratoire Hubert Curien & Institut d’Optique, IBM)

This paper reviews important theoretical and experimental aspects of both electrostatics and channel mobility in High-K Metal Gate UTBB-FDSOI MOSFETs. With an eye toward optimization, the team presents a simulation chain, including advanced quantum solvers, and semi-empirical Technology Computer Assisted Design (TCAD) tools.

 

33.2 Suppression of Die-to-Die Delay Variability of Silicon on Thin Buried Oxide (SOTB) CMOS Circuits by Balanced P/N Drivability Control with Back-Bias for Ultralow-Voltage (0.4 V) Operation (LEAP, U. Tokyo)

SOTB is what Hitachi calls its flavor of FD-SOI.  The researchers point out that small-variability transistors like SOTB are effective for reducing the operation voltage (Vdd). This paper proposes the balanced n/p drivability for reducing the die-to-die delay variation by back bias for various circuits. Excellent delay variability reduction by this n/p balanced control is demonstrated at ultra-low Vdd of 0.4 V.

 

2.8: Co-Integration of InGaAs n- and SiGe p-MOSFETs into Digital CMOS Circuits Using Hybrid Dual-Channel ETXOI Substrate (IBM)

ETSOI is IBM’s flavor of FD-SOI, and this paper is about FD-SOI devices using high mobility material for boosting performance. The presenters “demonstrate for the first time on the same wafer and on the same device level a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs UTBB FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI) using double bonding.” They showed a) that it could be done; b) it’s viable hybrid high-mobility dual-channel CMOS; c) it still supports back-biasing for Vt tuning.

 

5.2 Surface Roughness Limited Mobility Modeling in Ultra-Thin SOI and Quantum Well III-V MOSFETs  (DIEGM – U. Udine)

As with the IBM paper (2.8) above, this paper is about FD-SOI devices using high mobility material for boosting performance. The abstract explains, “This paper presents a new model for surface roughness mobility accounting for the wave-function oxide penetration and can naturally deal with Hetero-Structure. Calibration with experiments in Si MOSFETs results in a r.m.s. value of the SR spectrum in close agreement with AFM and TEM measurements.” The simulated μSR in III-V UTB MOSFETs shows a weaker degradation at small channel thickness (Tw) than predicted by the T6w law observed in UTB Si MOSFETs.

Please stay tuned for a subsequent ASN post that will cover the meeting’s SOI-FinFET, RF-SOI and advanced device papers.  (The papers themselves are typically available through the IEEE Xplore Digital Libary within a few months of the conference.)

ByGianni PRATA

Get the Picture

Hitachi’s latch-up-free, SOI-based chips enable new generations of compact medical ultrasound systems.

Medical challenge

Ultrasound systems need to be smaller, more cost-effective, and higher performance – without compromising reliability.

Design challenge

Ultrasound is based on high-voltage pulses that drive transducers, which create and receive bursts of sound waves. Low-power, high-performance electronics control a complex set of amplitudes, frequencies, direction and depth-of-focus. Increasing footprint constraints are pushing designers to embed the control electronics on the pulsar IC.  Cost-effective and highly reliable solutions are required to prevent the high-voltage, analog drivers from causing fatal “latch-up” in the low-power, digital control electronics. Read More

ByErin Berard

The Moment Is Now

There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes.

Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them.

The four most significant reasons to change to this solution now rather than later are that hybrid SOTB:

1. cuts power and leakage in half

2. gets threshold voltage (Vt) and variability under control

3. is fully compatible with current bulk design is easy to manufacture.

4. is easy to manufacture. Read More

ByGianni PRATA

Breakthroughs at the IEDM

The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.

Here are a few highlights from some of the papers that presented advances in SOI-based devices and architectures at the most recent meeting (December 2008, San Francisco). Read More

ByErin Berard

Less Than Ever

Hitachi demonstrates why it has the smallest Vth variability, and identifies the remaining components of random doping fluctuation.

In a “Comprehensive Study on Vth Variability in Silicon on Thin BOX (SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation,” (N. Sugii et. al., IEDM 2008) Hitachi scientists at the Central Research Laboratory demonstrated that the planar FDSOI devices fabricated on SOTB have the smallest Vth variability among planar CMOS due to low-dose channel and back bias control. Read More

ByGianni PRATA

Breakthrough SOI News at VLSI Symposia

Breakthrough SOI News at VLSI Symposia

  • Intel presented A Scaled Floating Body Cell (FBC) Memory with
    High-k+Metal Gate on Thin-Silicon and Thin-BOX for 16-nm Technology Node and Beyond. The company said its SOI-based FBC memory cell is the smallest ever reported, and has the lowest operating voltage. It is predicted to be feasible through the 11nm node.
  • Hitachi and Renesas presented Smallest Vth Variability by Intrinsic Silicon on Thin BOX (SOTB) CMOS with Single Metal Gate. Solving threshold voltage (Vth) variability eliminates a major obstacle for nodes beyond 45nm. The companies predict this will enable SOTB to run through the end of the device miniaturization era.
By

Thin BOX: A Solution for High-Speed, Low-Power SoCs

Control of Si substrate bias in “Silicon on Thin BOX” suppresses leakage current at 45nm and beyond.

Leakage currents in MOSFETs, originating in scattering from device features, pose a serious challenge in high-performance, low-power SoCs (system-on-a-chip), which are applicable to mobile products. The situation becomes more critical at the 45nm technology node. Read More

ByGianni PRATA

Hitachi’s tiny mu-chip

Already the world’s smallest RFID chip, SOI makes the next generation far thinner than a piece of paper – while radically increasing productivity.

The next generation of Hitachi’s µ-chip (mu-chip) is poised to make a major impact on the RFID (radio frequency identification) world. Presented at the IEEE conference in February 2006, this latest version of the world’s smallest RFID chip is based on SOI technology. The result is a chip so small, so thin, that it easily leaves the others behind by at least two generations.
How small is small? Consider it this way. The µ-chip that has been in mass production since 2001 measures 0.4mm on a side – so you could hide it comfortably under a grain of salt.
The newest generation µ-chip on SOI measures 0.15mm on a side – so you could hide about a dozen of them under that same grain of salt.

How thin is thin? The current generation is 60 microns thick – about three-quarters as thick as a piece of paper, which is typically about 80 microns thick. The new generation on SOI is only 7.5 microns thick – so a stack of 10 would still be less thick than a piece of paper.
For Hitachi, these SOI-enabled smaller dimensions translate into two very important advantages:
1. Substantially lower cost of ownership.
With SOI, each device is surrounded by insulator, preventing interference between devices and enabling higher integration on an even smaller area. With the smaller chips, more fit on a wafer – in this case as much as seven times as many. That makes for dramatically lower manufacturing costs – which could potentially enable the company to break the 5-cent barrier that analysts say is needed to really launch the RFID revolution.

2. The ability to embed the chips in paper.
This opens the door to a whole new realm of applications. Anywhere paper and security considerations intersect, the new µ-chip is a very attractive contender. The extreme thinness was achieved by completely removing the supporting silicon layer, leaving only the top silicon layer in which the circuit is fabricated, and the layer of insulation beneath it.

The µ-chip is being used for animal tagging in East Asia to ensure traceability in the food supply chain. (Courtesy of Hitachi America)

Lowering costs

Until now, cost has been a major impediment to large-scale RFID deployment. The current generation µ-chip plus antenna was selling in the 10- to 15-cent range. With the massive increase in productivity enabled by the smaller chip, Hitachi should be well positioned to bring prices down further.
Says Sarah LoPrinzi, BCC Research Analyst and author of “RFID: Technology, Applications and Market Potential” (August 2006), “Hitachi’s recent announcement of the next generation of µ-chips resolves some of the technical and economic chip manufacturing issues that have impeded the development of low cost RFID tags. In the RFID industry, the magical cost-per-tag is widely thought to be $0.05/tag. Once the $0.05 barrier is overcome, item-level inventory control becomes more realistic.”

Put it in the paper

The new, ultra-thin µ-chip opens the doors to a wider range of paper-based applications, acting as an “intelligent watermark”.

As Mark Roberti, editor-in-chief of the RFID Journal, told ASN, “The value in having an ultra-thin RFID tag is that companies can embed the tag in packaging materials for product authentication and anti-counterfeiting applications without worrying that the transponder will be so visible as to make the packaging unattractive.” Retail gift certificates, labels and other paper documents would benefit from enhanced security.

To help fight counterfeiting and improve supply-chain management, Winwatch of Switzerland has IP for embedding RFID chips such as the µ into the glass, hands or axis of high-end watches. (Courtesy of Winwatch)

An obvious application might seem to be banknotes, but this is probably not for the very near-term. While embedding the newest ultra-thin µ-chip in paper currency is now entirely feasible from a technical standpoint, there still remain issues for government and public debate regarding privacy and security in the supporting infrastructure design.

But with both businesses and governments looking for more reliable, cost-effective electronic solutions for managing supply chains and preventing fraud, the tiny µ-chip should be a major player.

* Concept: Read the technical description on the Hitachi website