SOI wafer leader Soitec was awarded the Best Partnership Award by Sony Semiconductor. Soitec earned the recognition for outstanding support that has contributed to Sony’s success in the RF semiconductor market.
Soitec’s high-resistivity silicon-on-insulator (HR-SOI) wafers have long been a favorite of RF designers for 2G and 3G switches. But the company’s latest eSi substrates has taken off like wildfire, and are now used by all the major companies that make RF chips for smart phones. The eSI wafers enable much higher linearity and isolation, helping designers to address some of the most advanced LTE requirements at competitive costs. You can read more about the technical details of the wafers and how they were developed here and how they solve key challenges here.
“We are very honored to receive this award from Sony recognizing the long partnership between our companies,” said Bernard Aspar, senior vice president and general manager of Soitec’s Communication & Power Business Unit. “It demonstrates Soitec’s commitment to deliver the enabling substrates that support Sony’s RF devices business.”
Soitec has reached high-volume manufacturing of our new Enhanced Signal Integrity™ (eSI) substrates, enabling cost-effective and high-performance RF devices. They are the first ‘trap-rich’ type of material in full production, and are already used in manufacturing by most of the leading RF foundries in front-end modules for 4G and LTE mobile computing and communication applications.
This is a major addition to our Wave SOI™ family of high-resistivity (HR) wafers for wireless applications. Our HR-SOI wafers have been used by market leaders for almost a decade, successfully addressing the challenges of 2G and 3G networks. But the data transfer rates of the new generation of 4G and LTE protocols called for a new substrate solution that would help designers meet the higher linearity and increased integration requirements.
Working together, Soitec and Université catholique de Louvain (UCL) developed a technique that adds a “trap-rich” layer underneath the buried oxide, which freezes the parasitic surface conduction that’s inherent in any oxidized silicon substrate. (The technical details are explained in a related post – click here to read it.) Using a set of very specific patents, Soitec applied proprietary technology and accumulated knowledge to build the new eSI product line.
Because this layer is built at the substrate level, expensive process steps such as high-energy implant and conservative design rules are not required when designing on eSI wafers. The result is a cheaper process and potentially smaller die area per function.
The eSI substrate allows RF designers to integrate on the same chip diverse functions such as switches, power amplifiers and antenna tuners with excellent RF isolation, good insertion loss and better signal integrity than traditional technologies.
Here is a table outlining some of the major performance advances in front-end module integration that the eSI substrate enables:
The adoption of RF-SOI wafers for RF switches in handsets is now over 65 percent (Source: Yole Développement). The first RF-SOI power amplifiers and integrated front-end modules are being well received and gaining momentum in the market. Based on current levels of adoption and performance, increasing use of RF-SOI wafers for integrated front-end modules is expected to follow the same adoption rate as seen with switches.
Looking back over the mobile revolution, we have seen the ever-increasing pressure on smart phone and device manufacturers to support increased demand for data traffic. Moving forward requires the contributions of all players along the value chain, including substrate manufacturers.
SOI substrates are playing a major role in RF applications. Soitec’s eSI product, developed and fine tuned over the past few years, is now qualified by several key customers and is already being used in volume production of mobile handsets on today’s market. Together, we are enabling the cost-effective integration of more and more functions as well as higher data throughput, smaller size, better reliability, improved performance and lower system cost.
NOTE: This article was largely excerpted from a white paper entitled Innovative RF-SOI Wafers for Wireless Applications. To download the complete white paper, click here.
ST reports on highly integrated SRAM and RF on 300mm wafers. Yield matches bulk with improved FOM.
Wireless communications systems may soon replace personal computers as a key driver of volume manufacturing.
A full CMOS 65nm Partially Depleted Low Power (LP) SOI technology has been developed at STMicroelectronics on high resistivity (HR) (› 1kOhm-cm) 300mm SOI wafers provided by Soitec. This latest work is the first to prove that 300mm HR SOI can match bulk yield, with improved figures of merit (FOM) of both digital and RF circuits, for high-volume wireless applications Read More
Optimization of RF circuits for high-resistivity SOI substrates facilitates multi-mode, multi-standard terminals integration.
The new generations of multi-mode, multistandards terminals increase the need to integrate digital, analog and RF functions on the same substrates using a System-on- Chip (SoC) approach. Silicon-on-Insulator (SOI), which can use high-resistivity (HR) wafers ( > 1000 ohms.cm) for the mechanical, supporting substrate (below the buried oxide), is enabling breakthroughs in designing RF circuits and integrating them with low-power, low-voltage digital. Read More
When an RF chip is built on a bulk silicon substrate, the semiconducting properties of the silicon induce RF signal loss in the substrate. These capacitive and resistive losses negatively impact energy management.
The semiconducting properties of the silicon also induce transmission of parasitic interferences (crosstalk) (see Figure 1). Usage of an SOI substrate improves significantly the high- frequency behavior of the chip: first, because the buried insulating layer reduces part of the electromagnetic field propagation; second, because bonded SOI technology enables the use of a highly resistive (intrinsic silicon) handle wafer, dramatically reducing both resistive losses and crosstalk. Read More