Tag Archive IBM

ByAdele Hars

SOI Consortium at Key China Events in May: World Semiconductor Congress (Nanjing) and SOI Academy/FD-SOI Training (Shanghai)

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd & 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.)

QR code for WCS, Nanjing ’19

At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information.

Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat.

QR code for SOI Academy and FD-SOI Training, Shanghaid 2019

The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.

We’ve got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.

ByAdele Hars

World’s New Fastest Supercomputer? That’s FinFETs-on-SOI in Action.

The CPUs in Summit, the world’s new fastest supercomputer are built on 14nm FinFET-on-SOI technology. Yes, those IBM Power9 CPUs are fabbed by GlobalFoundries (you’ll also find them in the z14, the most recent in IBM’s z-series of servers – a series that’s been on various iterations of SOI since its launch in 2003, btw). Summit’s at the U.S. Department of Energy’s Oak Ridge National Laboratory (ORNL) in Tennessee, USA. It is now the top US supercomputer, and it’s for science.

The IBM-built Summit currently claims the spot in the Top500 as the world’s smartest and most powerful supercomputer. “It is capable of performing 200 quadrillion calculations per second — or 200 petaflops — making it the fastest in the world,” says IBM’s Dr. John E. Kelly, III, SVP, Cognitive Solutions and IBM Research. “But this system has never been just about speed. Summit is also optimized for AI in a data-intense world. We designed a whole new heterogeneous architecture that integrates the robust data analysis of powerful IBM Power CPUs with the deep learning capabilities of GPUs. The result is unparalleled performance on critical new applications.”

And if that’s not impressive enough for you, it’s also #5 on the Green500 list for the world’s most energy-efficient computers, posting Power Efficiency (GFlops/watts) of 13.889.

Summit supercomputer nodes: The IBM-built Summit supercomputer is the world’s smartest and most powerful AI machine. It consists of 4,600 individual nodes. Each node contains two 22-core 3.07GHz IBM POWER9 CPUs, which are built on GlobalFoundries’ 14nm HP FinFET-on-SOI technology, as well as six NVIDIA Telsa GPUs. (Photo Credit: ORNL).

As GF noted when they announced the technology in the fall of 2017 (read the GF press release here), their 14HP is the industry’s only technology to integrate a FinFET transistor architecture on SOI. Featuring a 17-layer metal stack and more than eight billion transistors per chip, the technology leverages embedded DRAM and other innovative features to deliver higher performance, reduced energy, and better area scaling over previous generations to address a wide range of deep computing workloads.

These technologies have long, deep histories (and were developed in close collaboration with SOI wafer leader Soitec). Here at ASN we have a fabulous archive of pieces contributed by IBM explaining the genesis of the technology – they’re great reads and still entirely pertinent:

The IBM POWER9 processor delivers unprecedented speeds for deep learning and AI workloads. IBM Engineer, Stefanie Chiras tests the IBM Power System server in Austin, Texas. (Photo Credit: Jack Plunkett/Feature Photo Service for IBM).

As ORNL noted in its press release (you can read it here), the first projects will apply machine learning and AI to astrophysics, materials science, cancer research and systems biology.

BTW, Summit also has a slightly smaller sister machine called Sierra, going in at the Lawrence Livermore National Laboratory (part of the Department of Energy’s National Nuclear Security Administration). With 4,320 nodes (each  also containing two 22-core 3.07GHz IBM POWER9 CPUs, which are built on GlobalFoundries’ 14nm HP FinFET-on-SOI technology, but just four NVIDIA Telsa GPUs), Sierra’s claimed the #3 spot on the June 2018 Top500 list of the world’s most powerful supercomputers.

And the Power 9 is now finding it’s way into major data centers – like Google’s (read about that here). There have been some good pieces in the press about it, including in Forbes and The Motley Fool.  So yes, clearly there are exciting markets for FinFETs on SOI!


Interview (part 2 of 2): Leti Is a Catalyst for the FD-SOI Ecosystem. CEO Marie Semeria Explains Where They’re Headed


Leti CEO Marie Semeria (photo ©Pierre Jayet/CEA)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie-Noelle Semeria shares her insights here in part 2 of this exclusive ASN interview as to what Leti’s doing to drive the ecosystem forward. (In part 1, she shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)

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ASN: In which areas do you see SOI giving designers an edge?

MS: There is an advantage in terms of cost and power, so it’s attractive for IoT, for automotive, and more and more for medical devices. We see the first products in networks, in imaging, in RF. The flexibility of the design, thanks to the back bias gives another asset in terms of integration and cost. We consider that 28nm FD-SOI and 22nm FD-SOI are the IoT platforms, enabling many functions required by IoT applications. It’s a very exciting period for designers, for product managers, for start-ups. You can imagine new applications, new designs, and take advantage of engineered substrates combined with planar FD-SOI CMOS technology and 3D integration strategies to explore new frontiers.


Leti’s home at the Minatec Innovation Campus in Grenoble boasts 10,000m² of clean room space. Here we see Leti’s mobile clean room, which they call the LBB ( for Liaison Blanc Blanc) carrying wafers from one clean room to another. (photo credit: P.Jayet/CEA)

ASN: What is Leti doing moving forward?

MS: Our commitment is to create value for our partners. So what is key for SOI now is to extend the ecosystem and to catch the IoT wave, especially for automotives, manufacturing and wearables. That’s why we launched the Silicon Impulse Initiative (SII) as a single entry gate providing access to FD-SOI IP and technology. SII is a consortium, gathering Soitec, ST, CMP, Dolphin and others, in order to beef up the EDA and design ecosystems. Silicon Impulse offers multi-project wafer runs (MPWs) with ST and GF as foundries based on a full portfolio of IPs. SII is setting up the ecosystem to make FD-SOI technology available for all the designers who have IP in bulk or in FinFET. To reach designers, we have set up events close to international conferences like DAC and VLSI, and we promote SII together with the SOI Consortium in San Francisco, Taiwan, Shanghai, Dresden….

The second way we are accelerating the deployment of FD-SOI technology in manufacturing is to provide our expertise to the companies who made the choice for FD-SOI technology. Leti assignees are working in Crolles with ST and in Dresden with GF to support the development of the technology and of specific IP such as back bias IP. The design center located in the Minatec premises is also open to designers who want to experiment with FD-SOI technology and have access to proof in silicon.

ASN: What role does Leti play in the SOI roadmap?

MS: The role of Leti is to pioneer the technology, to extend the ecosystem and to demonstrate in products the powerful ability of FD-SOI to impact new applications. Leti pioneered FD-SOI technology about 20 years ago. Soitec is a start-up of Leti, as well as SOISIC (which was acquired by ARM) in design. We developed the technology with ST, partnering with IBM, TI and universities. Now we’ve opened the ecosystem with GlobalFoundries and are considering new players. With the Silicon Impulse Initiative we are going a step further to open the technology to designers in the framework of our design center. We have had a pioneering role. Now we have to play a catalyst role in order to channel new customers toward FD-SOI technology and to enable new products.

Leti demonstrates that the FD-SOI roadmap can be expanded up to 7nm with huge performance taking advantage of the back biasing. Leti’s role is to transform the present window into a wide route for numerous applications requiring multi-node generations of technologies.


Leti is located in the heart of Minatec, an international hub for micro and nanotechnology research. The 50-acre campus is unlike any other R&D facility in Europe. (Photo credit: Pierre Jayet/CEA)

ASN: Is Silicon Impulse strictly FD-SOI, or do you have photonics, MEMS, RF-SOI…?

MS: We started with FD-SOI at 28nm because it’s available: it’s here. But as soon as the full EDA-IP ecosystem is set-up, this will be open for sure to all the emerging technologies: embedded memory (RRAM, PCM,MRAM…), 3D integration (CoolCube, Cu/Cu), imaging, photonics, sensors, RF, neuromorphic technology, quantum systems….which are developed in Leti. Having access to a full capability of demonstrations in a world class innovation ecosystem backed by a semiconductor foundry and a global IP portfolio leverages the value of SII.

ASN: Can you tell us about the arrangement with GlobalFoundries for 22nm FD-SOI? How did that evolve, and what does it mean for the ecosystem?

MS: Yes, last month we announced that we have joined GlobalFoundries’ GlobalSolutions ecosystem as an ASIC provider, specifically to support their 22FDX™ technology platform. We have worked with GlobalFoundries over the years in the frame of the IBM Alliance pre-T0 program..

In joining the GlobalSolutions ecosystem, Leti’s goal is to ensure that GF’s customers – chip designers – get the very best service from FD-SOI design conception through high-volume production. This has been in the works for a while. At the beginning of 2015, we sent a team to GlobalFoundries’ Fab 1 in Dresden to support ramp up of the platform. And now as an ecosystem partner, Leti will help their customers with circuit-design IP, including fully leveraging the back-bias feature, which will give them exceptional performance at very low voltages with low leakage.

We will be able to help a broad range of designers use all the strengths that FD-SOI brings to the table in terms of ultra-low-power and high performance, especially in 22nm IoT and mobile devices. It really is a win-win situation, in that both our customer bases will get increased access to both our respective technologies and expertise. It’s an excellent example of Leti’s global strategy.

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(This concludes part 2 of 2 in this Leti interview series. In part 1, Marie Semeria shared her insights into what makes Leti tick – if you missed it, you can click here to read it now.)


Interview: Leti Is the Moving Force Behind FD-SOI. CEO Marie Semeria Explains the Strategy (part 1 of 2)

From wafers to apps, Leti has been the moving force behind all things SOI for over 30 years. Now they’re the powerhouse behind the FD-SOI phenomenon. CEO Marie Semeria shares her insights here in part 1 of this exclusive ASN interview as to what makes Leti tick. In part 2, we’ll talk about Leti’s new projects and partnerships.

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Advanced Substrate News (ASN): You’ve been CEO of Leti for a little over a year now, but those outside the Grenoble ecosystem are just getting to know you. Can you tell us a little about yourself and how you came to Leti?


Marie Semaria, CEO, CEA-Leti

Marie Semeria (MS): My background is in physics. I did my PhD at Leti on magnetic memories. Then I joined Sagem in the framework of a technology transfer, followed by a start-up in field-emission display (FED). When I came back to Leti, I spent more than 15 years in different positions, mainly involved in microelectronics. This work included setting up the cooperation with the IBM alliance and technology program coordination, as well as preparing Leti’s future and setting up long-term projects and partnerships.

Then three years ago the CEO at CEA Tech asked me to join that organization. CEA Tech is the technology research unit of the CEA (the French Atomic Energy and Alternative Energy Commission). Leti is one of CEA Tech’s three institutes, which together are developing a broad portfolio of technologies for information/communications technologies, energy, and healthcare. So I extended what I did in Leti covering the whole domain of expertise of CEA Tech. Finally, in October 2014, I took over from outgoing Leti CEO Laurent Malier.

ASN: Can you tell us about Leti’s structure and budget? How are you different from the other big European research organizations?

MS: Leti is a leading-edge research institute. Our mission is to innovate: with industry, for industry. So 83% of our budget comes from partnerships funded by industry, or partially funded by industry and supported by the European Commission or local or national authorities. The other 17% is a grant from CEA. Our commitment is to create value. And so the business model of Leti is value-centric – value for its partners.

ASN: How do you decide what you’re going to work on? Is it your customers?

MS: Leti focuses its work on technological research. We are not an academic lab. We work closely with industry. So we share our roadmap with our industrial partners, which gives us feedback on their expectations, their visions, and helps us anticipate their needs.


Leti is located in the heart of the Minatec innovation campus in Grenoble. Minatec was founded by CEA Grenoble, INPG (Grenoble Institute of Technology) and local government agencies. The project combines a physical research campus with a network of companies, researchers and engineering schools. As such, Minatec is home to 2,400 researchers, 1,200 students, and 600 business and technology transfer experts on a 20-hectare (about 50-acre) state-of-the-art campus with 10,000 m² of clean room space. An international hub for micro and nanotechnology research, the campus is unlike any other R&D facility in Europe. (Photo: courtesy Minatec)

On another side, we have to be innovative ourselves, so we are very open to what is going on in the scientific world, sensing new trends, analyzing migrations, monitoring the emergence of new concepts. Therefore, part of Leti’s research is fed by partnerships with academic labs. And there are great opportunities to work with two divisions of CEA related to fundamental research in materials science and in life science. We have a partnership with Caltech in NEMS. We have partnerships with MIT, and with Berkeley in FD-SOI design. It is key for Leti to build on the relationships with the world’s leading international technological universities. We’re fully involved with the very active Grenoble ecosystem. There are great leveraging opportunities within MINATEC and MINALOGIC, with Grenoble-Alpes University and with the INPG engineering school in math and physics. The cooperation with the researchers at LTM is key in microelectronics and we will work with new teams at INRIA who will join us in the new software and design center located in MINATEC.

ASN: How much Leti activity is based on SOI?

MS: SOI is the differentiator for Leti in nanoelectronics. We pioneered the technology 30 years ago and boosted the diffusion and the adoption of the technology worldwide. This year we launched a new initiative named Silicon Impulse together with our partners ST, CMP, and Dolphin…to provide access to the FD-SOI technology and IP to designers. I would say about 50% of the resources of Leti is related to nano: nanoelectronics, nanosystems, nanopower, 3D integration, packaging, with silicon at the core.

All that we have developed in terms of CMOS, embedded memory, RF, photonics and MEMS, is based on SOI. So we’ve developed a complete, fully-depleted (FD) SOI platform for the Internet of Things, because you’ll need all these functions. Really, all the microelectronics activity of Leti has been based on SOI for a while now. It’s why today we continue to pioneer the technology. For example, we develop the substrates and we assess their performance with Soitec in the framework of a joint lab, which is a new strategy for both of us. We work with ST, with GlobalFoundries, to transfer the technology, to prove the substrate in their products. Now we are in a key position as a leading, innovating institute to turn our disruptive technology into products. So it’s really a turning point for us.

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Here’s a quick “official” summary of Leti:

As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Learn more at www.leti.fr. Follow them on Twitter @CEA_Leti and on LinkedIn.

Click here to read part 2 of this exclusive interview.


RF-SOI Roars Back into the Headlines

Articles about chips built on RF-SOI technology are back in the headlines. What’s driving it? Data – lots of it, and at ever higher speeds, finding its way in and out of your mobile device.

Bear in mind that we’re talking now about RF-SOI, which is not the same thing as RF in FD-SOI. These RF-SOI chips serve front-end module (FEM) functions, and are designed specifically for the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances. They handle the back-and-forth of signals between the transceiver and the antenna. Today it would be practically impossible to find a smartphone that doesn’t have an RF FEM based on RF-SOI wafer technology. And the advent of 4G/LTE/LTE-A (and next, 5G) only serves to drive this market to new heights.

(In a recent ASN post, we explained the differences between RF-SOI and FD-SOI with RF – if you missed it, you can still read it here.)

By way of background, the current RF buzz is aligning with lots of activity on the world standards stage. The ITU (International Telecommunications Union), which sets time lines and processes, has just finished up its Radiocommunication Assembly (RA-15), where it approved the IMT-2020 Resolution, paving the way for 5G mobile systems (press release here). That puts 5G rolling out in 2020. If you’re really going to connect all the things in the big IoT picture, you’re going to need a whole lot more bandwidth.

But in the meantime, driven by video, even the current move from 3G to 4G/LTE-A is massive when it comes to what your mobile device has to handle. FEM designers are working all out to accommodate this, and new generations of SOI substrates are key to making it happen.

Check out this graphic from Cisco’s Global Mobile Data Traffic Forecast Update 2014–2019 White Paper, showing a CAGR of 57% in mobile data through 2019 – so this is in the 4G to LTE-A time frame.


Cisco Forecasts 24.3 Exabytes per Month of Mobile Data Traffic by 2019 (Courtesy: Cisco VNI Mobile, 2015)


And the just-released Ericsson Mobility Report (get it here) sees a huge increase in M2M (machine-to-machine – an essential of IoT) and consumer cellular and non-cellular hitting the airwaves in the next five years.


A connected device is “…a physical object that has an IP stack, enabling two-way communication over a network interface.” (Source: Ericsson Mobility Report, November 2015.)


So, new solutions are needed, and RF-SOI is at the heart of it. Here’s a quick round-up of important pieces you won’t want to miss.

Microwave Journal

MicrowaveJcover_RFSOI_Oct15RF-SOI was the cover story and in the technical features of the October 2015 issue of the prestigious Microwave Journal (click here for that October digital edition).

Just to put it in perspective, getting published in the Microwave Journal is a holy grail for RF engineers. For over 50 years, it’s been the leading RF and microwave technology publication, with all peer-reviewed articles. So for RF-SOI to take center stage there is a blockbuster – it just doesn’t get much better than that. Here are the links:

Semiwiki goes to GF

Industry guru Scotten Jones wrote in semiwiki.com about the key role of RF-SOI in GF’s strategy. This was gleaned from a recent trip to the (ex-IBM) fab in Burlington, VT. His wrap-up, GlobalFoundries Visit – Part 2 – Waking the Sleeping Giant (see it here) provides new insight into just how important RF-SOI is for the company.

The article contains a link to the slide deck of the presentation given to them by the folks at GF. It’s tremendous – if you’re at all interested in RF-SOI, you really should look at it. You can access it directly here.

As recounted in the article, GF’s Burlington fab has shipped more than 18 billion RF-SOI devices since IBM first announced the their RF-SOI process back in 2007. They’ve had more than 1450 tape-outs. The 60,000 wafer/month RF-SOI market is driven by tuner and switch apps. By virtue of putting these apps on SOI rather than using III-V materials, they reduce costs and are able to integrate key logic and control functionality.

(Source: semiwiki.com and GlobalFoundries)

Check out this GF slide showing the massive growth they’re projecting:


(Source: semiwiki.com and GlobalFoundries)

And here’s the roadmap that says it all:


(Source: semiwiki.com and GlobalFoundries)

(Source: semiwiki.com and GlobalFoundries)

Elsewhere in the news, there have also been a number of new RF-SOI-based products announced. We’ll be expanding on those in the ASN Buzz, so stay tuned!


RF-SOI vs. FD-SOI with RF – What’s the difference?

Is RF-SOI the same thing as RF on FD-SOI? No, it’s not. However, the runaway success of RF-SOI and the growing list of recent announcements related to FD-SOI with integrated RF has lead to some confusion in the press and social media. The two are different technologies, addressing different markets, and built on two very different types of SOI wafers. The use of one technology or the other depends on the requirements of the targeted RF application.

For the non-technical reader, here is a bit of basic background. At the most simplistic level – RF: radio frequency – is part of the analog family, and as such is all about waves. And when you talk about waves, you talk about losses over distance (attenuation), speed, wavelength and frequency – which is why the RF design has a rep of being something of a black art. The distance to cover, the power envelope and the amount of data to carry over that distance (and of course, the cost) determine the chip solutions. An important part of the RF chip solution is the choice of the wafer substrate itself.

So here’s a quick primer to help sort out what’s what. Please bear in mind, though, that this is a fast-evolving world, so what you’re about to read is not a definitive and forever what’s what – but more of a general (and simplified) “this is how it is currently shaking out”.

RF-SOI – Talk to the Tower

When it comes to using your mobile device for data transmission over a 2G, 3G, 4G/LTE/LTE-A (and next, 5G) network, you still need dedicated RF front-end modules (FEMs). FEMs handle the back-and-forth of signals between the transceiver and the antenna. They contain multiple parts, including switches, power amplifiers, antenna tuning, power management and filters. Traditionally, they were built on gallium arsenide substrates. But more and more, the multiple chips in FEM chipsets are being reduced to single SOCs built on a special class of high-resistivity SOI wafers. This is the realm of RF-SOI. The wafers for RF-SOI are designed specifically to handle the special needs of getting a lot of data transmitted wirelessly, often over relatively long distances.


Soitec premiered a radically new and immensely successful generation of RF-SOI substrates in 2013: the enhanced Signal Integrity™(eSI) family, which introduced the concept of the “trap-rich” layer developed at UCL. (Image courtesy of Soitec)

The latest standards (LTE-A and 5G) raise the stakes ever higher, requiring mobile devices to support more bands, higher frequency bands, and emission and reception on adjacent bands with downlink and uplink carrier aggregation. (Carrier aggregation refers to the simultaneous reception of multiple frequency bands to improve data throughput.)

For RF designers, that means choosing substrates that favor low RF loss and high RF linearity. A couple of years ago, SOI leader Soitec, in partnership with UCL, brought breakthrough RF-SOI wafer technology to the market (read about that here). Now, a few generations later, Soitec estimates that one billion RF devices are produced each quarter using their advanced and enhanced Signal Integrity™(eSI)wafers for RF. In fact it would be nigh near impossible to find a smartphone that doesn’t have an RF FEM based on  RF-SOI wafer technology.

Here at ASN, we’ve covered many of the leaders in RF-SOI FEMs over the last few years. Click on any of these names to get an idea of what they’re doing: IBM (now part of GlobalFoundries), Peregrine, SkyWorks, TowerJazz, ST, Qorvo, Sony, Qualcomm, Grace, Toshiba and MagnaChip. To learn more about the latest developments in wafer technology for RF-SOI, click here. With demand soaring, Soitec’s most advanced RF-SOI wafers are now also being produced by Simgui in China – read about that here.

In fact, the cover story and technical features of the October 2015 issue of the prestigious Microwave Journal is dedicated to RF-SOI – click here to read it.

So in terms of terminology, that’s “RF-SOI”. Now let’s look at how RF on FD-SOI is different.

RF in FD-SOI – for digital integration

When we talk about RF in FD-SOI, we’re typically talking about some RF functionality being integrated into SOCs that are essentially digital processors. True, you can integrate RF functionality into an SOC built on planar bulk (it’s generally agreed to be a nightmare in bulk FinFETs, though). But you can integrate RF into your digital SOC much more easily, efficiently and with less power if you do it in FD-SOI.

RF/analog has a (well-deserved) rep of being the most challenging part of chip design. Analog/RF devices are super sensitive to voltage variations. The digital parts of a chip, which have strong, sudden signal switching, can raise havoc with nearby analog/RF blocks. This means that the analog/RF designers have to care acutely about gain, matching, variability, noise, power dissipation, and resistance. They use all kinds of specialized techniques: FD-SOI makes their job a lot easier (good explanation in slide 8 here). What’s more, FD-SOI’s analog performance far exceeds bulk.

What sort of chips are we talking about? For now, we’re talking about processors for mobile devices, for IoT, for automotive, for consumer electronics. When we say “RF in an FD-SOI SOC”, we’re currently talking about chips that are connecting over a relatively short distance to a nearby box or device (<100m for local WiFi, or a few meters for Bluetooth or Zigbee, for example).

ST’s new set-top-box processors on 28nm FD-SOI (read about them here) are a great example. They are the first on the market integrating 4×4 802.11ac Wi-Fi (using IP from Quantenna) and High Dynamic Range support. This means the set-top boxes can reliably serve lots of HD video via WiFi to multiple users throughout the house (hopefully ending the cry: “Who’s hogging all the Wifi?!?”). ST credits their 28nm FD-SOI silicon technology with providing that highly-efficient RF, state-of-the-art WiFi performance and robustness required for reliable video delivery inside the home.

For RF on FD-SOI – as in other FD-SOI apps – designers use SOI wafers with ultra-thin silicon, ultra-thin insulating BOX and phenomenal top silicon thickness uniformity. These wafers are not the special high-resistivity wafers used in RF-SOI. Rather, they are the latest generations of the same (amazing!) FD-SOI wafers that Soitec introduced in 2010. (For an excellent, in-depth interview with the Soitec FD-SOI wafer guru on the supply chain and the most recent developments, click here.)


The top silicon uniformity of Soitec’s “FD-2D” wafers for FD-SOI is guaranteed to within +/-5Å at all points on all wafers. 5 Å across a wafer is equivalent to 5 mm over 3,000 km, which corresponds to approximately 0.2 inches over the distance between Chicago and San Francisco. That uniformity is maintained not just across each wafer, but from one wafer to the next. The BOX thickness is 10nm to 25nm, depending on the customer’s approach.

This is the type of wafers that GloFo, ST, Samsung, Freescale, Sony, several other companies in Japan and many more around the world are using when they say they’re doing RF on FD-SOI. Bear in mind that this level of SOC integration is fairly new (Samsung and TSMC just announced RF integration into SOCs for the first time in 2014 on 28bulk). But using FD-SOI technology and the corresponding ultra-thin SOI wafer substrates makes life much easier for the RF folks on the design teams, gets far better performance and far lower power at a much more attractive cost.

Further ahead, FD-SOI is also a candidate for transceivers and baseband/modem SOCs, which require high-performance digital and analog/RF integration. But even with transceivers on FD-SOI, you’ll still need the FEM on RF-SOI to handle the interface.

So, that’s the current difference between RF-SOI and RF on FD-SOI.

Hope that helps to clear things up?

ByFanny Rodriguez

Great line-up planned for IEEE S3S (SOI, 3D and low-voltage — 5-8 October, Sonoma, CA). Advance Program available. Registration still open.


Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.

This year’s program includes:


The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.

Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris

Download the Advance Program

Find all the details about the conference on our website: s3sconference

Click here to go directly to the IEEE S3S Conference registration page.

Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.

S3S Conference

The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928

October 5th thru 8th, 2015

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LIgroupS3SJoin the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.

ByGianni PRATA

IBM 0.3V SOI-FinFET SRAM paper garners press attention

An IBM paper on a 14nm SOI-FinFET SRAM functional down to 0.3V has garnered press attention. The paper, entitled 14nm FinFET Based Supply Voltage Boosting Techniques for Extreme Low Vmin Operation by R.V. Joshi et al, was presented during the Symposium on VLSI Circuits in Kyoto, Japan in June. According to the abstract, the authors presented a new, “… dynamic supply and interconnect boosting techniques for low voltage SRAMs and logic in deep 14nm FinFET technologies. The capacitive coupling in a FinFET device is used to dynamically boost the virtual logic and array supply voltage, improving Vmin. Hardware measurements show a 2.5-3x access time improvement at lower voltages and a functional Vmin down to 0.3V. Results are supported by novel physics-based capacitance extraction and novel superfast statistical circuit simulations.” EETimes reported on the paper in a piece entitled “IBM Slashes Next-Gen Power” (see it here), wherein the lead author confirmed that this work was based on a 14nm SOI-FinFET architecture.

ByGianni PRATA

IBM Photonics (That’s SOI!) Ready for Cloud, Big Data Apps


Cassette carrying several hundred chips intended for 100 Gb/s transceivers, diced from wafers fabricated with IBM SOI-CMOS Integrated Nano-Photonics Technology. The dense monolithic integration of optical and electrical circuits and the scalable manufacturing process provide a cost-effective silicon photonics interconnect solution, suitable for deployment in cloud servers, datacenters, and supercomputers. (US quarter coin shown for scale.) (Courtesy: IBM)

For the first time, IBM engineers have designed and tested a fully integrated wavelength multiplexed silicon photonics chip, which the company says will soon enable manufacturing of 100 Gb/s optical transceivers (read the press release here). This will allow datacenters to offer greater data rates and bandwidth for cloud computing and Big Data applications.

Early in the program (back in 2007), IBM contributed a piece to ASN about why their photonics program is on SOI – you can read that here. (Most all photonics — except the lasers — are on SOI. You can read more ASN photonics pieces from Intel and others here.)

Silicon photonics greatly reduces data bottlenecks inside of systems and between computing components, improving response times and delivering faster insights from Big Data. IBM’s breakthrough enables the integration of different optical components side-by-side with electrical circuits on a single silicon chip using sub-100nm semiconductor technology.

IBM’s silicon photonics chips uses four distinct colors of light travelling within an optical fiber, rather than traditional copper wiring, to transmit data in and around a computing system. In just one second, this new transceiver is estimated to be capable of digitally sharing 63 million tweets or six million images, or downloading an entire high-definition digital movie in just two seconds.

IBM presented details at the recent 2015 Conference on Lasers and Electro Optics.

ByGianni PRATA

Shanghai More-Than-Moore Presentations Now Posted on SOI Consortium Website

Presentations given at the ‘Beyond Computing’ Innovative Technologies Symposium (March 2015 in Shanghai) are now available on the SOI Consortium website (click here to see the list). The Symposium covered MEMS, semiconductor manufacturing, RF and power, which are key topics for the fast growing “More than Moore” industry. The one-day, closed-door symposium was organized by members of the SOI Consortium and the Shanghai Industrial μTechnology Research Institute (SITRI) to facilitate exchanges with industry leaders in China.