ST further accelerates its FD-SOI ROs* by 2ps/stage, and reduces SRAM’s VMIN by an extra 70mV. IBM shows an apple-to-apple comparison of 10nm FinFETs on Bulk and SOI. AIST improves the energy efficiency of its FPGA by more than 10X and Nikon shows 2 wafers can be bonded with an overlay accuracy better than 250nm.
We learned all this and much more during the very successful 2014 IEEE S3S Conference.
The conference’s 40th edition (first created as the IEEE SOS technology workshop in 1975) was held in San Francisco Oct. 6-9. Dedicated to central technologies for tomorrow’s mainstream applications, the event boasted nearly 80 papers presented over 3 days covering conception, design, simulation, process and characterization of devices and circuits.
Many of the talks we heard made it very clear that the Internet-of-Things will be the next big market growth segment. It will be enabled by extremely energy-efficient and low-cost technologies in the field of RF-communications, sensors and both embedded and cloud computing. The program of the conference was very well designed to tackle these topics, starting with the short courses on Energy Efficiency and Monolithic 3D, an RF fundamentals & applications class, a MEMS hot topic session and a strong focus on ultra-low power throughout the SubVt sessions.
The interest of the participants could be seen through an increase in Short Course and Fundamentals Class participation (+20%) compared to last year.
The companies working in the field of RF communications and mobile chips were well represented, including attendees and presenters coming from Broadcom, MediaTek, Murata, Newlans, Qualcomm, RFMD, Skyworks and TowerJazz.
The SubVT portion of the conference featured an extremely strong suite of papers on advancements in subthreshold circuit design including ultra-low-voltage microprocessors, FPGAs, and analog circuits. Additionally, there were sessions on technologies which enable very low voltage computation, such as radiation testing during subthreshold operation, and efficient energy-harvesting devices to allow indefinite operation of IoT systems. A number of talks explored the future of ultra low voltage computing, presenting results from emerging technologies such as Spin Torque Transfer devices and TFETs.
The 3D integration track keeps growing in the conference and is strongly focused on monolithic 3D. A dedicated full day short course was offered again this year, as well as two joint sessions featuring several papers on process integration, design, precision alignment bonders and more. Progress is being made and a lot of interest in this technology is being generated (See the EE Times article).
Planar Fully-Depleted SOI technologies were well represented again this year, in both SOI and Sub-Vt parallel sessions. A full session was also dedicated to FinFETs.
STMicroelectronics and CEA-Leti gave us a wealth of information on:
How to improve your circuit’s efficiency by co-optimizing Vdd, poly-bias and back-gate voltage simultaneously during the circuit design. Picking the correct optimization vector enables you to gain more than 2X in speed or up to 5X in power compared to the non-optimized circuit. (P. Flatresse, “Design Strategy for Energy Efficient SOCs in UTBB FD-SOI Technology” in the “Energy Efficiency” short course). In the same presentation we saw how going to a single-well configuration can help further reduce SRAM’s VMin by 70mV (see graph to the right).
The latest updates on 14nm technology, including an additional 2ps/stage RO delay reduction since the 2014 VLSI results shown last June. This means ROs running faster than 8ps/stage at 10nA/stage of static leakage. The key elements for the 10nm node (sSOI, thinner BOX, replacement gate, next gen. ID-RSD) where also discussed. (M. Haond, “14nm UTBB FD-SOI Technology”).
In the past year we witnessed the foundry announcements for FD-SOI technology offering. Global Foundries very clearly re-stated their interest in the FD-SOI technology, claiming that 28FD-SOI is a good technology for cost sensitive mobile applications, with the cost of 28LP and the performance of 28HPP. However, GF favors a flavor of FD-SOI technology they call Advanced ET-SOI, with similar performance to 20LPM at a reduced cost.
The IEEE S3S Conference Best Paper Award went to Hanpei Koike and co-authors from the National Institute of AIST, for their paper entitled “More than An Order of Magnitude Energy Improvement of FPGA by Combining 0.4V Operation and Multi-Vt Optimization of 20k Body Bias Domains,” presented in the SubVT part of the conference. In this work, an FPGA was fabricated in the AIST SOTB (Si On Thin BOX — which is another name for FD-SOI) process, and demonstrated successful operation down to voltages at and below the minimum energy point of the circuit. A 13x reduction in Power-Delay-Product over conventional 1.2V operation was achieved through a combination of low voltage operation and flexible body-biasing, enabled by the very thin BOX.
On the FinFET side, T.B. Hook (IBM) presented a direct comparison of “SOI FinFET versus Bulk FinFET for 10nm and below”, based on silicon data. This is a very unique work in the sense that both technologies are being developed and optimized by the same teams, in the same fab, with the same ground rules, which enables a real apple-to-apple comparison. SOI comes out a better technology in terms of Fin height control (better performance and ION variability), VT mismatch (lower VMin), output conductance (better analog and low voltage perf.) and reliability. Though external stressors are expected to be more efficient in Bulk FinFETs, mobility measurements are only 10% lower for SOI PFETs and are actually 40% higher for SOI NFETs, because of the absence of doping. The devices’ thermal resistance is higher on SOI, though bulk FinFETs are not as immune to self-heating as planar bulk. Both technologies are still competitive down to the 10nm node, but looking forward, bulk’s advantages will be rendered moot by the introduction of high mobility materials and dimensions shrinking, while SOI advantages will keep getting larger.
Next year, the S3S Conference will be held October 5-8, at the DoubleTree by Hilton Sonoma Wine Country Hotel, Rohnert Park, California.
The organizing committee is looking forward to seeing you there!
Steven A. Vitale is an Assistant Group Leader in the Quantum Information and Integrated Nanosystems Group at MIT Lincoln Laboratory. He received his B.S. in Chemical Engineering from Johns Hopkins University and Ph.D. in Chemical Engineering from MIT. Steven’s current research focuses on developing a fully-depleted silicon-on-insulator (FDSOI) ultra-low-power microelectronics technology for energy-starved systems such as space-based systems and implantable biomedical devices. Prior to joining MIT-LL, Steven was a member of the Silicon Technology Development group at Texas Instruments where he developed advanced gate etch processes. He has published 26 refereed journal articles and holds 5 patents related to semiconductor processing. From 2011 to 2012 Steven was the General Chair of the IEEE Subthreshold Microelectronics Conference, and is on the Executive Committees of the AVS Plasma Science and Technology Division, the AVS Electronic Materials and Processing Division, and the IEEE S3S Conference.
Frederic Allibert received his MS degree from the National Institute for Applied Sciences (INSA, Lyon, France) in 1997 and his PhD from Grenoble Polytechnic’s Institute (INPG) in 2003, focusing on the electrical characterization of Unibond wafers and the study of advanced device architectures such as planar double-gate and 4-gate transistors. He was a visiting scientist at KAIST (Taejon, Korea) in 1998 and joined Soitec in 1999. As an R&D scientist, he implemented SOI-specific electrical measurement techniques (for thin films, multi-layers, high resistivity) and supported the development of products and technologies targeting various applications, including FD-SOI, RF, imagers, and high-mobility materials. As Soitec’s assignee at the Albany Nanotech Center since 2011, his focus is on substrate technologies for advanced nodes. He has authored or co-authored over 50 papers and holds over 10 patents.
*RO = ring oscillator
In a piece entitled Time To Look At SOI Again (you can read it here), SemiconductorEngineering Executive Editor Mark Lapedus charts the industry’s accelerating interest in SOI, including FD-SOI and FinFETs on SOI.
He notes that FD-SOI is now planned for four generations: 28nm, 20nm, 14nm and 10nm. The offering has expanded beyond ST to Samsung and GF. He quotes GF’s Mike Mendicino as saying, “We’re seeing a lot of interest from customers (for FDSOI).”
For FinFETs, he quotes Terry Hook’s IBM presentation at the recent IEEE S3S Conference, when he said that on SOI, “…the formation of the fin is blindingly simple”. (If you missed Terry’s ASN piece last year, you can read it here.)
All the presentations made at the SOI Consortium‘s Shanghai workshops on RF-SOI and FD-SOI are now being posted.
The RF-SOI posting includes presentations from IBS, ST, UCL, Skyworks, Shanghai Technology Institute, IBM, SMIC, Soitec and GlobalFoundries – click here for those.
The FD-SOI postings include presentations from IBS, ST, Synopsys, Verisilicon, Wave Semi, IBM and GlobalFoundries – click here for those.
As of this writing, most of the presentations are available – the rest will follow very shortly so check back soon if the one you want is not there yet.
The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
Some years back, European research giant CEA-Leti made a major commitment to support FD-SOI, partnering with STMicroelectronics, Soitec and IBM. Now, with the big FD-SOI foundry announcement by Samsung and STMicroelectronics, Leti’s ready to bring its vast expertise to players throughout the value chain, right up through design integration.
To learn more about the range Leti covers, you may also want to check out the “Leti Day” conferences around the world, where they showcase their technology. The next one is in Grenoble (24-26 June, registration site here), followed by an invitation-only event during Semicon West (info here), as well as events in Paris and Tokyo.
ASN recently caught up again with Laurent Malier, CEO of CEA-Leti to get his take on the ST-Samsung news. (A few months ago, we did an in-depth interview with Malier on the massive role Leti plays in the FD-SOI ecosystem — click here to read it if you missed it then).
Here are some excerpts from our conversation.
Advanced Substrate News (ASN): What does the Samsung-ST announcement mean for Leti?
Laurent Malier (LM): It means the success of our strategy. For years, we’ve been heavily investing in FD-SOI technology, committing critical scientific and technological support at each phase of FD-SOI development. We were very confident that it was the best option for balancing performance, energy efficiency and cost. In terms of technology and performance, that was very clearly demonstrated last year at CES and in Barcelona. In addition to performance you need to go into manufacturing, secure the ramp-up, secure the costs, and secure the full ecosystem. We worked very hard on all these things over the last year and a half. But the last brick was missing: securing a foundry for the second source and enlarging access to the technology. Now we have it: the ST-Samsung announcement gives us the opportunity to showcase our work and our methodology
ASN: In which areas did Leti contribute to FD-SOI development?
LM: Leti really took a global approach in the development of FD-SOI. Of course, the SOI substrate is based on a Leti invention. Device research was done by Leti teams with our ecosystem of partners at three different sites, first in Grenoble, and later at Crolles [ST] and Albany [IBM]. We were also active in the modeling (UTSOI models implemented in all EDA tools were developed by Leti) and design kit development, so that a complete design kit was available for designers. We had designers who worked for several years in order to prove the results at the circuit level. And we have several customers for whom we’re deploying the technology in their applications. So from raw material to architecture and application design, we have a global footprint.
Because FD-SOI is an enabling technology, we need to do more than support the “push” – we also need to support the “pull” in exploring applications that will benefit from this technology. This is something else we do. Leti is not only a silicon technology institute but also is focused on applications. Half of our activity looks at application opportunities – especially for telecom, IoT, healthcare, automotives and power management.
ASN: Do you see opportunities for FD-SOI in IoT?
LM: For me, the first wave of IoT will be in machine-to-machine [M2M] and process monitoring, so that’s synergistic with sensors. Because your objects are connected, you’ll greatly expand your ability to explore data. You’ll need more efficient local data processing and more efficient data transmission – so these are places for FD-SOI circuits. For companies that are interested in any part of the value chain – design, sensor integration and so forth – these are areas where we are leaders and can provide expertise. Look for more announcements coming up at Leti Days.