IEEE S3S Conference
10-13 October 2016
Hyatt Regency San Francisco Airport
IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference
Theme: Energy Efficient Technology for the Internet of Things
Late News submissions open and Advance Program available
The IEEE S3S Conference brings together 3 key technologies that will play a major role in tomorrow’s industry: SOI, 3D integration, and Subthreshold Microelectronics. The numerous degrees of freedom they allow enable the ultra-low power operation and adjustable performance level mandatory for energy-starved systems, perfectly suiting the needs of the numerous categories of connected devices commonly referred to as the Internet of Things. This natural synergy was made obvious during the talks we listened to during past editions of the conference. For this reason, we adopted “Energy Efficient Technology for the Internet of Things” as the theme of the 2016 IEEE S3S.
This theme will be present throughout the conference. It will start on October 10th with a full day tutorial addressing two important IoT-related topics: Energy Efficient Computing and Communications, and will peak during the Plenary Hot Topics session, focused on the Internet of Things, on Thursday October 13th.
We have an outstanding technical program, including a very strong list of invited speakers, all of them leading authorities from illustrious organizations.
Our Keynote speakers are decision-makers from major industries:
Several sessions will also be of particular interest to designers and technologists who want to learn about new knobs to implement in their circuits: Two tutorials, related to 3D technology and SOI design respectively and the technical sessions on SOI and Low Voltage Circuit Design.
Applications will be illustrated in our session dedicated to SOI circuit implementations.
You can look at our Advance Program to get details about the technical content of the conference, as well as the conference venue and registration.
And you still have time to actively participate by submitting a late news paper before August 31st.
The conference has a long tradition of allying technical and social activities.
This will be the case again this year with several dinners & receptions that will give us plenty of opportunities to discuss with our colleagues.
With its broad scope of technology-related applications and social-oriented environment, the S3S is an excellent venue to meet new people with different but related research interests. It is an efficient way to shed new light on your own focus area, and to sprout new ideas and collaboration themes. It is also a place where industry and academia can exchange about the application of on-going research and tomorrow’s company needs.
Deadline for Late News submissions is
August 31st, 2016
For further information, please visit our website at s3sconference.org or contact the conference manager:
Joyce Lloyd • 6930 De Celis Pl., #36
Van Nuys, CA 91406
T 818.795.3768 • F 818.855.8392 • E email@example.com
Now in its third year, the 2015 IEEE S3S Conference has evolved into the premier venue for sharing the latest and most important findings in the areas of process integration, advanced materials & materials processing, and device and circuit design for SOI, 3D and low-voltage microelectronics. World-class leading experts in their fields will come to this year’s S3S Conference to present, discuss and debate the most recent breakthroughs in their research.
This year’s program includes:
The conference also features several events tailored for socialization and peer-to-peer discussions, such as the welcome reception, the cookout and the interactive Poster & Reception Session which is a great place to meet new colleagues and learn and exchange insights on technical topics. Enjoy a light snack and a beverage of your choice while meandering around to meet and discuss technical issues with long-time colleagues and make connections with new and influential experts and decision makers in your field.
Take time to visit the local attractions of Sonoma County. Sonoma is well known for outdoor recreation, spas, golf, night life, shopping, culinary activities, arts and music and wineries. It is truly my pleasure to serve as the General Chair of the 2015 Conference. —Bruce Doris
Download the Advance Program
Find all the details about the conference on our website: s3sconference
Click here to go directly to the IEEE S3S Conference registration page.
Click here for hotel information. To be sure of getting a room at the special conference rate book before 18 September 2015.
The DoubleTree by Hilton Sonoma Wine Country, One Doubletree Drive, Rohnert Park, CA 94928
October 5th thru 8th, 2015
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Join the IEEE S3S Conference group on LinkedIn to follow the news — click here or search on LinkedIn for IEEE S3S.
The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S) is welcoming papers until May 18, 2015.
Last year, the second edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success targetting key topics and attracting even more participants than in 2013.
While paper submissions are still accepted, the 2015 edition of the conference already promises a rich content of high-level presentations.
Geoffrey Yeap from Qualcomm will open the plenary session. He will give us a broad overview of the Ultra-Low Power SoC technologies.
Invited speakers from major industries (Intel, On Semiconductor, ST, Freescale, NXP, Soitec and more) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration.
There will be two short courses again this year: One on SOI Application, and the other on Monolithic 3D.
There will also be a class on Logic devices for 28nm and beyond as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about Ultra-Low Power.
During the Rump session we will debate about the What does IoT mean for semiconductor technology?
Scope of the conference:
The Committee will review papers submitted by May 18 in the three following focus areas of the conference:
Silicon On Insulator (SOI): Ever increasing demand and advances in SOI and related technologies make it essential to meet and discuss new gains and accomplishments in the field. For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulator technology. Previously unpublished papers are solicited in all areas of SOI technology and related devices, circuits and applications.
Subthreshold Microelectronics: Ultra-low-power microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Ubiquitous sensor networks, RFID tags, implanted medical devices, portable biosensors, handheld devices, and space-based applications are among those that would benefit from extremely low power circuits. One of the most promising methods of achieving ultra-low-power microelectronics is to reduce the operating voltage to below the transistor threshold voltage, which can result in energy savings of more than 90% compared to conventional low-power microelectronics. Papers describing original research and concepts in any subject of ultra-low-power microelectronics will be considered.
3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale Integrated Circuits “orthogonally” in addition to classical 2D device and interconnect scaling. This session will address the unique features of such stacking with special emphasis on wafer level bonding as a reliable and cost effective method, similar to the creation of SOI wafers. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation.
Students are encouraged to submit papers and compete for the Best Student paper awards. Details on paper submission are given on the call for papers webpage.
Paper submission deadline: 18 May, 2015
Notification of acceptance: 07 June, 2015
Short course date: 5 October, 2015
Conference date: 5 – 8 October, 2015
More details are available on the S3S website.
The 2014 IEEE SOI-3DI–Subthreshold (S3S) Microelectronics Technology Unified Conference will take place from Monday October 6 through Thursday October 8 in San Francisco.
Last year we entered into a new era as the IEEE S3S Conference. The transition from the IEEE International SOI Conference to the IEEE S3S conference was successful by any measurement. The first year of the new conference leading-edge experts from 3D Integration, Sub-threshold Microelectronics and SOI fields gathered and we established a world class international venue to present, learn and debate about these exciting topics. The overall participation at the first year of the new conference grew by over 50%, and the overall quality and quantity of the technical content grew even more.
This year we are looking forward to continuing to enhance the content of the 2014 S3S Conference.
Short courses: Monolithic 3D & Power-Efficient Chip Tech
On Monday, Oct. 6 we will feature two Short Courses that will run in parallel. Short courses are an educational venue where newcomers can gain overview and generalists can learn more details about new and timely topics.
The short course on Monolithic 3D will be a full day deep dive into the topic of three-dimensional integration wherein the vertical connectivity is compatible with the horizontal connectivity (10,000x better than TSV). Already there are extremely successful examples of monolithic 3D Flash Memory. Looking beyond this initial application, we will explore the application of monolithic 3D to alternate memories like RRAM, CMOS systems with silicon and other channel materials like III V. In addition, a significant portion of the short course will be dedicated to the exciting opportunity of Monolithic 3D in the context of CMOS Logic.
The other short course we will offer this year is entitled Power Efficient Chip Technology. This short course will address several key aspects of power-efficiency including low power transistors and circuits. The course will also review in detail the impact of design and architecture on the energy-efficiency of systems. The short course chairs as well as the instructors are world class leading experts from the most prestigious industry and academic institutions.
The regular conference sessions will start on Tuesday Oct. 7 with the plenary session, which will feature presentations from Wall Street (Morgan Stanley Investment Banking), Microsoft and MediaTek. After the plenary session we will hear invited talks and this year’s selection of outstanding papers from international researchers from top companies and universities. The most up to date results will be shared. Audience questions and one on one interaction with presenters is encouraged.
Back by popular demand we will have 2 Hot Topics Sessions this year. The first Hot Topic Session is scheduled for Tuesday Oct. 7th and will feature exciting 3DI topics. The other Hot Topics session is scheduled for Thursday Oct 9 and will showcase new and exciting work in the area of MEMS.
Our unique poster session and reception format will have a short presentation by the authors followed by one on one interaction to review details of the poster with the audience, in a friendly atmosphere, around a drink. Last year we had regular posters as well as several invited posters with very high quality content and we anticipate this year’s poster session to be even better than last years.
We are offering a choice of two different fundamentals classes on Wednesday afternoon. One of the Fundamentals classes will focus on Robust Design of Subthreshold Digital and Mixed Circuits, with tutorials by the worlds leading experts in this field. The SOI fundamentals course is focused on RF SOI Technology Fundamentals and Applications.
Our technical content is detailed on our program webpage.
Panel discussions, cookout & more
Keeping in line with tradition, on Wednesday night we will have a hearty cook out with delicious food and drink followed by the Panel Session entitled Cost and Benefit of Scaling Beyond 14nm. Panel speakers from financial, semiconductor equipment, technology, and academic research institutions will gather along with the audience to debate this timely topic. Although Thursday is the last day of the conference we will have stimulating presentations on novel devices, energy harvesting, radiation effects along with the MEMS Hot Topic Session and Late News Session. As always we will finish the conference with the award ceremony for the best papers.
Our conference has a long tradition of attracting presenters and audience members from the most prestigious research, technology and academic institutions from around the world. There are many social events at the S3S Conference as well as quiet time where ideas are discussed and challenged off line and people from various fields can learn more about other fields of interest from leading experts.
The conference also offers many opportunities for networking with people inside and also outside ones area. The venue this year is San Francisco. We chose this location to attract the regions leading experts from Academia and Industry. If you have free time we encourage you to explore San Francisco which is famous for a multitude of cultural and culinary opportunities.
To take full advantage of this outstanding event, register before September 18!
Special hotel rates are also available from the dedicated hotel registration page.
The committee and I look forward to seeing you in San Fransisco.
– Bruce Doris, S3S General Chair
SOI-3D-Subthreshold Microelectronics Technology Unified Conference
6-9 October 2014
Westin San Francisco Airport, Millbrae, CA
Last year, the first edition of the IEEE S3S conference, founded upon the co-location of the IEEE International SOI Conference and the IEEE Subthreshold Microelectronics Conference was a great success with a 50% increase in attendance.
The conference will, this year again, hold two parallel sessions related to SOI and Subthreshold Microelectronics supplemented by a common session on 3D integration.
The 2014 edition of the conference already promises a rich content of high-level presentations.
The plenary session will host Alice Wang (MediaTek), Bruno Terkaly (Microsoft) and Mark Edelstone (Morgan Stanley Investment Banking). They will give us a broad overview of the new markets and opportunities for the upcoming years.
Invited speakers from major industries (like GlobalFoundries, SEH, ST, IBM, Rambus) and from many prestigious academic institutions will share with us their views of the ongoing technical challenges related to SOI, Sub-VT and 3D integration. The complete list of invited speakers can be seen on the program outline page of the conference website.
On the same webpage, more information is given about the various dedicated sessions.
There will be two short courses again this year: One on Power Efficiency, and the other on Monolithic 3D. There will also be a class on RF-SOI Technology Fundamentals and Applications as well as a fundamentals class on Robust Subthreshold Ultra-low-voltage Design of Digital and Analog/RF Circuits.
The Hot Topics session will, this year, be about MEMS. During the Rump session we will debate about the Cost and Benefit of Scaling Beyond 14nm.
The Committee will review papers submitted by May 26 in the three following focus areas of the conference:
Students are encouraged to submit papers and compete for the Best Student paper awards, sponsored by Qualcomm. Details on paper submission and awards are given on the call for paper webpage.
The 2014 edition of the conference will be very conveniently located in Millbrae, California, close to the San Francisco airport. The BART and Caltrain stations, within walking distance, give you access to San Francisco to the north and the Silicon Valley to the south. Conference attendants will be able to easily combine their trips with visiting colleagues in the Bay Area or touring the Golden City.
Paper submission deadline: 26 May 2014
Notification of acceptance: 23 June 2014
Short course date: 6 October 2014
Conference date: 6 – 9 October 2014
More details are available on the S3S website.
The IEEE is once again giving two of its most prestigious awards to some of the SOI and advanced substrate industry’s leading figures.
There are few greater honors in engineering than the IEEE Technical Field Awards (TFAs). And once again, people who work in advanced substrates are among the recipients of two major awards: the Andrew S. Grove award and the Daniel E. Noble Award for Emerging Technologies.
The TFAs are awarded for contributions or leadership in specific fields of interest of the IEEE. The awards consist of a bronze medal, certificate, and honorarium. They are typically announced each summer, but the actual ceremonies take place over a year later, giving the recipients time to arrange their schedules to be there.
This explains why in the summer of 2011, the 2012 award winners were announced, while the ceremonies for the 2011 winners announced in the summer of 2010 are just being held now.
The IEEE Andrew S. Grove Award honors its namesake’s lifetime achievements. It is sponsored by the IEEE Electron Devices Society, and presented to an individual for outstanding contributions to solid-state devices and technology.
As announced last year, the co-recipients of the 2011 IEEE Andrew S. Grove Award are Judy Hoyt and Eugene Fitzgerald. Professor Hoyt is with the MIT Department of Materials Science. Eugene Fitzgerald is the Merton C. Flemings-SMA Professor of Materials Science and Engineering and head of The Fitzgerald Group at MIT.
Hoyt and Fitzgerald are cited for “seminal contributions to the demonstration of Si/Ge lattice mismatch strain engineering for enhanced carrier transport properties in MOSFET devices.” Their work on “strained” silicon and its application to SOI wafers is well-known in the advanced substrates community. (Professor Fitzgerald wrote about this work in ASN5, Summer 2006.)
The 2011 Grove Award will be presented at the 2011 IEEE International Electron Devices Meeting (IEDM), which takes place in December 2011 in Washington D.C., USA.
The IEEE has also announced that 2012 Grove award will feature another SOI luminary: Jean-Pierre Colinge, Head of the Microelectronics Centre, Tyndall National Institute, Cork, Ireland. The award recognizes Dr. Colinge “For contributions to silicon-on-insulator devices and technology.” He is heralded in the industry for his seminal and continued work in multigate FETS. This paved the way for FinFET and TriGate architectures. The actual ceremony will take place at the end of 2012. Dr. Colinge and his work have been featured in many editions of ASN.
Previous Grove winners with strong ties to the advanced substrate community include Bijan Davari (IBM, 2010) and Dimitri A. Antoniadis (IBM, 2002).
The IEEE Daniel E. Noble Award for Emerging Technologies honors Dr. Daniel E. Noble, Executive Vice Chairman of the Board emeritus of Motorola. It is given for outstanding contributions to emerging technologies recognized within recent years.
The 2011 Noble Award was given to Mark L. Burgener and Ronald E. Reedy for “basic research and development of silicon on sapphire technology culminating in high-yield, commercially viable integrated circuits”. Dr. Burgener is vice president of advanced research and Dr. Reedy is the chief operating officer at Peregrine Semiconductor Corporation, San Diego, California.
In particular, the award recognizes their persistence and contributions in making silicon-on-sapphire (SOS) commercially viable for producing integrated circuits with improved speed, lower power consumption and more isolation compared to bulk silicon circuits.
The ceremony for the 2011 Noble Award took place during the IEEE/MTT-S International Microwave Symposium (MTT 2011) in June 2011 in Baltimore, MD, USA.
This summer, the IEEE also announced the winner of the 2012 Noble award: Subramanian S. Iyer, for “the development and implementation of embedded DRAM technologies.” Dr. Iyer is Distinguished Engineer & Chief Technologist, Semiconductor Research & Development Center, IBM Systems & Technology Group. He wrote about therole of SOI in “eDRAM” technology in ASN6 (December 2006). The technology is now at the heart of IBM’s latest offerings.
Highlights from the IEEE 2011 SOI Conference include presentations by ST, ARM, IBM, Intel, Leti, Peregrine, GlobalFoundries and more.
The 2011 IEEE SOI Conference, held in Tempe, AZ this past October was not one to miss. Highlights include excellent and insightful papers from ST, ARM, IBM, Intel, Leti, Peregrine and GlobalFoundries, plus many more that indicate SOI-based technologies are at the heart of many a roadmap.
Consider some of the plenary talks.
First was Competitive SOC on UTBB SOI by Thomas Skotnicki of ST Microelectronics. This was a detailed presentation on ST’s vision for planar fully depleted (FD) SOI (which he described as equivalent to a FinFET rotated by 90 degrees). Here are some of the key points:
Next up was FD-SOI Design Portability from BULK at 20nm Node by Jean Luc Pelloie of ARM. Jean Luc, who is ARM’s Director of SOI Technology, described how a Cortex M0 implementation flow was proven in 22nm SOI. He emphasized that the design migration to FD-SOI is straightforward in terms of EDA flow: the interconnects routing, parasitics are identical, and FD-SOI transistors’ electrical behavior is similar to bulk transistors.
There’s no floating-body effect, no history effect, no timing variability, he reminded attendees. Logic and memories are identical. That said, further optimization can be done to account for different electrical features at the device level. The few differences specific to FD-SOI are not design-related but more process/device-related (SPICE models, antenna effect, ESD protection, potential parasitic bipolar, and back-gate bias).
Consider the improvements in performance that ARM’s seeing on an M0 core on 20nm FD-SOI vs. 28nm bulk: 40% better at 1V, 56% at 0.9V, 81% at 0.8, and an amazing 125% better performance at 0.7V.
As SOI Consortium Director Horacio Mendez pointed out in ASN this summer, you typically expect to get about a 25% improvement in performance moving to the next node. But ARM’s showing that if you move to the next node and move to FD-SOI, you get really phenomenal results, especially at the lower supply voltages.
In the Hot Topics Session, Bruce Doris (IBM) announced new High Performance values for FD-SOI in his presentation on The Future of SOI Transistor Technology:
Integration of photonics and electronic circuits on SOI was the subject of both Yuri Vlasov’s (IBM) plenary talk, and Juthika Basak’s (Intel) Short Course.
A half-dozen excellent presentations by Leti during the short course and invited papers explored FD-SOI from many perspectives, including scaling paths, properties and challenges/solutions.
Papers from Peregrine and Soitec showed some impressive results for their new mass-produced bonded silicon-on-sapphire (BSOS) wafers for RF applications. In Strain Reduction in Silicon-on-Sapphire by Wafer Bonding BSOS films showed 56% higher electron mobility than traditional SOS; and RF switch performance in BSOS was better than GaAs PHEMTs.
J.P. Raskin (UCL), who’s doing some fascinating work, presented Sensing and MEMS Devices in Thin Film SOI MOS Technology.
And finally, a team from MIT/Lincoln Labs once again slipped in a tantalizing concept in their late paper submission entitled SOI Circuits Powered by Embedded Solar Cell.
The online version of ASN will be covering more of the papers presented at this conference in upcoming PaperLinks articles. But clearly, the 2011 IEEE SOI conference was an excellent one.
What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may trump performance for high-volume markets, however.
Our work recently presented at the 2009 IEEE SOI Conference indicates that a planar fully depleted (FD) structure on very thin-BOX (~10nm thick) is a compelling candidate. Specifically, we found that for 6T-SRAM cells at the 22nm node: