Two new products from semi equipment manufacturer Altatech: one for ultra-thin film deposition, and one for searching out nano-defects. Altatech is a division of Soitec, best known in the advanced substrates community for its leadership in SOI wafers. This part of the company, however, develops highly efficient, cost-effective inspection and chemical vapor deposition (CVD) technologies used for R&D and manufacturing of semiconductors, LEDs, MEMS and photovoltaic devices.
The company’s newest inspection system, the Orion Lightspeed™, is capable of pinpointing the size and location of nano-scale defects inside compound semiconductor materials and transparent substrates (see press release here). The new system helps to ensure the quality control of high-value engineered substrates used in several fast growing markets including high-brightness LEDs, power semiconductors and 3D ICs. Inspection is based on Altatech’s patented synchronous Doppler detection™ technology, which determines the exact size and position of defects by making direct physical measurements with resolution below 100 nm. This provides true defect sizing, as opposed to other types of inspection equipment on the market that make indirect measurements using diffracted light to calculate approximate defect sizes. It handles 200mm or 300mm substrates, with throughput of 85 and 80 wafers per hour, respectively. Beta systems have already been installed at customers’ facilities and are demonstrating excellent performance. Shipments of production units are scheduled to begin in April 2015.
The new AltaCVD 3D Memory Cell™ is the latest member of Altatech’s AltaCVD line, designed to deposit ultra-thin semiconductor films that enable the manufacturing of high-density, low-power memory ICs used throughout mobile electronics (see press release here). The new system performs atomic-layer deposition 10 times faster than conventional atomic-layer deposition (ALD) systems, helping to meet global market demands for both high-volume production and cost efficiency in fabricating advanced memories. The system is currently demonstrating its unique capabilities and performance at one of Altatech’s key customers. Production units are available.
Soitec, a leader in SOI wafers and other advanced substrates, recently announced the sale of its gallium arsenide (GaAs) epitaxy business (the Soitec Specialty Electronics subsidiary) to Intelligent Epitaxy Technology Inc (see press release here). The deal follows the previous collaboration between Soitec and IntelliEPI (see press release dated December 12, 2013).
“The sale of our gallium arsenide (GaAs) epitaxy business to IntelliEPI reflects our drive to refocus Soitec’s electronics division on its key products under its five-year Soitec 2015 program,” explained Bernard Aspar, Senior Vice President and Soitec’s Communication & Power Business Unit General Manager.
“The transaction will enable IntelliEPI to widen its customer base and penetrate to several critical GaAs application markets such as automotive radar technology. It will also enable IntelliEPI to provide best-valued products and services to all its customers with expanded manufacturing capacities from its Texas, USA location,” said Yung-Chung Kao, IntelliEPI President and CEO.
Advanced substrate leader Soitec and Intelligent Epitaxy Technology, Inc. (IntelliEPI, Taiwan) a leader in InP, GaAs, and GaSb epi wafers, have signed a collaborative agreement to better serve the GaAs market (press release here).
“We are delighted to announce the license of our technology leading to a second source for our products for our key GaAs customers ,” said Bernard Aspar, Senior Vice President and Soitec’s Communication & Power Business Unit General Manager.
“This collaborative agreement will reinforce our GaAs technology and product know-how while, at the same time, offering Soitec’s customers supply-chain security,” said Yung-Chung Kao, IntelliEPI President and CEO.
Gallium arsenide (GaAs), a III-V semiconductor, is used in the manufacture of devices such as microwave frequency ICs, monolithic microwave ICs, infrared light-emitting diodes, laser diodes, solar cells and optical windows. GaAs is often used as a substrate material for the epitaxial growth of other III-V semiconductors including InGaAs and GaInNAs.
If you say “IP” in the chip business, everyone thinks of cores and design. But in fact, the importance of intellectual property for chips can extend right down to the substrate level.
Engineered, advanced wafer substrates open new doors for designers. For example, Soitec recently announcement that we are licensing some of our Smart Stacking™ generic bonding IP related to back-side illumination (BSI) in image sensors to TSMC. This is a clear testament to the value of IP starting at the substrate level. But in fact, TSMC is not the first company licensing our portfolio for BSI: ST took a license for BSI a few years ago.
Soitec is known throughout the industry for our Smart CutTM technology, the enabler of the silicon-on-insulator (SOI) wafer revolution. Most of today’s industry-leading SOI wafers destined for chip manufacturing are made by wafer suppliers using the Smart Cut layer transfer technology. The Smart Cut technology is also behind the development of new families of standard and custom engineered wafers.
In fact, Soitec’s IP portfolio extends to over 3000 patents covering over 600 inventions, and every year, we add about 350 more patents. This gives us what is arguably the most complete advanced substrate engineering portfolio in the world.
So when speaking of Soitec’s expertise, we might think first of SOI wafers, but in fact, such IP is generic. It can be used as building blocks in leading-edge microelectronic products, applied to an array of materials covering a wide realm of applications.
For example, Smart Cut™ technology is now being leveraged by Sumitomo Electric to produce GaN substrates for high-performance LED lighting applications. Following the announcement of last year, Sumitomo is now industrializing the product and investing in Smart Cut technology.
In the case of Soitec’s Smart Stacking™ generic bonding technology, one of the earliest applications was indeed BSI image sensors, to help manufacturers to deliver increased sensitivity and smaller pixel size. But Smart Stacking will also be leveraged to dramatically improve the performance of RF products, opening new doors to future RF and 3D-integration applications.
One example of how effective our IP policy is came about in 1997 when we contracted with Shin-Etsu Handotai Co., Ltd (SEH) of Japan for SOI manufacturing using our Smart Cut technology. The manufacturing agreement helped establish SOI products made with Smart Cut technology as the global standard.
Last year, Soitec and SEH (which is the world leader in the manufacturing of silicon wafers) announced a Smart Cut™ licensing extension and expanded technology cooperation agreement. The new partnership includes an extended 10-year licensing agreement between the two companies and establishes a new level of joint technology cooperation. It will facilitate the development and wafer supply of SOI wafers to meet major market opportunities such as SOI for RF devices, FinFETs on SOI and FD-SOI.
The agreement expands the scope of the partnership between Soitec and SEH, including cross-licensing Smart Cut related patents between the two companies. SEH will now also be able to extend its Smart Cut manufacturing capabilities to other materials, a trend commonly referred to as Silicon on Anything or SOA (any material on top of which there is a thin film of plain silicon), thereby further expanding the scope of applications.
Soitec’s expertise also extends to the domain of III-V epitaxy, which is leveraged in substrates for applications like RF, power, and lighting.
Beyond microelectronics, we are leveraging and expanding our innovation portfolio in energy markets. For example, earlier this year we announced the industry’s first four-junction solar cell for concentrator photovoltaic systems. We leverage both our proprietary semiconductor-bonding (Smart Stacking™) and layer-transfer (Smart Cut™) technologies to successfully stack non-lattice-matched materials while also raising the possibility of re-using expensive materials. These cells have recently reached efficiency of 44.7%, setting the world record.
The Soitec IP portfolio now represents over 20 years of successful innovation at the substrate level. We invest around 10% of our revenue in R&D to develop and perfect breakthrough materials technologies. Our R&D teams work closely with manufacturers, as well as with laboratories such as CEA-Leti and the Fraunhofer Institute for Solar Energy Systems. We also take full advantage of the high-tech resources available in and around all of our locations worldwide.
In short, the innovations found in our substrate engineering IP portfolio are at the heart of how we lead, grow and maximize value through incremental and breakthrough solutions for the electronics and energy industries.
To drive the competitiveness of PCs, smartphones and other leading-edge devices, the electronics industry has relied for decades on the continued miniaturization of the multitude of transistors integrated in the chips at the heart of those products. However, at the tiny dimensions transistors are reaching today, conventional technology is becoming ineffective to satisfactorily combine higher transistor density, meaningful performance gains and low power consumption.
To continue scaling CMOS technology, new approaches are needed and the industry is turning to ultra-thin body, “fully depleted” (FD) transistors. These may retain a planar architecture (Fig. 1b) or go tri-dimensional (Fig.1c), in which case current flows in vertical ‘fins’ of silicon.
In both cases, in contrast with traditional technology, the current between source and drain is only allowed to flow through a very thin silicon region, defined by the geometry of the transistor. In addition, such transistors can eliminate or alleviate the need for implanting “dopant” atoms into their channel.
The physics of FD transistors allows their behavior to be greatly improved – making it possible to continue creating more complex chips with better performance and, most importantly, with power consumption kept under tight control.The semiconductor industry is introducing planar FD (also referred to as FD-SOI) starting at the 28nm node, with first IC product samples scheduled for the end of 2012. Tri-dimensional FD or FinFET, on the other hand, is expected below 20nm in foundries.
With FD technology, either planar or tri-dimensional, the transistors are either necessarily or advantageously fabricated on innovative silicon-on-insulator (SOI) starting wafers. These wafers consist of a very thin layer of crystalline silicon, separated from a silicon base by a high-quality (and optionally ultra-thin) oxide. Soitec’s Smart CutTM technology is used to produce them and is licensed to third-parties to ensure multi-sourcing options.
Top silicon and buried oxide requirements (thickness, uniformity, etc.) are different for the planar and FinFET implementations of FD transistors. Two different wafer product lines are available to serve the needs of these two technology flavors.
Planar FD technology puts tight requirements upon starting wafers to deliver all its benefits: for example, top silicon layer thickness must be uniform to just a few Angstroms. Today, Soitec’s FD-2D product line meets these needs in a cost-effective way and makes planar FD technology a reality.Figure 2 outlines the structure of a transistor fabricated from an FD-2D wafer. For the 28nm technology node, the buried oxide thickness has been set to 25nm; the ultra-thin top silicon allows fabrication of transistors with 5nm to 8nm silicon under the gate. Future generations can leverage even thinner buried oxide layers, contributing to making this technology scalable to subsequent nodes.
By enabling a planar implementation of fully depleted technology, these wafers offer the opportunity to access the benefits of FD today – there is no need to anxiously await FinFET and the 16nm/14nm technology node. Adopters of planar FD are announcing very substantial performance and leakage gains as well as impressive improvements of energy efficiency, along with exceptional performance maintained at very low power supply [Ref.1-3].
Owing to the great compatibility of planar FD with conventional CMOS, designers retain the flows and tools they would use with the latter. Furthermore, chip manufacturers use the same production lines as well as extremely similar process steps. Finally, different studies indicate that the cost of ownership of chips based on planar FD is extremely competitive compared to any alternative.
A FinFET transistor consists of one or several fins of silicon, electrically isolated from the substrate, around which the gate wraps.One solution (Figure 3a) to manufacture FinFETs consists of starting from a traditional bulk silicon wafer and completely handling fin creation and isolation through the CMOS process. The alternative (Figure 3b) is to start from a “FinFET-friendly” wafer such as Soitec’s FD-3D, which pre-defines some of the fin characteristics and, with its buried oxide, natively embeds the electrical isolation, thus simplifying the CMOS process.
Specifically [Ref. 4-5], FD-3D wafers help obtain clearly defined and reproducible fin height and width, consistent alignment of gate, source, drain and channel, and provide optimal isolation of each fin. In addition, it is possible to implement undoped fins if desired – thus cutting variability related to random dopant fluctuations.
Overall, and especially as dimensions will continue to shrink beyond the 16nm node, FD-3D wafers offer to facilitate control over key parameters of FinFETs as well as simplify the fabrication process. They represent an opportunity for chipmakers to make the most of FinFET technology in terms of power/performance ratio and leakage power at chip level. They are also a worthwhile proposition to reduce the industrialization challenges and optimize the total cost of ownership.
Looking beyond the 10nm node, technology based on germanium and III-V compounds is being actively researched. In parallel, the transition of leading-edge chip production to 450mm diameter wafers is expected for the end of this decade.
In this context, the Smart Cut™ layer transfer technology for manufacturing innovative wafers may again prove extremely valuable by enabling independent control over various optimization knobs. For example, transferring a thin layer of high-quality, optimized III-V material onto a low-cost handle wafer (silicon or other), with an optimized interfacing layer, could be an interesting option.
Fully depleted silicon technology is coming. The question is how fast and how easily this transition can be accomplished: innovative wafers provide part of the answer.
With FD-2D, they enable a planar implementation, providing the semiconductor ecosystem with an early and low-risk path towards optimal performance and power efficiency across all use cases, as soon as the 28nm node.
With FD-3D, they can help efficiently address some key challenges of FinFET technology and make the most of it.
Looking further ahead, the Smart CutTM technology will continue to simplify the implementation of the next silicon technology breakthroughs.
[Ref.1] White Paper, “Planar fully depleted silicon technology to design competitive SOC at 28nm and beyond”, STMicroelectronics – http://www.soiconsortium.org/about-soi/white-papers.php
[Ref.2] ST Ericsson Technology Blog, May 2012: “FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor – Part 2”, http://blog.stericsson.com/blog/2012/05/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-%E2%80%93-part-2-2/
[Ref.3] “MWC ST-Ericsson Media & Analyst Briefing”, February, 2012 – http://www.stericsson.com/investors/Analyst-Event-Presentation-MWC-12.pdf
[Ref.4] « SOI Value in IBM Silicon Technology », Oct.2011 – http://www.gsaglobal.org/3dic/docs/20111019_IBM_SOI_Value_GSA.pdf
[Ref.5] “SOI versus bulk-silicon nanoscale FinFETs”, Jerry G.Fossum et al., SSE Volume 54, Issue 2, Feb. 2010.
Advanced engineered substrates are a key to the Raytheon-led DARPA COSMOS project to integrate compound semiconductors and silicon CMOS on a single chip.
In what we believe to be an industry first, a Raytheon Company-led team has demonstrated the industry’s first Indium Phosphide (InP)-based heterojunction bipolar transistor (HBT) fabricated on a silicon wafer. HBTs are high-mobility, compound semiconductor (CS) transistors used primarily in RF and radar applications.
The team developed a process for directly growing a CS on a uniquely engineered silicon substrate. This innovation provides a technical approach that is creating a new class of high-performance circuits integrating CS and silicon-based CMOS on a single chip. It starts with a single wafer to enable more affordable military applications. Read More
Systems houses and research labs from seven European nations are working together on GaN HEMT technology for critical defense applications.
Defense radar and communication systems as well as wireless communication systems have a drastic need for increased RF performance and high-power, high-efficiency, high-linearity and low-cost monolithic amplifiers operating in the 1–40 GHz frequency range. Read More
Financing approved for new III-V program
The first phase of OPTIMUM, a new III-V research project lead by Thales Communications France (TCF) and partners UMS, OMMIC and Picogiga International, has recently been approved and financed. There are four sub-sections within the pro-ject. The first focuses on innovative III-V materials and technologies, in particular the optimization of GaAs substrates and the use of Smart Cut technology in future materials such as GaN and InP. Other sections focus on basic technologies such as packaging, as well as components and applications. With synergies established between the major players, the consortium expects to facilitate an expanded, world-class industrial and research pole of excellence in III-V based microelectronics and optoelectronics for the greater Paris region. •